
; 64tass Turbo Assembler Macro V1.54.1900 listing file
; 64tass --m65816 -D TARGET=1 --long-address --flat -b -o kernel.bin --list kernel.lst --labels=kernel.lbl src\kernel.asm
; Thu Dec 31 14:28:45 2020

;Offset	;PC	;Hex		;Monitor	;Source

;******  Command line definitions

=1						TARGET=1

;******  Processing input file: src\kernel.asm

=1						TARGET_FLASH = 1              ; The code is being assembled for Flash
=2						TARGET_RAM = 2                ; The code is being assembled for RAM

;******  Processing file: src\macros_inc.asm


;******  Return to file: src\kernel.asm


;******  Processing file: src\characters.asm

=$01						CHAR_CTRL_A = $01   ; CTRL-A (move to start of line)
=$03						CHAR_CTRL_C = $03   ; CTRL-C
=$05						CHAR_CTRL_E = $05   ; CTRL-E (move to end of line)
=$08						CHAR_BS = $08       ; Backspace (delete character to the left of the cursor)
=$09						CHAR_TAB = $09      ; TAB (moves cursor to next tabulated column)
=$0a						CHAR_LF = $0A       ; Line feed
=$0d						CHAR_CR = $0D       ; Carriage return
=$0f						CHAR_INS = $0F      ; Insert a space at the cursor
=$11						CHAR_UP = $11       ; Up arrow
=$1d						CHAR_RIGHT = $1D    ; Right arrow
=$20						CHAR_SP = $20       ; Space
=$91						CHAR_DOWN = $91     ; Down arrow
=$9d						CHAR_LEFT = $9D     ; Left arrow
=$7f						CHAR_DEL = $7F      ; Delete key (delete the character at the cursor)
=$81						CHAR_F1 = $81       ; Function keys
=$82						CHAR_F2 = $82
=$83						CHAR_F3 = $83
=$84						CHAR_F4 = $84
=$85						CHAR_F5 = $85
=$86						CHAR_F6 = $86
=$87						CHAR_F7 = $87
=$88						CHAR_F8 = $88
=$89						CHAR_F9 = $89
=$8a						CHAR_F10 = $8A
=$8b						CHAR_F11 = $8B
=$8c						CHAR_F12 = $8C

;******  Return to file: src\kernel.asm


;******  Processing file: src\simulator_inc.asm


;******  Return to file: src\kernel.asm


;******  Processing file: src\page_00_inc.asm

=$000000					BANK0_BEGIN      = $000000 ;Start of bank 0 and Direct page
=$000000					TMPPTR1          = $000000 ; 4 byte temporary pointer
=$000004					TMPPTR2          = $000004 ; 4 byte temporary pointer
=$000008					OPL2_ADDY_PTR_LO = $000008 ; THis Points towards the Instruments Database
=$000009					OPL2_ADDY_PTR_MD = $000009
=$00000a					OPL2_ADDY_PTR_HI = $00000A
=$00000c					SCREENBEGIN      = $00000C ;3 Bytes Start of screen in video RAM. This is the upper-left corrner of the current video page being written to. This may not be what's being displayed by VICKY. Update this if you change VICKY's display page.
=$00000f					COLS_VISIBLE     = $00000F ;2 Bytes Columns visible per screen line. A virtual line can be longer than displayed, up to COLS_PER_LINE long. Default = 80
=$000011					COLS_PER_LINE    = $000011 ;2 Bytes Columns in memory per screen line. A virtual line can be this long. Default=128
=$000013					LINES_VISIBLE    = $000013 ;2 Bytes The number of rows visible on the screen. Default=25
=$000015					LINES_MAX        = $000015 ;2 Bytes The number of rows in memory for the screen. Default=64
=$000017					CURSORPOS        = $000017 ;3 Bytes The next character written to the screen will be written in this location.
=$00001a					CURSORX          = $00001A ;2 Bytes This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
=$00001c					CURSORY          = $00001C ;2 Bytes This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
=$00001e					CURCOLOR         = $00001E ;1 Byte Color of next character to be printed to the screen.
=$00001f					COLORPOS         = $00001F ;3 Byte address of cursor's position in the color matrix
=$000022					STACKBOT         = $000022 ;2 Bytes Lowest location the stack should be allowed to write to. If SP falls below this value, the runtime should generate STACK OVERFLOW error and abort.
=$000024					STACKTOP         = $000024 ;2 Bytes Highest location the stack can occupy. If SP goes above this value, the runtime should generate STACK OVERFLOW error and abort.
=$000026					OPL2_OPERATOR    = $000026 ;
=$000027					OPL2_CHANNEL     = $000027 ;
=$000028					OPL2_REG_REGION  = $000028 ; Offset to the Group of Registers
=$00002a					OPL2_REG_OFFSET  = $00002A ; 2 Bytes (16Bits)
=$00002c					OPL2_IND_ADDY_LL = $00002C ; 2 Bytes Reserved (Only need 3)
=$00002e					OPL2_IND_ADDY_HL = $00002E ; 2 Bytes Reserved (Only need 3)
=$000030					OPL2_NOTE        = $000030 ; 1 Byte
=$000031					OPL2_OCTAVE      = $000031 ; 1 Byte
=$000032					OPL2_PARAMETER0  = $000032 ; 1 Byte - Key On/Feedback
=$000033					OPL2_PARAMETER1  = $000033 ; 1 Byte
=$000034					OPL2_PARAMETER2  = $000034 ; 1 Byte
=$000035					OPL2_PARAMETER3  = $000035 ; 1 Byte
=$000036					OPL2_LOOP        = $000036 ;
=$000036					OPL2_BLOCK       = $000036
=$000038					SDCARD_FILE_PTR  = $000038 ; 3 Bytes Pointer to Filename to open
=$00003c					SDCARD_BYTE_NUM  = $00003C ; 2Bytes
=$00003f					SDCARD_PRSNT_MNT = $00003F ; 1 Byte, Indicate that the SDCard is Present and that it is Mounted
=$000040					BM_CLEAR_SCRN_X  = $000040
=$000042					BM_CLEAR_SCRN_Y  = $000042
=$000040					RAD_STARTLINE    = $000040 ; 1 Byte
=$000041					RAD_PATTERN_IDX  = $000041 ; 1 Byte
=$000042					RAD_LINE         = $000042 ; 1 Byte
=$000043					RAD_LINENUMBER   = $000043 ; 1 Byte
=$000044					RAD_CHANNEL_NUM  = $000044 ; 1 Byte
=$000045					RAD_ISLASTCHAN   = $000045 ; 1 Byte
=$000046					RAD_Y_POINTER    = $000046 ; 2 Bytes
=$000048					RAD_TICK         = $000048
=$00004a					RAD_CHANNEL_DATA = $00004A ; 2 Bytes
=$00004c					RAD_CHANNE_EFFCT = $00004C
=$00004d					RAD_TEMP         = $00004D
=$000050					RAD_ADDR         = $000050 ; 3 bytes to avoid OPL2 errors.
=$000053					RAD_PATTRN       = $000053 ; 1 bytes - offset to patter
=$000054					RAD_PTN_DEST     = $000054 ; 3 bytes - where to write the pattern data
=$000057					RAD_CHANNEL      = $000057 ; 2 bytes - 0 to 8
=$000059					RAD_LAST_NOTE    = $000059 ; 1 if this is the last note
=$00005a					RAD_LINE_PTR     = $00005A ; 2 bytes - offset to memory location
=$000040					BMP_X_SIZE       = $000040 ; 2 Bytes
=$000042					BMP_Y_SIZE       = $000042 ; 2 Bytes
=$000044					BMP_PRSE_SRC_PTR = $000044 ; 3 Bytes
=$000048					BMP_PRSE_DST_PTR = $000048 ; 3 Bytes
=$00004c					BMP_COLOR_PALET  = $00004C ; 2 Bytes
=$00004e					SCRN_X_STRIDE    = $00004E ; 2 Bytes, Basically How many Pixel Accross in Bitmap Mode
=$000050					BMP_FILE_SIZE    = $000050 ; 4 Bytes
=$000054					BMP_POSITION_X   = $000054 ; 2 Bytes Where, the BMP will be position on the X Axis
=$000056					BMP_POSITION_Y   = $000056 ; 2 Bytes Where, the BMP will be position on the Y Axis
=$000058					BMP_PALET_CHOICE = $000058 ;
=$0000e0					MOUSE_PTR        = $0000E0
=$0000e1					MOUSE_POS_X_LO   = $0000E1
=$0000e2					MOUSE_POS_X_HI   = $0000E2
=$0000e3					MOUSE_POS_Y_LO   = $0000E3
=$0000e4					MOUSE_POS_Y_HI   = $0000E4
=$0000f0					USER_TEMP        = $0000F0 ;32 Bytes Temp space for user programs
=$000100					GAVIN_BLOCK      = $000100 ;256 Bytes Gavin reserved, overlaps debugging registers at $1F0
=$000140					INT_CONTROLLER   = $000140 ; $000140...$00015F Interrupt Controller
=$000160					TIMER_CONTROLLER = $000160 ; $000160...$00017F Timer0/Timer1/Timer2 Block
=$000160					TIMER_CTRL_REGLL = $000160 ;
=$000161					TIMER_CTRL_REGLH = $000161 ;
=$000162					TIMER_CTRL_REGHL = $000162 ;
=$000163					TIMER_CTRL_REGHH = $000163 ;
=$000240					CPU_REGISTERS    = $000240 ; Byte
=$000240					CPUPC            = $000240 ;2 Bytes Program Counter (PC)
=$000242					CPUPBR           = $000242 ;2 Bytes Program Bank Register (K)
=$000244					CPUA             = $000244 ;2 Bytes Accumulator (A)
=$000246					CPUX             = $000246 ;2 Bytes X Register (X)
=$000248					CPUY             = $000248 ;2 Bytes Y Register (Y)
=$00024a					CPUSTACK         = $00024A ;2 Bytes Stack Pointer (S)
=$00024c					CPUDP            = $00024C ;2 Bytes Direct Page Register (D)
=$00024e					CPUDBR           = $00024E ;1 Byte  Data Bank Register (B)
=$00024f					CPUFLAGS         = $00024F ;1 Byte  Flags (P)
=$000250					MONITOR_VARS     = $000250 ; Byte  MONITOR Variables. BASIC variables may overlap this space
=$000250					MCMDADDR         = $000250 ;3 Bytes Address of the current line of text being processed by the command parser. Can be in display memory or a variable in memory. MONITOR will parse up to MTEXTLEN characters or to a null character.
=$000253					MCMP_TEXT        = $000253 ;3 Bytes Address of symbol being evaluated for COMPARE routine
=$000256					MCMP_LEN         = $000256 ;2 Bytes Length of symbol being evaluated for COMPARE routine
=$000258					MCMD             = $000258 ;3 Bytes Address of the current command/function string
=$00025b					MCMD_LEN         = $00025B ;2 Bytes Length of the current command/function string
=$00025d					MARG1            = $00025D ;4 Bytes First command argument. May be data or address, depending on command
=$000261					MARG2            = $000261 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
=$000265					MARG3            = $000265 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
=$000269					MARG4            = $000269 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
=$00026d					MARG5            = $00026D ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
=$000271					MARG6            = $000271 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
=$000275					MARG7            = $000275 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
=$000279					MARG8            = $000279 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
=$000300					LOADFILE_VARS    = $000300 ; Byte
=$000300					LOADFILE_NAME    = $000300 ;3 Bytes (addr) Name of file to load. Address in Data Page
=$000303					LOADFILE_LEN     = $000303 ;1 Byte  Length of filename. 0=Null Terminated
=$000304					LOADPBR          = $000304 ;1 Byte  First Program Bank of loaded file ($05 segment)
=$000305					LOADPC           = $000305 ;2 Bytes Start address of loaded file ($05 segment)
=$000307					LOADDBR          = $000307 ;1 Byte  First data bank of loaded file ($06 segment)
=$000308					LOADADDR         = $000308 ;2 Bytes FIrst data address of loaded file ($06 segment)
=$00030a					LOADFILE_TYPE    = $00030A ;3 Bytes (addr) File type string in loaded data file. Actual string data will be in Bank 1. Valid values are BIN, PRG, P16
=$00030d					BLOCK_LEN        = $00030D ;2 Bytes Length of block being loaded
=$00030f					BLOCK_ADDR       = $00030F ;2 Bytes (temp) Address of block being loaded
=$000311					BLOCK_BANK       = $000311 ;1 Byte  (temp) Bank of block being loaded
=$000312					BLOCK_COUNT      = $000312 ;2 Bytes (temp) Counter of bytes read as file is loaded
=$000300					FDC_DRIVE        = $000300 ;1 byte - The number of the selected drive
=$000301					FDC_HEAD         = $000301 ;1 byte - The head number (0 or 1)
=$000302					FDC_CYLINDER     = $000302 ;1 byte - The cylinder number
=$000303					FDC_SECTOR       = $000303 ;1 byte - The sector number
=$000304					FDC_SECTOR_SIZE  = $000304 ;1 byte - The sector size code (2 = 512)
=$000305					FDC_SECPERTRK    = $000305 ;1 byte - The number of sectors per track (18 for 1.44 MB floppy)
=$000306					FDC_ST0          = $000306 ;1 byte - Status Register 0
=$000307					FDC_ST1          = $000307 ;1 byte - Status Register 1
=$000308					FDC_ST2          = $000308 ;1 byte - Status Register 2
=$000309					FDC_ST3          = $000309 ;1 byte - Status Register 3
=$00030a					FDC_PCN          = $00030A ;1 byte - Present Cylinder Number
=$00030b					FDC_STATUS       = $00030B ;1 byte - Status of what we think is going on with the FDC:
=$00030c					DIVIDEND         = $00030C ;4 bytes - Dividend for 32-bit division
=$000310					DIVISOR          = $000310 ;4 bytes - Divisor for 32-bit division
=$000314					REMAINDER        = $000314 ;4 bytes - Remainder for 32-bit division
=$000320					SDOS_VARIABLES   = $000320
=$000320					BIOS_STATUS      = $000320      ; 1 byte - Status of any BIOS operation
=$000321					BIOS_DEV         = $000321      ; 1 byte - Block device number for block operations
=$000322					BIOS_LBA         = $000322      ; 4 bytes - Address of block to read/write (this is the physical block, w/o reference to partition)
=$000326					BIOS_BUFF_PTR    = $000326      ; 4 bytes - 24-bit pointer to memory for read/write operations
=$00032a					BIOS_FIFO_COUNT  = $00032A      ; 2 bytes - The number of bytes read on the last block read
=$00032c					BIOS_FLAGS       = $00032C      ; 1 byte - Flags for various BIOSy things:
=$00032d					BIOS_TIMER       = $00032D      ; 1 byte - the number of 1/60 ticks for a time out
=$00032e					DOS_STATUS       = $00032E      ; 1 byte - The error code describing any error with file access
=$000330					DOS_CLUS_ID      = $000330      ; 4 bytes - The cluster desired for a DOS operation
=$000338					DOS_DIR_PTR      = $000338      ; 4 bytes - Pointer to a directory entry (assumed to be within DOS_SECTOR)
=$00033c					DOS_BUFF_PTR     = $00033C      ; 4 bytes - A pointer for DOS cluster read/write operations
=$000340					DOS_FD_PTR       = $000340      ; 4 bytes - A pointer to a file descriptor
=$000344					DOS_FAT_LBA      = $000344      ; 4 bytes - The LBA for a sector of the FAT we need to read/write
=$000348					DOS_TEMP         = $000348      ; 4 bytes - Temporary storage for DOS operations
=$00034c					DOS_FILE_SIZE    = $00034C      ; 4 bytes - The size of a file
=$000350					DOS_SRC_PTR      = $000350      ; 4 bytes - Pointer for transferring data
=$000354					DOS_DST_PTR      = $000354      ; 4 bytes - Pointer for transferring data
=$000358					DOS_END_PTR      = $000358      ; 4 bytes - Pointer to the last byte to save
=$00035c					DOS_RUN_PTR      = $00035C      ; 4 bytes - Pointer for starting a loaded program
=$000360					DOS_RUN_PARAM    = $000360      ; 4 bytes - Pointer to the ASCIIZ string for arguments in loading a program
=$000364					DOS_STR1_PTR     = $000364      ; 4 bytes - pointer to a string
=$000368					DOS_STR2_PTR     = $000368      ; 4 bytes - pointer to a string
=$00036b					DOS_SCRATCH      = $00036B      ; 4 bytes - general purpose short term storage
=$000400					DOS_PATH_BUFF    = $000400      ; 256 bytes - A buffer for path names
=$000500					FDC_PARAMETERS   = $000500      ; 16 bytes - a buffer of parameter data for the FDC
=$000510					FDC_RESULTS      = $000510      ; 16 bytes - Buffer for results of FDC commands
=$000530					FDC_PARAM_NUM    = $000530      ; 1 byte - The number of parameters to send to the FDC (including command)
=$000532					FDC_RESULT_NUM   = $000532      ; 1 byte - The number of results expected
=$000533					FDC_EXPECT_DAT   = $000533      ; 1 byte - 0 = the command expects no data, otherwise expects data
=$000534					FDC_CMD_RETRY    = $000534      ; 1 byte - a retry counter for commands
=$000700					CURRUART         = $000700 ; 3-bytes: the base address of the current UART
=$000703					CHAN_OUT         = $000703 ; 1-byte: the number of the current output channel (for PUTC, etc.)
=$000704					CHAN_IN          = $000704 ; 1-byte: the number of the current input channel (for GETCH, etc.)
=$000705					TIMERFLAGS       = $000705 ; 1-byte: flags to indicate that one of the timer interupts has triggered
=$80						TIMER0TRIGGER    = $80
=$40						TIMER1TRIGGER    = $40
=$20						TIMER2TRIGGER    = $20
=$000f00					KEY_BUFFER       = $000F00 ; 64 Bytes keyboard buffer
=$0080						KEY_BUFFER_SIZE  = $0080   ;128 Bytes (constant) keyboard buffer length
=$000f7f					KEY_BUFFER_END   = $000F7F ;  1 Byte  Last byte of keyboard buffer
=$000f83					KEY_BUFFER_CMD   = $000F83 ;  1 Byte  Indicates the Command Process Status
=$000f84					COMMAND_SIZE_STR = $000F84 ;  1 Byte
=$000f86					COMMAND_COMP_TMP = $000F86 ;  2 Bytes
=$000f87					KEYBOARD_SC_FLG  = $000F87 ;  1 Bytes that indicate the Status of Left Shift, Left CTRL, Left ALT, Right Shift
=$000f88					KEYBOARD_SC_TMP  = $000F88 ;  1 Byte, Interrupt Save Scan Code while Processing
=$000f89					KEYBOARD_LOCKS   = $000F89 ;  1 Byte, the status of the various lock keys
=$000f8a					KEYFLAG          = $000F8A ;  1 Byte, flag to indicate if CTRL-C has been pressed
=$000f8b					KEY_BUFFER_RPOS  = $000F8B ;  2 Byte, position of the character to read from the KEY_BUFFER
=$000f8d					KEY_BUFFER_WPOS  = $000F8D ;  2 Byte, position of the character to write to the KEY_BUFFER
=$001000					KERNEL_JMP_BEGIN = $001000 ; Reserved for the Kernel jump table
=$001fff					KERNEL_JMP_END   = $001FFF
=$002000					TEST_BEGIN       = $002000 ;28672 Bytes Test/diagnostic code for prototype.
=$007fff					TEST_END         = $007FFF ;0 Byte
=$008000					STACK_BEGIN      = $008000 ;32512 Bytes The default beginning of stack space
=$00feff					STACK_END        = $00FEFF ;0 Byte  End of stack space. Everything below this is I/O space
=$38ff00					ISR_BEGIN        = $38FF00 ; Byte  Beginning of CPU vectors in Direct page
=$38ff00					HRESET           = $38FF00 ;16 Bytes Handle RESET asserted. Reboot computer and re-initialize the kernel.
=$38ff10					HCOP             = $38FF10 ;16 Bytes Handle the COP instruction. Program use; not used by OS
=$38ff20					HBRK             = $38FF20 ;16 Bytes Handle the BRK instruction. Returns to BASIC Ready prompt.
=$38ff30					HABORT           = $38FF30 ;16 Bytes Handle ABORT asserted. Return to Ready prompt with an error message.
=$38ff40					HNMI             = $38FF40 ;32 Bytes Handle NMI
=$38ff60					HIRQ             = $38FF60 ;32 Bytes Handle IRQ
=$38ff80					Unused_FF80      = $38FF80 ;End of direct page Interrrupt handlers
=$38ffe0					VECTORS_BEGIN    = $38FFE0 ;0 Byte  Interrupt vectors
=$38ffe0					JMP_READY        = $38FFE0 ;4 Bytes Jumps to ROM READY routine. Modified whenever alternate command interpreter is loaded.
=$38ffe4					VECTOR_COP       = $38FFE4 ;2 Bytes Native COP Interrupt vector
=$38ffe6					VECTOR_BRK       = $38FFE6 ;2 Bytes Native BRK Interrupt vector
=$38ffe8					VECTOR_ABORT     = $38FFE8 ;2 Bytes Native ABORT Interrupt vector
=$38ffea					VECTOR_NMI       = $38FFEA ;2 Bytes Native NMI Interrupt vector
=$38ffec					VECTOR_RESET     = $38FFEC ;2 Bytes Unused (Native RESET vector)
=$38ffee					VECTOR_IRQ       = $38FFEE ;2 Bytes Native IRQ Vector
=$38fff0					RETURN           = $38FFF0 ;4 Bytes RETURN key handler. Points to BASIC or MONITOR subroutine to execute when RETURN is pressed.
=$38fff4					VECTOR_ECOP      = $38FFF4 ;2 Bytes Emulation mode interrupt handler
=$38fff6					VECTOR_EBRK      = $38FFF6 ;2 Bytes Emulation mode interrupt handler
=$38fff8					VECTOR_EABORT    = $38FFF8 ;2 Bytes Emulation mode interrupt handler
=$38fffa					VECTOR_ENMI      = $38FFFA ;2 Bytes Emulation mode interrupt handler
=$38fffc					VECTOR_ERESET    = $38FFFC ;2 Bytes Emulation mode interrupt handler
=$38fffe					VECTOR_EIRQ      = $38FFFE ;2 Bytes Emulation mode interrupt handler
=$400000					VECTORS_END      = $400000 ;*End of vector space
=$00ffff					BANK0_END        = $00FFFF ;End of Bank 00 and Direct page

;******  Return to file: src\kernel.asm


;******  Processing file: src\page_00_data.asm

>380000		00 a0 af			                .long $AFA000       ; SCREENBEGIN, 3 bytes, Start of screen in video RAM. This is the upper-left corrner of the current video page being written to. This may not be what's being displayed by VICKY. Update this if you change VICKY's display page.
>380003		4c 00				                .word 76            ; COLS_VISIBLE, 2 bytes, Columns visible per screen line. A virtual line can be longer than displayed, up to COLS_PER_LINE long. Default = 80
>380005		64 00				                .word 100           ; COLS_PER_LINE, 2 bytes, Columns in memory per screen line. A virtual line can be this long. Default=128
>380007		38 00				                .word 56            ; LINES_VISIBLE, 2 bytes, The number of rows visible on the screen. Default=25
>380009		40 00				                .word 64            ; LINES_MAX, 2 bytes, The number of rows in memory for the screen. Default=64
>38000b		00 a0 af			                .long $AFA000       ; CURSORPOS, 3 bytes, The next character written to the screen will be written in this location.
>38000e		00 00				                .word 0             ; CURSORX, 2 bytes, This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
>380010		00 00				                .word 0             ; CURSORY, 2 bytes, This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
>380012		0f				                .byte $0F           ; CURCOLOR, 2 bytes, Color of next character to be printed to the screen.
>380013		00				                .byte $00           ; CURATTR, 2 bytes, Attribute of next character to be printed to the screen.
>380014		00 80				                .word STACK_BEGIN   ; STACKBOT, 2 bytes, Lowest location the stack should be allowed to write to. If SP falls below this value, the runtime should generate STACK OVERFLOW error and abort.
>380016		ff fe				                .word STACK_END     ; STACKTOP, 2 bytes, Highest location the stack can occupy. If SP goes above this value, the runtime should generate STACK OVERFLOW error and abort.

;******  Return to file: src\kernel.asm


;******  Processing file: src\page_00_code.asm

.38ff00		18		clc		RHRESET         CLC
.38ff01		fb		xce		                XCE
.38ff02		5c 00 10 00	jmp $001000	                JML BOOT
.38ff10						RHCOP
.38ff10		c2 30		rep #$30	                REP #$30        ; set A&X long
.38ff12		8b		phb		                PHB
.38ff13		0b		phd		                PHD
.38ff14		48		pha		                PHA
.38ff15		da		phx		                PHX
.38ff16		5a		phy		                PHY
.38ff17		5c 08 10 00	jmp $001008	                JML BREAK
.38ff20						RHBRK
.38ff20		c2 30		rep #$30	                REP #$30        ; set A&X long
.38ff22		8b		phb		                PHB
.38ff23		0b		phd		                PHD
.38ff24		48		pha		                PHA
.38ff25		da		phx		                PHX
.38ff26		5a		phy		                PHY
.38ff27		5c 08 10 00	jmp $001008	                JML BREAK
.38ff30						RHABORT
.38ff30		c2 30		rep #$30	                REP #$30        ; set A&X long
.38ff32		8b		phb		                PHB
.38ff33		0b		phd		                PHD
.38ff34		48		pha		                PHA
.38ff35		da		phx		                PHX
.38ff36		5a		phy		                PHY
.38ff37		5c 08 10 00	jmp $001008	                JML BREAK
.38ff40						 RHNMI
.38ff40		c2 30		rep #$30	                REP #$30        ; set A&X long
.38ff42		8b		phb		                PHB
.38ff43		0b		phd		                PHD
.38ff44		48		pha		                PHA
.38ff45		da		phx		                PHX
.38ff46		5a		phy		                PHY
.38ff47		22 d5 18 38	jsl $3818d5	                JSL NMI_HANDLER
.38ff4b		7a		ply		                PLY
.38ff4c		fa		plx		                PLX
.38ff4d		68		pla		                PLA
.38ff4e		2b		pld		                PLD
.38ff4f		ab		plb		                PLB
.38ff50		40		rti		                RTI
.38ff60						RHIRQ
.38ff60		c2 30		rep #$30	                REP #$30        ; set A&X long
.38ff62		8b		phb		                PHB
.38ff63		0b		phd		                PHD
.38ff64		48		pha		                PHA
.38ff65		da		phx		                PHX
.38ff66		5a		phy		                PHY
.38ff67		22 14 17 38	jsl $381714	                JSL IRQ_HANDLER
.38ff6b		7a		ply		                PLY
.38ff6c		fa		plx		                PLX
.38ff6d		68		pla		                PLA
.38ff6e		2b		pld		                PLD
.38ff6f		ab		plb		                PLB
.38ff70		40		rti		                RTI
.38ffe0		5c 04 00 3a	jmp $3a0004	JUMP_READY      JML MONITOR    ; Kernel READY routine. Rewrite this address to jump to a custom kernel.
>38ffe4		10 ff				RVECTOR_COP     .addr HCOP     ; FFE4
>38ffe6		20 ff				RVECTOR_BRK     .addr HBRK     ; FFE6
>38ffe8		30 ff				RVECTOR_ABORT   .addr HABORT   ; FFE8
>38ffea		40 ff				RVECTOR_NMI     .addr HNMI     ; FFEA
>38ffec		00 00				                .word $0000    ; FFEC
>38ffee		60 ff				RVECTOR_IRQ     .addr HIRQ    ; FFEE
.38fff0		5c 05 07 39	jmp $390705	RRETURN         JML IRETURN
>38fff4		10 ff				RVECTOR_ECOP    .addr HCOP     ; FFF4
>38fff6		20 ff				RVECTOR_EBRK    .addr HBRK     ; FFF6
>38fff8		30 ff				RVECTOR_EABORT  .addr HABORT   ; FFF8
>38fffa		40 ff				RVECTOR_ENMI    .addr HNMI     ; FFFA
>38fffc		00 ff				RVECTOR_ERESET  .addr HRESET   ; FFFC
>38fffe		60 ff				RVECTOR_EIRQ    .addr HIRQ     ; FFFE

;******  Return to file: src\kernel.asm


;******  Processing file: src\Math_def.asm

=$000100					UNSIGNED_MULT_A_LO  = $000100
=$000101					UNSIGNED_MULT_A_HI  = $000101
=$000102					UNSIGNED_MULT_B_LO  = $000102
=$000103					UNSIGNED_MULT_B_HI  = $000103
=$000104					UNSIGNED_MULT_AL_LO = $000104
=$000105					UNSIGNED_MULT_AL_HI = $000105
=$000106					UNSIGNED_MULT_AH_LO = $000106
=$000107					UNSIGNED_MULT_AH_HI = $000107
=$000108					SIGNED_MULT_A_LO    = $000108
=$000109					SIGNED_MULT_A_HI    = $000109
=$00010a					SIGNED_MULT_B_LO    = $00010A
=$00010b					SIGNED_MULT_B_HI    = $00010B
=$00010c					SIGNED_MULT_AL_LO   = $00010C
=$00010d					SIGNED_MULT_AL_HI   = $00010D
=$00010e					SIGNED_MULT_AH_LO   = $00010E
=$00010f					SIGNED_MULT_AH_HI   = $00010F
=$000110					UNSIGNED_DIV_DEM_LO = $000110
=$000111					UNSIGNED_DIV_DEM_HI = $000111
=$000112					UNSIGNED_DIV_NUM_LO = $000112
=$000113					UNSIGNED_DIV_NUM_HI = $000113
=$000114					UNSIGNED_DIV_QUO_LO = $000114
=$000115					UNSIGNED_DIV_QUO_HI = $000115
=$000116					UNSIGNED_DIV_REM_LO = $000116
=$000117					UNSIGNED_DIV_REM_HI = $000117
=$000118					SIGNED_DIV_DEM_LO   = $000118
=$000119					SIGNED_DIV_DEM_HI   = $000119
=$00011a					SIGNED_DIV_NUM_LO   = $00011A
=$00011b					SIGNED_DIV_NUM_HI   = $00011B
=$00011c					SIGNED_DIV_QUO_LO   = $00011C
=$00011d					SIGNED_DIV_QUO_HI   = $00011D
=$00011e					SIGNED_DIV_REM_LO   = $00011E
=$00011f					SIGNED_DIV_REM_HI   = $00011F
=$000120					ADDER32_A_LL        = $000120
=$000121					ADDER32_A_LH        = $000121
=$000122					ADDER32_A_HL        = $000122
=$000123					ADDER32_A_HH        = $000123
=$000124					ADDER32_B_LL        = $000124
=$000125					ADDER32_B_LH        = $000125
=$000126					ADDER32_B_HL        = $000126
=$000127					ADDER32_B_HH        = $000127
=$000128					ADDER32_R_LL        = $000128
=$000129					ADDER32_R_LH        = $000129
=$00012a					ADDER32_R_HL        = $00012A
=$00012b					ADDER32_R_HH        = $00012B

;******  Return to file: src\kernel.asm


;******  Processing file: src\interrupt_def.asm

=$000140					INT_PENDING_REG0 = $000140 ;
=$000141					INT_PENDING_REG1 = $000141 ;
=$000142					INT_PENDING_REG2 = $000142 ;
=$000143					INT_PENDING_REG3 = $000143 ; FMX Model
=$000144					INT_POL_REG0     = $000144 ;
=$000145					INT_POL_REG1     = $000145 ;
=$000146					INT_POL_REG2     = $000146 ;
=$000147					INT_POL_REG7     = $000147 ; FMX Model
=$000148					INT_EDGE_REG0    = $000148 ;
=$000149					INT_EDGE_REG1    = $000149 ;
=$00014a					INT_EDGE_REG2    = $00014A ;
=$00014b					INT_EDGE_REG3    = $00014B ; FMX Model
=$00014c					INT_MASK_REG0    = $00014C ;
=$00014d					INT_MASK_REG1    = $00014D ;
=$00014e					INT_MASK_REG2    = $00014E ;
=$00014f					INT_MASK_REG3    = $00014F ; FMX Model
=$01						FNX0_INT00_SOF        = $01  ;Start of Frame @ 60FPS
=$02						FNX0_INT01_SOL        = $02  ;Start of Line (Programmable)
=$04						FNX0_INT02_TMR0       = $04  ;Timer 0 Interrupt
=$08						FNX0_INT03_TMR1       = $08  ;Timer 1 Interrupt
=$10						FNX0_INT04_TMR2       = $10  ;Timer 2 Interrupt
=$20						FNX0_INT05_RTC        = $20  ;Real-Time Clock Interrupt
=$40						FNX0_INT06_FDC        = $40  ;Floppy Disk Controller
=$80						FNX0_INT07_MOUSE      = $80  ; Mouse Interrupt (INT12 in SuperIO IOspace)
=$01						FNX1_INT00_KBD        = $01  ;Keyboard Interrupt
=$02						FNX1_INT01_SC0        = $02  ;VICKY_II (INT2) Sprite 2 Sprite Collision
=$04						FNX1_INT02_SC1        = $04  ;VICKY_II (INT3) Sprite 2 Tiles Collision
=$08						FNX1_INT03_COM2       = $08  ;Serial Port 2
=$10						FNX1_INT04_COM1       = $10  ;Serial Port 1
=$20						FNX1_INT05_MPU401     = $20  ;Midi Controller Interrupt
=$40						FNX1_INT06_LPT        = $40  ;Parallel Port
=$80						FNX1_INT07_SDCARD     = $80  ;SD Card Controller Interrupt (CH376S)
=$01						FNX2_INT00_OPL3       = $01  ;OPl3
=$02						FNX2_INT01_GABE_INT0  = $02  ;GABE (INT0) - TBD
=$04						FNX2_INT02_GABE_INT1  = $04  ;GABE (INT1) - TBD
=$08						FNX2_INT03_SDMA       = $08  ;VICKY_II (INT4)
=$10						FNX2_INT04_VDMA       = $10  ;VICKY_II (INT5)
=$20						FNX2_INT05_GABE_INT2  = $20  ;GABE (INT2) - TBD
=$40						FNX2_INT06_EXT        = $40  ;External Expansion
=$80						FNX2_INT07_SDCARD_INS = $80  ; SDCARD Insertion
=$01						FNX3_INT00_OPN2       = $01  ;OPN2
=$02						FNX3_INT01_OPM        = $02  ;OPM
=$04						FNX3_INT02_IDE        = $04  ;HDD IDE INTERRUPT
=$08						FNX3_INT03_TBD        = $08  ;TBD
=$10						FNX3_INT04_TBD        = $10  ;TBD
=$20						FNX3_INT05_TBD        = $20  ;GABE (INT2) - TBD
=$40						FNX3_INT06_TBD        = $40  ;External Expansion
=$80						FNX3_INT07_TBD        = $80  ; SDCARD Insertion

;******  Return to file: src\kernel.asm


;******  Processing file: src\dram_inc.asm

=$afa000					SCREEN_PAGE0     = $AFA000 ;8192 Bytes First page of display RAM. This is used at boot time to display the welcome screen and the BASIC or MONITOR command screens.
=$afc000					SCREEN_PAGE1     = $AFC000 ;8192 Bytes Additional page of display RAM. This can be used for page flipping or to handle multiple edit buffers.
=$b00000					SCREEN_END       = $B00000 ;End of display memory

;******  Return to file: src\kernel.asm


;******  Processing file: src\vicky_ii_def.asm

=$af0000					MASTER_CTRL_REG_L	      = $AF0000
=$01						Mstr_Ctrl_Text_Mode_En  = $01       ; Enable the Text Mode
=$02						Mstr_Ctrl_Text_Overlay  = $02       ; Enable the Overlay of the text mode on top of Graphic Mode (the Background Color is ignored)
=$04						Mstr_Ctrl_Graph_Mode_En = $04       ; Enable the Graphic Mode
=$08						Mstr_Ctrl_Bitmap_En     = $08       ; Enable the Bitmap Module In Vicky
=$10						Mstr_Ctrl_TileMap_En    = $10       ; Enable the Tile Module in Vicky
=$20						Mstr_Ctrl_Sprite_En     = $20       ; Enable the Sprite Module in Vicky
=$40						Mstr_Ctrl_GAMMA_En      = $40       ; this Enable the GAMMA correction - The Analog and DVI have different color value, the GAMMA is great to correct the difference
=$80						Mstr_Ctrl_Disable_Vid   = $80       ; This will disable the Scanning of the Video hence giving 100% bandwith to the CPU
=$af0001					MASTER_CTRL_REG_H       = $AF0001
=$01						Mstr_Ctrl_Video_Mode0   = $01       ; 0 - 640x480 (Clock @ 25.175Mhz), 1 - 800x600 (Clock @ 40Mhz)
=$02						Mstr_Ctrl_Video_Mode1   = $02       ; 0 - No Pixel Doubling, 1- Pixel Doubling (Reduce the Pixel Resolution by 2)
=$af0002					VKY_RESERVED_00         = $AF0002
=$af0003					VKY_RESERVED_01         = $AF0003
=$01						Border_Ctrl_Enable      = $01
=$af0004					BORDER_CTRL_REG         = $AF0004 ; Bit[0] - Enable (1 by default)  Bit[4..6]: X Scroll Offset ( Will scroll Left) (Acceptable Value: 0..7)
=$af0005					BORDER_COLOR_B          = $AF0005
=$af0006					BORDER_COLOR_G          = $AF0006
=$af0007					BORDER_COLOR_R          = $AF0007
=$af0008					BORDER_X_SIZE           = $AF0008; X-  Values: 0 - 32 (Default: 32)
=$af0009					BORDER_Y_SIZE           = $AF0009; Y- Values 0 -32 (Default: 32)
=$af000d					BACKGROUND_COLOR_B      = $AF000D ; When in Graphic Mode, if a pixel is "0" then the Background pixel is chosen
=$af000e					BACKGROUND_COLOR_G      = $AF000E
=$af000f					BACKGROUND_COLOR_R      = $AF000F ;
=$af0010					VKY_TXT_CURSOR_CTRL_REG = $AF0010   ;[0]  Enable Text Mode
=$01						Vky_Cursor_Enable       = $01
=$02						Vky_Cursor_Flash_Rate0  = $02
=$04						Vky_Cursor_Flash_Rate1  = $04
=$08						Vky_Cursor_FONT_Page0   = $08       ; Pick Font Page 0 or Font Page 1
=$10						Vky_Cursor_FONT_Page1   = $10       ; Pick Font Page 0 or Font Page 1
=$af0011					VKY_TXT_START_ADD_PTR   = $AF0011   ; This is an offset to change the Starting address of the Text Mode Buffer (in x)
=$af0012					VKY_TXT_CURSOR_CHAR_REG = $AF0012
=$af0013					VKY_TXT_CURSOR_COLR_REG = $AF0013
=$af0014					VKY_TXT_CURSOR_X_REG_L  = $AF0014
=$af0015					VKY_TXT_CURSOR_X_REG_H  = $AF0015
=$af0016					VKY_TXT_CURSOR_Y_REG_L  = $AF0016
=$af0017					VKY_TXT_CURSOR_Y_REG_H  = $AF0017
=$af001b					VKY_LINE_IRQ_CTRL_REG   = $AF001B ;[0] - Enable Line 0, [1] -Enable Line 1
=$af001c					VKY_LINE0_CMP_VALUE_LO  = $AF001C ;Write Only [7:0]
=$af001d					VKY_LINE0_CMP_VALUE_HI  = $AF001D ;Write Only [3:0]
=$af001e					VKY_LINE1_CMP_VALUE_LO  = $AF001E ;Write Only [7:0]
=$af001f					VKY_LINE1_CMP_VALUE_HI  = $AF001F ;Write Only [3:0]
=$af001c					VKY_INFO_CHIP_NUM_L     = $AF001C
=$af001d					VKY_INFO_CHIP_NUM_H     = $AF001D
=$af001e					VKY_INFO_CHIP_VER_L     = $AF001E
=$af001f					VKY_INFO_CHIP_VER_H     = $AF001F
=$af0500					MOUSE_PTR_GRAP0_START    = $AF0500 ; 16 x 16 = 256 Pixels (Grey Scale) 0 = Transparent, 1 = Black , 255 = White
=$af05ff					MOUSE_PTR_GRAP0_END      = $AF05FF ; Pointer 0
=$af0600					MOUSE_PTR_GRAP1_START    = $AF0600 ;
=$af06ff					MOUSE_PTR_GRAP1_END      = $AF06FF ; Pointer 1
=$af0700					MOUSE_PTR_CTRL_REG_L    = $AF0700 ; Bit[0] Enable, Bit[1] = 0  ( 0 = Pointer0, 1 = Pointer1)
=$af0701					MOUSE_PTR_CTRL_REG_H    = $AF0701 ;
=$af0702					MOUSE_PTR_X_POS_L       = $AF0702 ; X Position (0 - 639) (Can only read now) Writing will have no effect
=$af0703					MOUSE_PTR_X_POS_H       = $AF0703 ;
=$af0704					MOUSE_PTR_Y_POS_L       = $AF0704 ; Y Position (0 - 479) (Can only read now) Writing will have no effect
=$af0705					MOUSE_PTR_Y_POS_H       = $AF0705 ;
=$af0706					MOUSE_PTR_BYTE0         = $AF0706 ; Byte 0 of Mouse Packet (you must write 3 Bytes)
=$af0707					MOUSE_PTR_BYTE1         = $AF0707 ; Byte 1 of Mouse Packet (if you don't, then )
=$af0708					MOUSE_PTR_BYTE2         = $AF0708 ; Byte 2 of Mouse Packet (state Machine will be jammed in 1 state)
=$af070b					C256F_MODEL_MAJOR       = $AF070B ;
=$af070c					C256F_MODEL_MINOR       = $AF070C ;
=$af070d					FPGA_DOR                = $AF070D ;
=$af070e					FPGA_MOR                = $AF070E ;
=$af070f					FPGA_YOR                = $AF070F ;
=$af1f40					FG_CHAR_LUT_PTR         = $AF1F40
=$af1f80					BG_CHAR_LUT_PTR		    = $AF1F80
=$af2000					GRPH_LUT0_PTR		    = $AF2000
=$af2400					GRPH_LUT1_PTR		    = $AF2400
=$af2800					GRPH_LUT2_PTR		    = $AF2800
=$af2c00					GRPH_LUT3_PTR		    = $AF2C00
=$af3000					GRPH_LUT4_PTR		    = $AF3000
=$af3400					GRPH_LUT5_PTR		    = $AF3400
=$af3800					GRPH_LUT6_PTR		    = $AF3800
=$af3c00					GRPH_LUT7_PTR		    = $AF3C00
=$af4000					GAMMA_B_LUT_PTR		    = $AF4000
=$af4100					GAMMA_G_LUT_PTR		    = $AF4100
=$af4200					GAMMA_R_LUT_PTR		    = $AF4200
=$af8000					FONT_MEMORY_BANK0       = $AF8000     ;$AF8000 - $AF87FF
=$af8800					FONT_MEMORY_BANK1       = $AF8800     ;$AF8800 - $AF8FFF
=$afa000					CS_TEXT_MEM_PTR         = $AFA000
=$afc000					CS_COLOR_MEM_PTR        = $AFC000
=$afe000					BTX_START               = $AFE000     ; BEATRIX Registers
=$afffff					BTX_END                 = $AFFFFF

;******  Processing file: src\VKYII_CFP9553_BITMAP_def.asm

=$01						BM_Enable             = $01
=$00						BM_LUT0               = $00 ;
=$02						BM_LUT1               = $02 ;
=$04						BM_LUT2               = $04 ;
=$06						BM_LUT3               = $06 ;
=$08						BM_LUT4               = $08 ;
=$0a						BM_LUT5               = $0A ;
=$0c						BM_LUT6               = $0C ;
=$0e						BM_LUT7               = $0E ;
=$af0100					BM0_CONTROL_REG     = $AF0100
=$af0101					BM0_START_ADDY_L    = $AF0101
=$af0102					BM0_START_ADDY_M    = $AF0102
=$af0103					BM0_START_ADDY_H    = $AF0103
=$af0104					BM0_X_OFFSET        = $AF0104   ; Not Implemented
=$af0105					BM0_Y_OFFSET        = $AF0105   ; Not Implemented
=$af0106					BM0_RESERVED_6      = $AF0106
=$af0107					BM0_RESERVED_7      = $AF0107
=$af0108					BM1_CONTROL_REG     = $AF0108
=$af0109					BM1_START_ADDY_L    = $AF0109
=$af010a					BM1_START_ADDY_M    = $AF010A
=$af010b					BM1_START_ADDY_H    = $AF010B
=$af010c					BM1_X_OFFSET        = $AF010C   ; Not Implemented
=$af010d					BM1_Y_OFFSET        = $AF010D   ; Not Implemented
=$af010e					BM1_RESERVED_6      = $AF010E
=$af010f					BM1_RESERVED_7      = $AF010F

;******  Return to file: src\vicky_ii_def.asm


;******  Processing file: src\VKYII_CFP9553_TILEMAP_def.asm

=$01						TILE_Enable             = $01
=$af0200					TL0_CONTROL_REG         = $AF0200       ; Bit[0] - Enable, Bit[3:1] - LUT Select,
=$af0201					TL0_START_ADDY_L        = $AF0201       ; Not USed right now - Starting Address to where is the MAP
=$af0202					TL0_START_ADDY_M        = $AF0202
=$af0203					TL0_START_ADDY_H        = $AF0203
=$af0204					TL0_TOTAL_X_SIZE_L      = $AF0204       ; Size of the Map in X Tile Count [9:0] (1024 Max)
=$af0205					TL0_TOTAL_X_SIZE_H      = $AF0205
=$af0206					TL0_TOTAL_Y_SIZE_L      = $AF0206       ; Size of the Map in Y Tile Count [9:0]
=$af0207					TL0_TOTAL_Y_SIZE_H      = $AF0207
=$af0208					TL0_WINDOW_X_POS_L      = $AF0208       ; Top Left Corner Position of the TileMAp Window in X + Scroll
=$af0209					TL0_WINDOW_X_POS_H      = $AF0209       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in X
=$af020a					TL0_WINDOW_Y_POS_L      = $AF020A       ; Top Left Corner Position of the TileMAp Window in Y
=$af020b					TL0_WINDOW_Y_POS_H      = $AF020B       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in Y
=$af020c					TL1_CONTROL_REG         = $AF020C       ; Bit[0] - Enable, Bit[3:1] - LUT Select,
=$af020d					TL1_START_ADDY_L        = $AF020D       ; Not USed right now - Starting Address to where is the MAP
=$af020e					TL1_START_ADDY_M        = $AF020E
=$af020f					TL1_START_ADDY_H        = $AF020F
=$af0210					TL1_TOTAL_X_SIZE_L      = $AF0210       ; Size of the Map in X Tile Count [9:0] (1024 Max)
=$af0211					TL1_TOTAL_X_SIZE_H      = $AF0211
=$af0212					TL1_TOTAL_Y_SIZE_L      = $AF0212       ; Size of the Map in Y Tile Count [9:0]
=$af0213					TL1_TOTAL_Y_SIZE_H      = $AF0213
=$af0214					TL1_WINDOW_X_POS_L      = $AF0214       ; Top Left Corner Position of the TileMAp Window in X + Scroll
=$af0215					TL1_WINDOW_X_POS_H      = $AF0215       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in X
=$af0216					TL1_WINDOW_Y_POS_L      = $AF0216       ; Top Left Corner Position of the TileMAp Window in Y
=$af0217					TL1_WINDOW_Y_POS_H      = $AF0217       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in Y
=$af0218					TL2_CONTROL_REG         = $AF0218       ; Bit[0] - Enable, Bit[3:1] - LUT Select,
=$af0219					TL2_START_ADDY_L        = $AF0219       ; Not USed right now - Starting Address to where is the MAP
=$af021a					TL2_START_ADDY_M        = $AF021A
=$af021b					TL2_START_ADDY_H        = $AF021B
=$af021c					TL2_TOTAL_X_SIZE_L      = $AF021C       ; Size of the Map in X Tile Count [9:0] (1024 Max)
=$af021d					TL2_TOTAL_X_SIZE_H      = $AF021D
=$af021e					TL2_TOTAL_Y_SIZE_L      = $AF021E       ; Size of the Map in Y Tile Count [9:0]
=$af021f					TL2_TOTAL_Y_SIZE_H      = $AF021F
=$af0220					TL2_WINDOW_X_POS_L      = $AF0220       ; Top Left Corner Position of the TileMAp Window in X + Scroll
=$af0221					TL2_WINDOW_X_POS_H      = $AF0221       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in X
=$af0222					TL2_WINDOW_Y_POS_L      = $AF0222       ; Top Left Corner Position of the TileMAp Window in Y
=$af0223					TL2_WINDOW_Y_POS_H      = $AF0223       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in Y
=$af0224					TL3_CONTROL_REG         = $AF0224       ; Bit[0] - Enable, Bit[3:1] - LUT Select,
=$af0225					TL3_START_ADDY_L        = $AF0225       ; Not USed right now - Starting Address to where is the MAP
=$af0226					TL3_START_ADDY_M        = $AF0226
=$af0227					TL3_START_ADDY_H        = $AF0227
=$af0228					TL3_TOTAL_X_SIZE_L      = $AF0228       ; Size of the Map in X Tile Count [9:0] (1024 Max)
=$af0229					TL3_TOTAL_X_SIZE_H      = $AF0229
=$af022a					TL3_TOTAL_Y_SIZE_L      = $AF022A       ; Size of the Map in Y Tile Count [9:0]
=$af022b					TL3_TOTAL_Y_SIZE_H      = $AF022B
=$af022c					TL3_WINDOW_X_POS_L      = $AF022C       ; Top Left Corner Position of the TileMAp Window in X + Scroll
=$af022d					TL3_WINDOW_X_POS_H      = $AF022D       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in X
=$af022e					TL3_WINDOW_Y_POS_L      = $AF022E       ; Top Left Corner Position of the TileMAp Window in Y
=$af022f					TL3_WINDOW_Y_POS_H      = $AF022F       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in Y
=$af0280					TILESET0_ADDY_L         = $AF0280   ; Pointer to Tileset 0 [21:0]
=$af0281					TILESET0_ADDY_M         = $AF0281
=$af0282					TILESET0_ADDY_H         = $AF0282
=$af0283					TILESET0_ADDY_CFG       = $AF0283   ; [3] - TileStride256x256 [2:0] LUT
=$af0284					TILESET1_ADDY_L         = $AF0284
=$af0285					TILESET1_ADDY_M         = $AF0285
=$af0286					TILESET1_ADDY_H         = $AF0286
=$af0287					TILESET1_ADDY_CFG       = $AF0287
=$af0288					TILESET2_ADDY_L         = $AF0288
=$af0289					TILESET2_ADDY_M         = $AF0289
=$af028a					TILESET2_ADDY_H         = $AF028A
=$af028b					TILESET2_ADDY_CFG       = $AF028B
=$af028c					TILESET3_ADDY_L         = $AF028C
=$af028d					TILESET3_ADDY_M         = $AF028D
=$af028e					TILESET3_ADDY_H         = $AF028E
=$af028f					TILESET3_ADDY_CFG       = $AF028F
=$af0290					TILESET4_ADDY_L         = $AF0290
=$af0291					TILESET4_ADDY_M         = $AF0291
=$af0292					TILESET4_ADDY_H         = $AF0292
=$af0293					TILESET4_ADDY_CFG       = $AF0293
=$af0294					TILESET5_ADDY_L         = $AF0294
=$af0295					TILESET5_ADDY_M         = $AF0295
=$af0296					TILESET5_ADDY_H         = $AF0296
=$af0297					TILESET5_ADDY_CFG       = $AF0297
=$af0298					TILESET6_ADDY_L         = $AF0298
=$af0299					TILESET6_ADDY_M         = $AF0299
=$af029a					TILESET6_ADDY_H         = $AF029A
=$af029b					TILESET6_ADDY_CFG       = $AF029B
=$af029c					TILESET7_ADDY_L         = $AF029C
=$af029d					TILESET7_ADDY_M         = $AF029D
=$af029e					TILESET7_ADDY_H         = $AF029E
=$af029f					TILESET7_ADDY_CFG       = $AF029F

;******  Return to file: src\vicky_ii_def.asm


;******  Processing file: src\VKYII_CFP9553_VDMA_def.asm

=$af0400					VDMA_CONTROL_REG        = $AF0400
=$01						VDMA_CTRL_Enable        = $01
=$02						VDMA_CTRL_1D_2D         = $02       ; 0 - 1D (Linear) Transfer , 1 - 2D (Block) Transfer
=$04						VDMA_CTRL_TRF_Fill      = $04       ; 0 - Transfer Src -> Dst, 1 - Fill Destination with "Byte2Write"
=$08						VDMA_CTRL_Int_Enable    = $08       ; Set to 1 to Enable the Generation of Interrupt when the Transfer is over.
=$10						VDMA_CTRL_SysRAM_Src    = $10       ; Set to 1 to Indicate that the Source is the System Ram Memory
=$20						VDMA_CTRL_SysRAM_Dst    = $20       ; Set to 1 to Indicate that the Destination is the System Ram Memory
=$80						VDMA_CTRL_Start_TRF     = $80       ; Set to 1 To Begin Process, Need to Cleared before, you can start another
=$00						VDMA_XFER_VRAM2VRAM = $00           ; VRAM -> VRAM transfer
=$01						VDMA_XFER_SRAM2VRAM = $01           ; SRAM -> VRAM transfer
=$02						VDMA_XFER_VRAM2SRAM = $02           ; VRAM -> SRAM transfer
=$af0401					VDMA_BYTE_2_WRITE       = $AF0401   ; Write Only - Byte to Write in the Fill Function
=$af0401					VDMA_STATUS_REG         = $AF0401   ; Read only
=$01						VDMA_STAT_Size_Err      = $01       ; If Set to 1, Overall Size is Invalid
=$02						VDMA_STAT_Dst_Add_Err   = $02       ; If Set to 1, Destination Address Invalid
=$04						VDMA_STAT_Src_Add_Err   = $04       ; If Set to 1, Source Address Invalid
=$80						VDMA_STAT_VDMA_IPS      = $80       ; If Set to 1, VDMA Transfer in Progress (this Inhibit CPU Access to Mem)
=$af0402					VDMA_SRC_ADDY_L         = $AF0402   ; Pointer to the Source of the Data to be stransfered
=$af0403					VDMA_SRC_ADDY_M         = $AF0403   ; This needs to be within Vicky's Range ($00_0000 - $3F_0000)
=$af0404					VDMA_SRC_ADDY_H         = $AF0404
=$af0405					VDMA_DST_ADDY_L         = $AF0405   ; Destination Pointer within Vicky's video memory Range
=$af0406					VDMA_DST_ADDY_M         = $AF0406   ; ($00_0000 - $3F_0000)
=$af0407					VDMA_DST_ADDY_H         = $AF0407
=$af0408					VDMA_SIZE_L             = $AF0408   ; Maximum Value: $40:0000 (4Megs)
=$af0409					VDMA_SIZE_M             = $AF0409
=$af040a					VDMA_SIZE_H             = $AF040A
=$af040b					VDMA_IGNORED            = $AF040B
=$af0408					VDMA_X_SIZE_L           = $AF0408   ; Maximum Value: 65535
=$af0409					VDMA_X_SIZE_H           = $AF0409
=$af040a					VDMA_Y_SIZE_L           = $AF040A   ; Maximum Value: 65535
=$af040b					VDMA_Y_SIZE_H           = $AF040B
=$af040c					VDMA_SRC_STRIDE_L       = $AF040C   ; Always use an Even Number ( The Engine uses Even Ver of that value)
=$af040d					VDMA_SRC_STRIDE_H       = $AF040D   ;
=$af040e					VDMA_DST_STRIDE_L       = $AF040E   ; Always use an Even Number ( The Engine uses Even Ver of that value)
=$af040f					VDMA_DST_STRIDE_H       = $AF040F   ;

;******  Return to file: src\vicky_ii_def.asm


;******  Processing file: src\VKYII_CFP9553_SDMA_def.asm

=$af0420					SDMA_CTRL_REG0           = $AF0420
=$01						SDMA_CTRL0_Enable        = $01
=$02						SDMA_CTRL0_1D_2D         = $02     ; 0 - 1D (Linear) Transfer , 1 - 2D (Block) Transfer
=$04						SDMA_CTRL0_TRF_Fill      = $04     ; 0 - Transfer Src -> Dst, 1 - Fill Destination with "Byte2Write"
=$08						SDMA_CTRL0_Int_Enable    = $08     ; Set to 1 to Enable the Generation of Interrupt when the Transfer is over.
=$10						SDMA_CTRL0_SysRAM_Src    = $10     ; Set to 1 to Indicate that the Source is the System Ram Memory
=$20						SDMA_CTRL0_SysRAM_Dst    = $20     ; Set to 1 to Indicate that the Destination is the System Ram Memory
=$00						SDMA_XFER_SRAM2SRAM = $00           ; SRAM -> SRAM transfer
=$10						SDMA_XFER_SRAM2VRAM = $10           ; SRAM -> VRAM transfer
=$20						SDMA_XFER_VRAM2SRAM = $20           ; VRAM -> SRAM transfer
=$30						SDMA_XFER_SRAMIO = $30              ; SRAM <-> IO transfer (see: SDMA_CONTROL_REG1 for config and direction)
=$40						SDMA_CTLR0_RSVD          = $40      ; Reserved
=$80						SDMA_CTRL0_Start_TRF     = $80      ; Set to 1 To Begin Process, Need to Cleared before, you can start another
=$af0421					SDMA_CTRL_REG1           = $AF0421  ; Write Only - Byte to Write in the Fill Function
=$01						SDMA_CTRL1_IO_Src		 = $01		; 1 = Source is an IO Address (ADC, SuperIO, IDE)
=$02						SDMA_CTRL1_IO_Src16		 = $02		; 0 = Src 8Bits Transfer / 1= 16Bits Transfer
=$04						SDMA_CTRL1_IO_Dst		 = $04		; 1 = Destination is an IO Address (DAC, SuperIO, IDE)
=$08						SDMA_CTRL1_IO_Dst16      = $08      ; 0 = Dst 8bits Transfer / 1= 16bits
=$af0422					SDMA_SRC_ADDY_L         = $AF0422   ; Pointer to the Source of the Data to be stransfered
=$af0423					SDMA_SRC_ADDY_M         = $AF0423   ; This needs to be within CPU's system RAM range ($00_0000 - $3F_FFFF)
=$af0424					SDMA_SRC_ADDY_H         = $AF0424
=$af0425					SDMA_DST_ADDY_L         = $AF0425   ; Destination Pointer within CPU's video memory Range
=$af0426					SDMA_DST_ADDY_M         = $AF0426   ; This needs to be within CPU's system RAM range ($00_0000 - $3F_FFFF)
=$af0427					SDMA_DST_ADDY_H         = $AF0427
=$af0428					SDMA_SIZE_L             = $AF0428   ; Maximum Value: $40:0000 (4Megs)
=$af0429					SDMA_SIZE_M             = $AF0429
=$af042a					SDMA_SIZE_H             = $AF042A
=$af042b					SDMA_IGNORED            = $AF042B
=$af0428					SDMA_X_SIZE_L           = $AF0428   ; Maximum Value: 65535
=$af0429					SDMA_X_SIZE_H           = $AF0429
=$af042a					SDMA_Y_SIZE_L           = $AF042A   ; Maximum Value: 65535
=$af042b					SDMA_Y_SIZE_H           = $AF042B
=$af042c					SDMA_SRC_STRIDE_L       = $AF042C   ; Always use an Even Number ( The Engine uses Even Ver of that value)
=$af042d					SDMA_SRC_STRIDE_H       = $AF042D   ;
=$af042e					SDMA_DST_STRIDE_L       = $AF042E   ; Always use an Even Number ( The Engine uses Even Ver of that value)
=$af042f					SDMA_DST_STRIDE_H       = $AF042F   ;
=$af0430					SDMA_BYTE_2_WRITE       = $AF0430   ; Write Only - Byte to Write in the Fill Function
=$af0430					SDMA_STATUS_REG         = $AF0430   ; Read only
=$01						SDMA_STAT_Size_Err       = $01      ; If Set to 1, Overall Size is Invalid
=$02						SDMA_STAT_Dst_Add_Err    = $02      ; If Set to 1, Destination Address Invalid
=$04						SDMA_STAT_Src_Add_Err    = $04      ; If Set to 1, Source Address Invalid
=$08						SDMA_STAT_TimeOut_Err    = $08      ; will be set to 1 if a Timeout occur when transfering between data from and to VRAM

;******  Return to file: src\vicky_ii_def.asm


;******  Processing file: src\VKYII_CFP9553_SPRITE_def.asm

=$01						SPRITE_Enable             = $01
=$00						SPRITE_LUT0               = $00 ; This is the LUT that the Sprite will use
=$02						SPRITE_LUT1               = $02
=$04						SPRITE_LUT2               = $04 ; Only 4 LUT for Now, So this bit is not used.
=$06						SPRITE_LUT3               = $06 ; Only 4 LUT for Now, So this bit is not used.
=$08						SPRITE_LUT4               = $08 ; Only 4 LUT for Now, So this bit is not used.
=$0a						SPRITE_LUT5               = $0A ; Only 4 LUT for Now, So this bit is not used.
=$0c						SPRITE_LUT6               = $0C ; Only 4 LUT for Now, So this bit is not used.
=$0e						SPRITE_LUT7               = $0E ; Only 4 LUT for Now, So this bit is not used.
=$00						SPRITE_DEPTH0             = $00
=$10						SPRITE_DEPTH1             = $10
=$20						SPRITE_DEPTH2             = $20
=$30						SPRITE_DEPTH3             = $30
=$40						SPRITE_DEPTH4             = $40
=$50						SPRITE_DEPTH5             = $50
=$60						SPRITE_DEPTH6             = $60
=$af0c00					SP00_CONTROL_REG        = $AF0C00
=$af0c01					SP00_ADDY_PTR_L         = $AF0C01
=$af0c02					SP00_ADDY_PTR_M         = $AF0C02
=$af0c03					SP00_ADDY_PTR_H         = $AF0C03
=$af0c04					SP00_X_POS_L            = $AF0C04
=$af0c05					SP00_X_POS_H            = $AF0C05
=$af0c06					SP00_Y_POS_L            = $AF0C06
=$af0c07					SP00_Y_POS_H            = $AF0C07
=$af0c08					SP01_CONTROL_REG        = $AF0C08
=$af0c09					SP01_ADDY_PTR_L         = $AF0C09
=$af0c0a					SP01_ADDY_PTR_M         = $AF0C0A
=$af0c0b					SP01_ADDY_PTR_H         = $AF0C0B
=$af0c0c					SP01_X_POS_L            = $AF0C0C
=$af0c0d					SP01_X_POS_H            = $AF0C0D
=$af0c0e					SP01_Y_POS_L            = $AF0C0E
=$af0c0f					SP01_Y_POS_H            = $AF0C0F
=$af0c10					SP02_CONTROL_REG        = $AF0C10
=$af0c11					SP02_ADDY_PTR_L         = $AF0C11
=$af0c12					SP02_ADDY_PTR_M         = $AF0C12
=$af0c13					SP02_ADDY_PTR_H         = $AF0C13
=$af0c14					SP02_X_POS_L            = $AF0C14
=$af0c15					SP02_X_POS_H            = $AF0C15
=$af0c16					SP02_Y_POS_L            = $AF0C16
=$af0c17					SP02_Y_POS_H            = $AF0C17
=$af0c18					SP03_CONTROL_REG        = $AF0C18
=$af0c19					SP03_ADDY_PTR_L         = $AF0C19
=$af0c1a					SP03_ADDY_PTR_M         = $AF0C1A
=$af0c1b					SP03_ADDY_PTR_H         = $AF0C1B
=$af0c1c					SP03_X_POS_L            = $AF0C1C
=$af0c1d					SP03_X_POS_H            = $AF0C1D
=$af0c1e					SP03_Y_POS_L            = $AF0C1E
=$af0c1f					SP03_Y_POS_H            = $AF0C1F
=$af0c20					SP04_CONTROL_REG        = $AF0C20
=$af0c21					SP04_ADDY_PTR_L         = $AF0C21
=$af0c22					SP04_ADDY_PTR_M         = $AF0C22
=$af0c23					SP04_ADDY_PTR_H         = $AF0C23
=$af0c24					SP04_X_POS_L            = $AF0C24
=$af0c25					SP04_X_POS_H            = $AF0C25
=$af0c26					SP04_Y_POS_L            = $AF0C26
=$af0c27					SP04_Y_POS_H            = $AF0C27
=$af0c28					SP05_CONTROL_REG        = $AF0C28
=$af0c29					SP05_ADDY_PTR_L         = $AF0C29
=$af0c2a					SP05_ADDY_PTR_M         = $AF0C2A
=$af0c2b					SP05_ADDY_PTR_H         = $AF0C2B
=$af0c2c					SP05_X_POS_L            = $AF0C2C
=$af0c2d					SP05_X_POS_H            = $AF0C2D
=$af0c2e					SP05_Y_POS_L            = $AF0C2E
=$af0c2f					SP05_Y_POS_H            = $AF0C2F
=$af0c30					SP06_CONTROL_REG        = $AF0C30
=$af0c31					SP06_ADDY_PTR_L         = $AF0C31
=$af0c32					SP06_ADDY_PTR_M         = $AF0C32
=$af0c33					SP06_ADDY_PTR_H         = $AF0C33
=$af0c34					SP06_X_POS_L            = $AF0C34
=$af0c35					SP06_X_POS_H            = $AF0C35
=$af0c36					SP06_Y_POS_L            = $AF0C36
=$af0c37					SP06_Y_POS_H            = $AF0C37
=$af0c38					SP07_CONTROL_REG        = $AF0C38
=$af0c39					SP07_ADDY_PTR_L         = $AF0C39
=$af0c3a					SP07_ADDY_PTR_M         = $AF0C3A
=$af0c3b					SP07_ADDY_PTR_H         = $AF0C3B
=$af0c3c					SP07_X_POS_L            = $AF0C3C
=$af0c3d					SP07_X_POS_H            = $AF0C3D
=$af0c3e					SP07_Y_POS_L            = $AF0C3E
=$af0c3f					SP07_Y_POS_H            = $AF0C3F
=$af0c40					SP08_CONTROL_REG        = $AF0C40
=$af0c41					SP08_ADDY_PTR_L         = $AF0C41
=$af0c42					SP08_ADDY_PTR_M         = $AF0C42
=$af0c43					SP08_ADDY_PTR_H         = $AF0C43
=$af0c44					SP08_X_POS_L            = $AF0C44
=$af0c45					SP08_X_POS_H            = $AF0C45
=$af0c46					SP08_Y_POS_L            = $AF0C46
=$af0c47					SP08_Y_POS_H            = $AF0C47
=$af0c48					SP09_CONTROL_REG        = $AF0C48
=$af0c49					SP09_ADDY_PTR_L         = $AF0C49
=$af0c4a					SP09_ADDY_PTR_M         = $AF0C4A
=$af0c4b					SP09_ADDY_PTR_H         = $AF0C4B
=$af0c4c					SP09_X_POS_L            = $AF0C4C
=$af0c4d					SP09_X_POS_H            = $AF0C4D
=$af0c4e					SP09_Y_POS_L            = $AF0C4E
=$af0c4f					SP09_Y_POS_H            = $AF0C4F
=$af0c50					SP10_CONTROL_REG        = $AF0C50
=$af0c51					SP10_ADDY_PTR_L         = $AF0C51
=$af0c52					SP10_ADDY_PTR_M         = $AF0C52
=$af0c53					SP10_ADDY_PTR_H         = $AF0C53
=$af0c54					SP10_X_POS_L            = $AF0C54
=$af0c55					SP10_X_POS_H            = $AF0C55
=$af0c56					SP10_Y_POS_L            = $AF0C56
=$af0c57					SP10_Y_POS_H            = $AF0C57
=$af0c58					SP11_CONTROL_REG        = $AF0C58
=$af0c59					SP11_ADDY_PTR_L         = $AF0C59
=$af0c5a					SP11_ADDY_PTR_M         = $AF0C5A
=$af0c5b					SP11_ADDY_PTR_H         = $AF0C5B
=$af0c5c					SP11_X_POS_L            = $AF0C5C
=$af0c5d					SP11_X_POS_H            = $AF0C5D
=$af0c5e					SP11_Y_POS_L            = $AF0C5E
=$af0c5f					SP11_Y_POS_H            = $AF0C5F
=$af0c60					SP12_CONTROL_REG        = $AF0C60
=$af0c61					SP12_ADDY_PTR_L         = $AF0C61
=$af0c62					SP12_ADDY_PTR_M         = $AF0C62
=$af0c63					SP12_ADDY_PTR_H         = $AF0C63
=$af0c64					SP12_X_POS_L            = $AF0C64
=$af0c65					SP12_X_POS_H            = $AF0C65
=$af0c66					SP12_Y_POS_L            = $AF0C66
=$af0c67					SP12_Y_POS_H            = $AF0C67
=$af0c68					SP13_CONTROL_REG        = $AF0C68
=$af0c69					SP13_ADDY_PTR_L         = $AF0C69
=$af0c6a					SP13_ADDY_PTR_M         = $AF0C6A
=$af0c6b					SP13_ADDY_PTR_H         = $AF0C6B
=$af0c6c					SP13_X_POS_L            = $AF0C6C
=$af0c6d					SP13_X_POS_H            = $AF0C6D
=$af0c6e					SP13_Y_POS_L            = $AF0C6E
=$af0c6f					SP13_Y_POS_H            = $AF0C6F
=$af0c70					SP14_CONTROL_REG        = $AF0C70
=$af0c71					SP14_ADDY_PTR_L         = $AF0C71
=$af0c72					SP14_ADDY_PTR_M         = $AF0C72
=$af0c73					SP14_ADDY_PTR_H         = $AF0C73
=$af0c74					SP14_X_POS_L            = $AF0C74
=$af0c75					SP14_X_POS_H            = $AF0C75
=$af0c76					SP14_Y_POS_L            = $AF0C76
=$af0c77					SP14_Y_POS_H            = $AF0C77
=$af0c78					SP15_CONTROL_REG        = $AF0C78
=$af0c79					SP15_ADDY_PTR_L         = $AF0C79
=$af0c7a					SP15_ADDY_PTR_M         = $AF0C7A
=$af0c7b					SP15_ADDY_PTR_H         = $AF0C7B
=$af0c7c					SP15_X_POS_L            = $AF0C7C
=$af0c7d					SP15_X_POS_H            = $AF0C7D
=$af0c7e					SP15_Y_POS_L            = $AF0C7E
=$af0c7f					SP15_Y_POS_H            = $AF0C7F
=$af0c80					SP16_CONTROL_REG        = $AF0C80
=$af0c81					SP16_ADDY_PTR_L         = $AF0C81
=$af0c82					SP16_ADDY_PTR_M         = $AF0C82
=$af0c83					SP16_ADDY_PTR_H         = $AF0C83
=$af0c84					SP16_X_POS_L            = $AF0C84
=$af0c85					SP16_X_POS_H            = $AF0C85
=$af0c86					SP16_Y_POS_L            = $AF0C86
=$af0c87					SP16_Y_POS_H            = $AF0C87
=$af0c88					SP17_CONTROL_REG        = $AF0C88
=$af0c89					SP17_ADDY_PTR_L         = $AF0C89
=$af0c8a					SP17_ADDY_PTR_M         = $AF0C8A
=$af0c8b					SP17_ADDY_PTR_H         = $AF0C8B
=$af0c8c					SP17_X_POS_L            = $AF0C8C
=$af0c8d					SP17_X_POS_H            = $AF0C8D
=$af0c8e					SP17_Y_POS_L            = $AF0C8E
=$af0c8f					SP17_Y_POS_H            = $AF0C8F
=$af0c90					SP18_CONTROL_REG        = $AF0C90
=$af0c91					SP18_ADDY_PTR_L         = $AF0C91
=$af0c92					SP18_ADDY_PTR_M         = $AF0C92
=$af0c93					SP18_ADDY_PTR_H         = $AF0C93
=$af0c94					SP18_X_POS_L            = $AF0C94
=$af0c95					SP18_X_POS_H            = $AF0C95
=$af0c96					SP18_Y_POS_L            = $AF0C96
=$af0c97					SP18_Y_POS_H            = $AF0C97
=$af0c98					SP19_CONTROL_REG        = $AF0C98
=$af0c99					SP19_ADDY_PTR_L         = $AF0C99
=$af0c9a					SP19_ADDY_PTR_M         = $AF0C9A
=$af0c9b					SP19_ADDY_PTR_H         = $AF0C9B
=$af0c9c					SP19_X_POS_L            = $AF0C9C
=$af0c9d					SP19_X_POS_H            = $AF0C9D
=$af0c9e					SP19_Y_POS_L            = $AF0C9E
=$af0c9f					SP19_Y_POS_H            = $AF0C9F
=$af0ca0					SP20_CONTROL_REG        = $AF0CA0
=$af0ca1					SP20_ADDY_PTR_L         = $AF0CA1
=$af0ca2					SP20_ADDY_PTR_M         = $AF0CA2
=$af0ca3					SP20_ADDY_PTR_H         = $AF0CA3
=$af0ca4					SP20_X_POS_L            = $AF0CA4
=$af0ca5					SP20_X_POS_H            = $AF0CA5
=$af0ca6					SP20_Y_POS_L            = $AF0CA6
=$af0ca7					SP20_Y_POS_H            = $AF0CA7
=$af0ca8					SP21_CONTROL_REG        = $AF0CA8
=$af0ca9					SP21_ADDY_PTR_L         = $AF0CA9
=$af0caa					SP21_ADDY_PTR_M         = $AF0CAA
=$af0cab					SP21_ADDY_PTR_H         = $AF0CAB
=$af0cac					SP21_X_POS_L            = $AF0CAC
=$af0cad					SP21_X_POS_H            = $AF0CAD
=$af0cae					SP21_Y_POS_L            = $AF0CAE
=$af0caf					SP21_Y_POS_H            = $AF0CAF
=$af0cb0					SP22_CONTROL_REG        = $AF0CB0
=$af0cb1					SP22_ADDY_PTR_L         = $AF0CB1
=$af0cb2					SP22_ADDY_PTR_M         = $AF0CB2
=$af0cb3					SP22_ADDY_PTR_H         = $AF0CB3
=$af0cb4					SP22_X_POS_L            = $AF0CB4
=$af0cb5					SP22_X_POS_H            = $AF0CB5
=$af0cb6					SP22_Y_POS_L            = $AF0CB6
=$af0cb7					SP22_Y_POS_H            = $AF0CB7
=$af0cb8					SP23_CONTROL_REG        = $AF0CB8
=$af0cb9					SP23_ADDY_PTR_L         = $AF0CB9
=$af0cba					SP23_ADDY_PTR_M         = $AF0CBA
=$af0cbb					SP23_ADDY_PTR_H         = $AF0CBB
=$af0cbc					SP23_X_POS_L            = $AF0CBC
=$af0cbd					SP23_X_POS_H            = $AF0CBD
=$af0cbe					SP23_Y_POS_L            = $AF0CBE
=$af0cbf					SP23_Y_POS_H            = $AF0CBF
=$af0cc0					SP24_CONTROL_REG        = $AF0CC0
=$af0cc1					SP24_ADDY_PTR_L         = $AF0CC1
=$af0cc2					SP24_ADDY_PTR_M         = $AF0CC2
=$af0cc3					SP24_ADDY_PTR_H         = $AF0CC3
=$af0cc4					SP24_X_POS_L            = $AF0CC4
=$af0cc5					SP24_X_POS_H            = $AF0CC5
=$af0cc6					SP24_Y_POS_L            = $AF0CC6
=$af0cc7					SP24_Y_POS_H            = $AF0CC7
=$af0cc8					SP25_CONTROL_REG        = $AF0CC8
=$af0cc9					SP25_ADDY_PTR_L         = $AF0CC9
=$af0cca					SP25_ADDY_PTR_M         = $AF0CCA
=$af0ccb					SP25_ADDY_PTR_H         = $AF0CCB
=$af0ccc					SP25_X_POS_L            = $AF0CCC
=$af0ccd					SP25_X_POS_H            = $AF0CCD
=$af0cce					SP25_Y_POS_L            = $AF0CCE
=$af0ccf					SP25_Y_POS_H            = $AF0CCF
=$af0cd0					SP26_CONTROL_REG        = $AF0CD0
=$af0cd1					SP26_ADDY_PTR_L         = $AF0CD1
=$af0cd2					SP26_ADDY_PTR_M         = $AF0CD2
=$af0cd3					SP26_ADDY_PTR_H         = $AF0CD3
=$af0cd4					SP26_X_POS_L            = $AF0CD4
=$af0cd5					SP26_X_POS_H            = $AF0CD5
=$af0cd6					SP26_Y_POS_L            = $AF0CD6
=$af0cd7					SP26_Y_POS_H            = $AF0CD7
=$af0cd8					SP27_CONTROL_REG        = $AF0CD8
=$af0cd9					SP27_ADDY_PTR_L         = $AF0CD9
=$af0cda					SP27_ADDY_PTR_M         = $AF0CDA
=$af0cdb					SP27_ADDY_PTR_H         = $AF0CDB
=$af0cdc					SP27_X_POS_L            = $AF0CDC
=$af0cdd					SP27_X_POS_H            = $AF0CDD
=$af0cde					SP27_Y_POS_L            = $AF0CDE
=$af0cdf					SP27_Y_POS_H            = $AF0CDF
=$af0ce0					SP28_CONTROL_REG        = $AF0CE0
=$af0ce1					SP28_ADDY_PTR_L         = $AF0CE1
=$af0ce2					SP28_ADDY_PTR_M         = $AF0CE2
=$af0ce3					SP28_ADDY_PTR_H         = $AF0CE3
=$af0ce4					SP28_X_POS_L            = $AF0CE4
=$af0ce5					SP28_X_POS_H            = $AF0CE5
=$af0ce6					SP28_Y_POS_L            = $AF0CE6
=$af0ce7					SP28_Y_POS_H            = $AF0CE7
=$af0ce8					SP29_CONTROL_REG        = $AF0CE8
=$af0ce9					SP29_ADDY_PTR_L         = $AF0CE9
=$af0cea					SP29_ADDY_PTR_M         = $AF0CEA
=$af0ceb					SP29_ADDY_PTR_H         = $AF0CEB
=$af0cec					SP29_X_POS_L            = $AF0CEC
=$af0ced					SP29_X_POS_H            = $AF0CED
=$af0cee					SP29_Y_POS_L            = $AF0CEE
=$af0cef					SP29_Y_POS_H            = $AF0CEF
=$af0cf0					SP30_CONTROL_REG        = $AF0CF0
=$af0cf1					SP30_ADDY_PTR_L         = $AF0CF1
=$af0cf2					SP30_ADDY_PTR_M         = $AF0CF2
=$af0cf3					SP30_ADDY_PTR_H         = $AF0CF3
=$af0cf4					SP30_X_POS_L            = $AF0CF4
=$af0cf5					SP30_X_POS_H            = $AF0CF5
=$af0cf6					SP30_Y_POS_L            = $AF0CF6
=$af0cf7					SP30_Y_POS_H            = $AF0CF7
=$af0cf8					SP31_CONTROL_REG        = $AF0CF8
=$af0cf9					SP31_ADDY_PTR_L         = $AF0CF9
=$af0cfa					SP31_ADDY_PTR_M         = $AF0CFA
=$af0cfb					SP31_ADDY_PTR_H         = $AF0CFB
=$af0cfc					SP31_X_POS_L            = $AF0CFC
=$af0cfd					SP31_X_POS_H            = $AF0CFD
=$af0cfe					SP31_Y_POS_L            = $AF0CFE
=$af0cff					SP31_Y_POS_H            = $AF0CFF
=$af0d00					SP32_CONTROL_REG        = $AF0D00
=$af0d01					SP32_ADDY_PTR_L         = $AF0D01
=$af0d02					SP32_ADDY_PTR_M         = $AF0D02
=$af0d03					SP32_ADDY_PTR_H         = $AF0D03
=$af0d04					SP32_X_POS_L            = $AF0D04
=$af0d05					SP32_X_POS_H            = $AF0D05
=$af0d06					SP32_Y_POS_L            = $AF0D06
=$af0d07					SP32_Y_POS_H            = $AF0D07
=$af0d08					SP33_CONTROL_REG        = $AF0D08
=$af0d09					SP33_ADDY_PTR_L         = $AF0D09
=$af0d0a					SP33_ADDY_PTR_M         = $AF0D0A
=$af0d0b					SP33_ADDY_PTR_H         = $AF0D0B
=$af0d0c					SP33_X_POS_L            = $AF0D0C
=$af0d0d					SP33_X_POS_H            = $AF0D0D
=$af0d0e					SP33_Y_POS_L            = $AF0D0E
=$af0d0f					SP33_Y_POS_H            = $AF0D0F
=$af0d10					SP34_CONTROL_REG        = $AF0D10
=$af0d11					SP34_ADDY_PTR_L         = $AF0D11
=$af0d12					SP34_ADDY_PTR_M         = $AF0D12
=$af0d13					SP34_ADDY_PTR_H         = $AF0D13
=$af0d14					SP34_X_POS_L            = $AF0D14
=$af0d15					SP34_X_POS_H            = $AF0D15
=$af0d16					SP34_Y_POS_L            = $AF0D16
=$af0d17					SP34_Y_POS_H            = $AF0D17
=$af0d18					SP35_CONTROL_REG        = $AF0D18
=$af0d19					SP35_ADDY_PTR_L         = $AF0D19
=$af0d1a					SP35_ADDY_PTR_M         = $AF0D1A
=$af0d1b					SP35_ADDY_PTR_H         = $AF0D1B
=$af0d1c					SP35_X_POS_L            = $AF0D1C
=$af0d1d					SP35_X_POS_H            = $AF0D1D
=$af0d1e					SP35_Y_POS_L            = $AF0D1E
=$af0d1f					SP35_Y_POS_H            = $AF0D1F
=$af0d20					SP36_CONTROL_REG        = $AF0D20
=$af0d21					SP36_ADDY_PTR_L         = $AF0D21
=$af0d22					SP36_ADDY_PTR_M         = $AF0D22
=$af0d23					SP36_ADDY_PTR_H         = $AF0D23
=$af0d24					SP36_X_POS_L            = $AF0D24
=$af0d25					SP36_X_POS_H            = $AF0D25
=$af0d26					SP36_Y_POS_L            = $AF0D26
=$af0d27					SP36_Y_POS_H            = $AF0D27
=$af0d28					SP37_CONTROL_REG        = $AF0D28
=$af0d29					SP37_ADDY_PTR_L         = $AF0D29
=$af0d2a					SP37_ADDY_PTR_M         = $AF0D2A
=$af0d2b					SP37_ADDY_PTR_H         = $AF0D2B
=$af0d2c					SP37_X_POS_L            = $AF0D2C
=$af0d2d					SP37_X_POS_H            = $AF0D2D
=$af0d2e					SP37_Y_POS_L            = $AF0D2E
=$af0d2f					SP37_Y_POS_H            = $AF0D2F
=$af0d30					SP38_CONTROL_REG        = $AF0D30
=$af0d31					SP38_ADDY_PTR_L         = $AF0D31
=$af0d32					SP38_ADDY_PTR_M         = $AF0D32
=$af0d33					SP38_ADDY_PTR_H         = $AF0D33
=$af0d34					SP38_X_POS_L            = $AF0D34
=$af0d35					SP38_X_POS_H            = $AF0D35
=$af0d36					SP38_Y_POS_L            = $AF0D36
=$af0d37					SP38_Y_POS_H            = $AF0D37
=$af0d38					SP39_CONTROL_REG        = $AF0D38
=$af0d39					SP39_ADDY_PTR_L         = $AF0D39
=$af0d3a					SP39_ADDY_PTR_M         = $AF0D3A
=$af0d3b					SP39_ADDY_PTR_H         = $AF0D3B
=$af0d3c					SP39_X_POS_L            = $AF0D3C
=$af0d3d					SP39_X_POS_H            = $AF0D3D
=$af0d3e					SP39_Y_POS_L            = $AF0D3E
=$af0d3f					SP39_Y_POS_H            = $AF0D3F
=$af0d40					SP40_CONTROL_REG        = $AF0D40
=$af0d41					SP40_ADDY_PTR_L         = $AF0D41
=$af0d42					SP40_ADDY_PTR_M         = $AF0D42
=$af0d43					SP40_ADDY_PTR_H         = $AF0D43
=$af0d44					SP40_X_POS_L            = $AF0D44
=$af0d45					SP40_X_POS_H            = $AF0D45
=$af0d46					SP40_Y_POS_L            = $AF0D46
=$af0d47					SP40_Y_POS_H            = $AF0D47
=$af0d48					SP41_CONTROL_REG        = $AF0D48
=$af0d49					SP41_ADDY_PTR_L         = $AF0D49
=$af0d4a					SP41_ADDY_PTR_M         = $AF0D4A
=$af0d4b					SP41_ADDY_PTR_H         = $AF0D4B
=$af0d4c					SP41_X_POS_L            = $AF0D4C
=$af0d4d					SP41_X_POS_H            = $AF0D4D
=$af0d4e					SP41_Y_POS_L            = $AF0D4E
=$af0d4f					SP41_Y_POS_H            = $AF0D4F
=$af0d50					SP42_CONTROL_REG        = $AF0D50
=$af0d51					SP42_ADDY_PTR_L         = $AF0D51
=$af0d52					SP42_ADDY_PTR_M         = $AF0D52
=$af0d53					SP42_ADDY_PTR_H         = $AF0D53
=$af0d54					SP42_X_POS_L            = $AF0D54
=$af0d55					SP42_X_POS_H            = $AF0D55
=$af0d56					SP42_Y_POS_L            = $AF0D56
=$af0d57					SP42_Y_POS_H            = $AF0D57
=$af0d58					SP43_CONTROL_REG        = $AF0D58
=$af0d59					SP43_ADDY_PTR_L         = $AF0D59
=$af0d5a					SP43_ADDY_PTR_M         = $AF0D5A
=$af0d5b					SP43_ADDY_PTR_H         = $AF0D5B
=$af0d5c					SP43_X_POS_L            = $AF0D5C
=$af0d5d					SP43_X_POS_H            = $AF0D5D
=$af0d5e					SP43_Y_POS_L            = $AF0D5E
=$af0d5f					SP43_Y_POS_H            = $AF0D5F
=$af0d60					SP44_CONTROL_REG        = $AF0D60
=$af0d61					SP44_ADDY_PTR_L         = $AF0D61
=$af0d62					SP44_ADDY_PTR_M         = $AF0D62
=$af0d63					SP44_ADDY_PTR_H         = $AF0D63
=$af0d64					SP44_X_POS_L            = $AF0D64
=$af0d65					SP44_X_POS_H            = $AF0D65
=$af0d66					SP44_Y_POS_L            = $AF0D66
=$af0d67					SP44_Y_POS_H            = $AF0D67
=$af0d68					SP45_CONTROL_REG        = $AF0D68
=$af0d69					SP45_ADDY_PTR_L         = $AF0D69
=$af0d6a					SP45_ADDY_PTR_M         = $AF0D6A
=$af0d6b					SP45_ADDY_PTR_H         = $AF0D6B
=$af0d6c					SP45_X_POS_L            = $AF0D6C
=$af0d6d					SP45_X_POS_H            = $AF0D6D
=$af0d6e					SP45_Y_POS_L            = $AF0D6E
=$af0d6f					SP45_Y_POS_H            = $AF0D6F
=$af0d70					SP46_CONTROL_REG        = $AF0D70
=$af0d71					SP46_ADDY_PTR_L         = $AF0D71
=$af0d72					SP46_ADDY_PTR_M         = $AF0D72
=$af0d73					SP46_ADDY_PTR_H         = $AF0D73
=$af0d74					SP46_X_POS_L            = $AF0D74
=$af0d75					SP46_X_POS_H            = $AF0D75
=$af0d76					SP46_Y_POS_L            = $AF0D76
=$af0d77					SP46_Y_POS_H            = $AF0D77
=$af0d78					SP47_CONTROL_REG        = $AF0D78
=$af0d79					SP47_ADDY_PTR_L         = $AF0D79
=$af0d7a					SP47_ADDY_PTR_M         = $AF0D7A
=$af0d7b					SP47_ADDY_PTR_H         = $AF0D7B
=$af0d7c					SP47_X_POS_L            = $AF0D7C
=$af0d7d					SP47_X_POS_H            = $AF0D7D
=$af0d7e					SP47_Y_POS_L            = $AF0D7E
=$af0d7f					SP47_Y_POS_H            = $AF0D7F
=$af0d80					SP48_CONTROL_REG        = $AF0D80
=$af0d81					SP48_ADDY_PTR_L         = $AF0D81
=$af0d82					SP48_ADDY_PTR_M         = $AF0D82
=$af0d83					SP48_ADDY_PTR_H         = $AF0D83
=$af0d84					SP48_X_POS_L            = $AF0D84
=$af0d85					SP48_X_POS_H            = $AF0D85
=$af0d86					SP48_Y_POS_L            = $AF0D86
=$af0d87					SP48_Y_POS_H            = $AF0D87
=$af0d88					SP49_CONTROL_REG        = $AF0D88
=$af0d89					SP49_ADDY_PTR_L         = $AF0D89
=$af0d8a					SP49_ADDY_PTR_M         = $AF0D8A
=$af0d8b					SP49_ADDY_PTR_H         = $AF0D8B
=$af0d8c					SP49_X_POS_L            = $AF0D8C
=$af0d8d					SP49_X_POS_H            = $AF0D8D
=$af0d8e					SP49_Y_POS_L            = $AF0D8E
=$af0d8f					SP49_Y_POS_H            = $AF0D8F
=$af0d90					SP50_CONTROL_REG        = $AF0D90
=$af0d91					SP50_ADDY_PTR_L         = $AF0D91
=$af0d92					SP50_ADDY_PTR_M         = $AF0D92
=$af0d93					SP50_ADDY_PTR_H         = $AF0D93
=$af0d94					SP50_X_POS_L            = $AF0D94
=$af0d95					SP50_X_POS_H            = $AF0D95
=$af0d96					SP50_Y_POS_L            = $AF0D96
=$af0d97					SP50_Y_POS_H            = $AF0D97
=$af0d98					SP51_CONTROL_REG        = $AF0D98
=$af0d99					SP51_ADDY_PTR_L         = $AF0D99
=$af0d9a					SP51_ADDY_PTR_M         = $AF0D9A
=$af0d9b					SP51_ADDY_PTR_H         = $AF0D9B
=$af0d9c					SP51_X_POS_L            = $AF0D9C
=$af0d9d					SP51_X_POS_H            = $AF0D9D
=$af0d9e					SP51_Y_POS_L            = $AF0D9E
=$af0d9f					SP51_Y_POS_H            = $AF0D9F
=$af0da0					SP52_CONTROL_REG        = $AF0DA0
=$af0da1					SP52_ADDY_PTR_L         = $AF0DA1
=$af0da2					SP52_ADDY_PTR_M         = $AF0DA2
=$af0da3					SP52_ADDY_PTR_H         = $AF0DA3
=$af0da4					SP52_X_POS_L            = $AF0DA4
=$af0da5					SP52_X_POS_H            = $AF0DA5
=$af0da6					SP52_Y_POS_L            = $AF0DA6
=$af0da7					SP52_Y_POS_H            = $AF0DA7
=$af0da8					SP53_CONTROL_REG        = $AF0DA8
=$af0da9					SP53_ADDY_PTR_L         = $AF0DA9
=$af0daa					SP53_ADDY_PTR_M         = $AF0DAA
=$af0dab					SP53_ADDY_PTR_H         = $AF0DAB
=$af0dac					SP53_X_POS_L            = $AF0DAC
=$af0dad					SP53_X_POS_H            = $AF0DAD
=$af0dae					SP53_Y_POS_L            = $AF0DAE
=$af0daf					SP53_Y_POS_H            = $AF0DAF
=$af0db0					SP54_CONTROL_REG        = $AF0DB0
=$af0db1					SP54_ADDY_PTR_L         = $AF0DB1
=$af0db2					SP54_ADDY_PTR_M         = $AF0DB2
=$af0db3					SP54_ADDY_PTR_H         = $AF0DB3
=$af0db4					SP54_X_POS_L            = $AF0DB4
=$af0db5					SP54_X_POS_H            = $AF0DB5
=$af0db6					SP54_Y_POS_L            = $AF0DB6
=$af0db7					SP54_Y_POS_H            = $AF0DB7
=$af0db8					SP55_CONTROL_REG        = $AF0DB8
=$af0db9					SP55_ADDY_PTR_L         = $AF0DB9
=$af0dba					SP55_ADDY_PTR_M         = $AF0DBA
=$af0dbb					SP55_ADDY_PTR_H         = $AF0DBB
=$af0dbc					SP55_X_POS_L            = $AF0DBC
=$af0dbd					SP55_X_POS_H            = $AF0DBD
=$af0dbe					SP55_Y_POS_L            = $AF0DBE
=$af0dbf					SP55_Y_POS_H            = $AF0DBF
=$af0dc0					SP56_CONTROL_REG        = $AF0DC0
=$af0dc1					SP56_ADDY_PTR_L         = $AF0DC1
=$af0dc2					SP56_ADDY_PTR_M         = $AF0DC2
=$af0dc3					SP56_ADDY_PTR_H         = $AF0DC3
=$af0dc4					SP56_X_POS_L            = $AF0DC4
=$af0dc5					SP56_X_POS_H            = $AF0DC5
=$af0dc6					SP56_Y_POS_L            = $AF0DC6
=$af0dc7					SP56_Y_POS_H            = $AF0DC7
=$af0dc8					SP57_CONTROL_REG        = $AF0DC8
=$af0dc9					SP57_ADDY_PTR_L         = $AF0DC9
=$af0dca					SP57_ADDY_PTR_M         = $AF0DCA
=$af0dcb					SP57_ADDY_PTR_H         = $AF0DCB
=$af0dcc					SP57_X_POS_L            = $AF0DCC
=$af0dcd					SP57_X_POS_H            = $AF0DCD
=$af0dce					SP57_Y_POS_L            = $AF0DCE
=$af0dcf					SP57_Y_POS_H            = $AF0DCF
=$af0dd0					SP58_CONTROL_REG        = $AF0DD0
=$af0dd1					SP58_ADDY_PTR_L         = $AF0DD1
=$af0dd2					SP58_ADDY_PTR_M         = $AF0DD2
=$af0dd3					SP58_ADDY_PTR_H         = $AF0DD3
=$af0dd4					SP58_X_POS_L            = $AF0DD4
=$af0dd5					SP58_X_POS_H            = $AF0DD5
=$af0dd6					SP58_Y_POS_L            = $AF0DD6
=$af0dd7					SP58_Y_POS_H            = $AF0DD7
=$af0dd8					SP59_CONTROL_REG        = $AF0DD8
=$af0dd9					SP59_ADDY_PTR_L         = $AF0DD9
=$af0dda					SP59_ADDY_PTR_M         = $AF0DDA
=$af0ddb					SP59_ADDY_PTR_H         = $AF0DDB
=$af0ddc					SP59_X_POS_L            = $AF0DDC
=$af0ddd					SP59_X_POS_H            = $AF0DDD
=$af0dde					SP59_Y_POS_L            = $AF0DDE
=$af0ddf					SP59_Y_POS_H            = $AF0DDF
=$af0de0					SP60_CONTROL_REG        = $AF0DE0
=$af0de1					SP60_ADDY_PTR_L         = $AF0DE1
=$af0de2					SP60_ADDY_PTR_M         = $AF0DE2
=$af0de3					SP60_ADDY_PTR_H         = $AF0DE3
=$af0de4					SP60_X_POS_L            = $AF0DE4
=$af0de5					SP60_X_POS_H            = $AF0DE5
=$af0de6					SP60_Y_POS_L            = $AF0DE6
=$af0de7					SP60_Y_POS_H            = $AF0DE7
=$af0de8					SP61_CONTROL_REG        = $AF0DE8
=$af0de9					SP61_ADDY_PTR_L         = $AF0DE9
=$af0dea					SP61_ADDY_PTR_M         = $AF0DEA
=$af0deb					SP61_ADDY_PTR_H         = $AF0DEB
=$af0dec					SP61_X_POS_L            = $AF0DEC
=$af0ded					SP61_X_POS_H            = $AF0DED
=$af0dee					SP61_Y_POS_L            = $AF0DEE
=$af0def					SP61_Y_POS_H            = $AF0DEF
=$af0df0					SP62_CONTROL_REG        = $AF0DF0
=$af0df1					SP62_ADDY_PTR_L         = $AF0DF1
=$af0df2					SP62_ADDY_PTR_M         = $AF0DF2
=$af0df3					SP62_ADDY_PTR_H         = $AF0DF3
=$af0df4					SP62_X_POS_L            = $AF0DF4
=$af0df5					SP62_X_POS_H            = $AF0DF5
=$af0df6					SP62_Y_POS_L            = $AF0DF6
=$af0df7					SP62_Y_POS_H            = $AF0DF7
=$af0df8					SP63_CONTROL_REG        = $AF0DF8
=$af0df9					SP63_ADDY_PTR_L         = $AF0DF9
=$af0dfa					SP63_ADDY_PTR_M         = $AF0DFA
=$af0dfb					SP63_ADDY_PTR_H         = $AF0DFB
=$af0dfc					SP63_X_POS_L            = $AF0DFC
=$af0dfd					SP63_X_POS_H            = $AF0DFD
=$af0dfe					SP63_Y_POS_L            = $AF0DFE
=$af0dff					SP63_Y_POS_H            = $AF0DFF

;******  Return to file: src\vicky_ii_def.asm


;******  Return to file: src\kernel.asm


;******  Processing file: src\super_io_def.asm

=$af1100					PME_STS_REG     = $AF1100
=$af1102					PME_EN_REG		  = $AF1102
=$af1104					PME_STS1_REG		= $AF1104
=$af1105					PME_STS2_REG		= $AF1105
=$af1106					PME_STS3_REG		= $AF1106
=$af1107					PME_STS4_REG		= $AF1107
=$af1108					PME_STS5_REG		= $AF1108
=$af110a					PME_EN1_REG     = $AF110A
=$af110b					PME_EN2_REG     = $AF110B
=$af110c					PME_EN3_REG     = $AF110C
=$af110d					PME_EN4_REG     = $AF110D
=$af110e					PME_EN5_REG     = $AF110E
=$af1110					SMI_STS1_REG		= $AF1110
=$af1111					SMI_STS2_REG		= $AF1111
=$af1112					SMI_STS3_REG		= $AF1112
=$af1113					SMI_STS4_REG		= $AF1113
=$af1114					SMI_STS5_REG		= $AF1114
=$af1116					SMI_EN1_REG     = $AF1116
=$af1117					SMI_EN2_REG     = $AF1117
=$af1118					SMI_EN3_REG     = $AF1118
=$af1119					SMI_EN4_REG     = $AF1119
=$af111a					SMI_EN5_REG     = $AF111A
=$af111c					MSC_ST_REG      = $AF111C
=$af111e					FORCE_DISK_CHANGE       = $AF111E
=$af111f					FLOPPY_DATA_RATE        = $AF111F
=$af1120					UART1_FIFO_CTRL_SHDW    = $AF1120
=$af1121					UART2_FIFO_CTRL_SHDW    = $AF1121
=$af1122					DEV_DISABLE_REG         = $AF1122
=$af1123					GP10_REG    		= $AF1123
=$af1124					GP11_REG    		= $AF1124
=$af1125					GP12_REG    		= $AF1125
=$af1126					GP13_REG    		= $AF1126
=$af1127					GP14_REG    		= $AF1127
=$af1128					GP15_REG    		= $AF1128
=$af1129					GP16_REG    		= $AF1129
=$af112a					GP17_REG    		= $AF112A
=$af112b					GP20_REG    		= $AF112B
=$af112c					GP21_REG    		= $AF112C
=$af112d					GP22_REG		= $AF112D
=$af112f					GP24_REG		= $AF112F
=$af1130					GP25_REG		= $AF1130
=$af1131					GP26_REG		= $AF1131
=$af1132					GP27_REG		= $AF1132
=$af1133					GP30_REG		= $AF1133
=$af1134					GP31_REG		= $AF1134
=$af1135					GP32_REG		= $AF1135
=$af1136					GP33_REG		= $AF1136
=$af1137					GP34_REG		= $AF1137
=$af1138					GP35_REG		= $AF1138
=$af1139					GP36_REG		= $AF1139
=$af113a					GP37_REG		= $AF113A
=$af113b					GP40_REG		= $AF113B
=$af113c					GP41_REG		= $AF113C
=$af113d					GP42_REG		= $AF113D
=$af113e					GP43_REG		= $AF113E
=$af113f					GP50_REG		= $AF113F
=$af1140					GP51_REG		= $AF1140
=$af1141					GP52_REG		= $AF1141
=$af1142					GP53_REG		= $AF1142
=$af1143					GP54_REG		= $AF1143
=$af1144					GP55_REG		= $AF1144
=$af1145					GP56_REG		= $AF1145
=$af1146					GP57_REG		= $AF1146
=$af1147					GP60_REG		= $AF1147
=$af1148					GP61_REG		= $AF1148
=$af114b					GP1_REG			= $AF114B
=$af114c					GP2_REG			= $AF114C
=$af114d					GP3_REG			= $AF114D
=$af114e					GP4_REG			= $AF114E
=$af114f					GP5_REG			= $AF114F
=$af1150					GP6_REG			= $AF1150
=$af1156					FAN1_REG		        = $AF1156
=$af1157					FAN2_REG            = $AF1157
=$af1158					FAN_CTRL_REG  	    = $AF1158
=$af1159					FAN1_TACH_REG       = $AF1159
=$af115a					FAN2_TACH_REG       = $AF115A
=$af115b					FAN1_PRELOAD_REG    = $AF115B
=$af115c					FAN2_PRELOAD_REG    = $AF115C
=$af115d					LED1_REG    		    = $AF115D
=$af115e					LED2_REG    		    = $AF115E
=$af115f					KEYBOARD_SCAN_CODE	= $AF115F

;******  Return to file: src\kernel.asm


;******  Processing file: src\keyboard_def.asm

=$af1064					STATUS_PORT 	= $AF1064
=$af1060					KBD_OUT_BUF 	= $AF1060
=$af1060					KBD_INPT_BUF	= $AF1060
=$af1064					KBD_CMD_BUF		= $AF1064
=$af1060					KBD_DATA_BUF	= $AF1060
=$af1060					PORT_A		    = $AF1060
=$af1061					PORT_B			= $AF1061
=$01						OUT_BUF_FULL    = $01
=$02						INPT_BUF_FULL	= $02
=$04						SYS_FLAG		= $04
=$08						CMD_DATA		= $08
=$10						KEYBD_INH       = $10
=$20						TRANS_TMOUT	    = $20
=$40						RCV_TMOUT		= $40
=$80						PARITY_EVEN		= $80
=$10						INH_KEYBOARD	= $10
=$ae						KBD_ENA			= $AE
=$ad						KBD_DIS			= $AD
=$f1						KB_MENU			= $F1
=$f4						KB_ENABLE		= $F4
=$f7						KB_MAKEBREAK    = $F7
=$fe						KB_ECHO			= $FE
=$ff						KB_RESET		= $FF
=$ed						KB_LED_CMD		= $ED
=$aa						KB_OK			= $AA
=$fa						KB_ACK			= $FA
=$ff						KB_OVERRUN		= $FF
=$fe						KB_RESEND		= $FE
=$f0						KB_BREAK		= $F0
=$10						KB_FA			= $10
=$20						KB_FE			= $20
=$40						KB_PR_LED		= $40
=$01						KB_SCROLL_LOCK  = $01
=$02						KB_NUM_LOCK     = $02
=$04						KB_CAPS_LOCK    = $04
=$80						KB_CTRL_C = $80             ; CTRL-C was pressed
=$60						KB_CREDITS = $60            ; Credits key was pressed

;******  Return to file: src\kernel.asm


;******  Processing file: src\SID_def.asm

=$afe400					SID0_V1_FREQ_LO    = $AFE400 ;SID - L - Voice 1 (Write Only) - FREQ LOW
=$afe401					SID0_V1_FREQ_HI    = $AFE401 ;SID - L - Voice 1 (Write Only) - FREQ HI
=$afe402					SID0_V1_PW_LO      = $AFE402 ;SID - L - Voice 1 (Write Only) - PW LOW
=$afe403					SID0_V1_PW_HI      = $AFE403 ;SID - L - Voice 1 (Write Only) - PW HI
=$afe404					SID0_V1_CTRL       = $AFE404 ;SID - L - Voice 1 (Write Only) - CTRL REG
=$afe405					SID0_V1_ATCK_DECY  = $AFE405 ;SID - L - Voice 1 (Write Only) - ATTACK / DECAY
=$afe406					SID0_V1_SSTN_RLSE  = $AFE406 ;SID - L - Voice 1 (Write Only) - SUSTAIN / RELEASE
=$afe407					SID0_V2_FREQ_LO    = $AFE407 ;SID - L - Voice 2 (Write Only) - FREQ LOW
=$afe408					SID0_V2_FREQ_HI    = $AFE408 ;SID - L - Voice 2 (Write Only) - FREQ HI
=$afe409					SID0_V2_PW_LO      = $AFE409 ;SID - L - Voice 2 (Write Only) - PW LOW
=$afe40a					SID0_V2_PW_HI      = $AFE40A ;SID - L - Voice 2 (Write Only) - PW HI
=$afe40b					SID0_V2_CTRL       = $AFE40B ;SID - L - Voice 2 (Write Only) - CTRL REG
=$afe40c					SID0_V2_ATCK_DECY  = $AFE40C ;SID - L - Voice 2 (Write Only) - ATTACK / DECAY
=$afe40d					SID0_V2_SSTN_RLSE  = $AFE40D ;SID - L - Voice 2 (Write Only) - SUSTAIN / RELEASE
=$afe40e					SID0_V3_FREQ_LO    = $AFE40E ;SID - L - Voice 3 (Write Only) - FREQ LOW
=$afe40f					SID0_V3_FREQ_HI    = $AFE40F ;SID - L - Voice 3 (Write Only) - FREQ HI
=$afe410					SID0_V3_PW_LO      = $AFE410 ;SID - L - Voice 3 (Write Only) - PW LOW
=$afe411					SID0_V3_PW_HI      = $AFE411 ;SID - L - Voice 3 (Write Only) - PW HI
=$afe412					SID0_V3_CTRL       = $AFE412 ;SID - L - Voice 3 (Write Only) - CTRL REG
=$afe413					SID0_V3_ATCK_DECY  = $AFE413 ;SID - L - Voice 3 (Write Only) - ATTACK / DECAY
=$afe414					SID0_V3_SSTN_RLSE  = $AFE414 ;SID - L - Voice 3 (Write Only) - SUSTAIN / RELEASE
=$afe415					SID0_FC_LO         = $AFE415 ;SID - L - Filter (Write Only) - FC LOW
=$afe416					SID0_FC_HI         = $AFE416 ;SID - L - Filter (Write Only) - FC HI
=$afe417					SID0_RES_FILT      = $AFE417 ;SID - L - Filter (Write Only) - RES / FILT
=$afe418					SID0_MODE_VOL      = $AFE418 ;SID - L - Filter (Write Only) - MODE / VOL
=$afe419					SID0_POT_X         = $AFE419 ;SID - L - Misc (Read Only) - POT X (C256 - NOT USED)
=$afe41a					SID0_POT_Y         = $AFE41A ;SID - L - Misc (Read Only) - POT Y (C256 - NOT USED)
=$afe41b					SID0_OSC3_RND      = $AFE41B ;SID - L - Misc (Read Only) - OSC3 / RANDOM
=$afe41c					SID0_ENV3          = $AFE41C ;SID - L - Misc (Read Only)  - ENV3
=$afe41d					SID0_NOT_USED0     = $AFE41D ;SID - L - NOT USED
=$afe41e					SID0_NOT_USED1     = $AFE41E ;SID - L - NOT USED
=$afe41f					SID0_NOT_USED2     = $AFE41F ;SID - L - NOT USED

;******  Return to file: src\kernel.asm


;******  Processing file: src\RTC_def.asm

=$af0800					RTC_SEC       = $AF0800 ;Seconds Register
=$af0801					RTC_SEC_ALARM = $AF0801 ;Seconds Alarm Register
=$af0802					RTC_MIN       = $AF0802 ;Minutes Register
=$af0803					RTC_MIN_ALARM = $AF0803 ;Minutes Alarm Register
=$af0804					RTC_HRS       = $AF0804 ;Hours Register
=$af0805					RTC_HRS_ALARM = $AF0805 ;Hours Alarm Register
=$af0806					RTC_DAY       = $AF0806 ;Day Register
=$af0807					RTC_DAY_ALARM = $AF0807 ;Day Alarm Register
=$af0808					RTC_DOW       = $AF0808 ;Day of Week Register
=$af0809					RTC_MONTH     = $AF0809 ;Month Register
=$af080a					RTC_YEAR      = $AF080A ;Year Register
=$af080b					RTC_RATES     = $AF080B ;Rates Register
=$af080c					RTC_ENABLE    = $AF080C ;Enables Register
=$af080d					RTC_FLAGS     = $AF080D ;Flags Register
=$af080e					RTC_CTRL      = $AF080E ;Control Register
=$af080f					RTC_CENTURY   = $AF080F ;Century Register

;******  Return to file: src\kernel.asm


;******  Processing file: src\io_def.asm

=0						CHAN_CONSOLE  = 0           ; ID for screen and keyboard access
=1						CHAN_COM1     = 1           ; ID for serial access on COM1 (external port)
=2						CHAN_COM2     = 2           ; ID for serial access on COM2 (internal port)
=3						CHAN_LPT      = 3           ; ID for parallel port
=$afe810					SDCARD_DATA   = $AFE810     ;(R/W) SDCARD (CH376S) Data PORT_A (A0 = 0)
=$afe811					SDCARD_CMD    = $AFE811     ;(R/W) SDCARD (CH376S) CMD/STATUS Port (A0 = 1)
=$afe812					SDCARD_STAT   = $AFE812     ;(R) SDCARD (Bit[0] = CD, Bit[1] = WP)
=$01						SDC_DETECTED = $01          ; SD card has been detected (0 = card present, 1 = no card present)
=$02						SDC_WRITEPROT = $02         ; SD card is write protected (0 = card is writeable, 1 = card is write protected or missing)
=$afe900					CODEC_DATA_LO = $AFE900     ;(W) LSB of Add/Data Reg to Control CODEC See WM8776 Spec
=$afe901					CODEC_DATA_HI = $AFE901     ;(W) MSB od Add/Data Reg to Control CODEC See WM8776 Spec
=$afe902					CODEC_WR_CTRL = $AFE902     ;(W) Bit[0] = 1 -> Start Writing the CODEC Control Register

;******  Return to file: src\kernel.asm


;******  Processing file: src\Trinity_CFP9301_def.asm

=$afe800					JOYSTICK0           = $AFE800   ;(R) Joystick 0 - J7 (next to SD Card)
=$afe801					JOYSTICK1           = $AFE801   ;(R) Joystick 1 - J8
=$afe802					JOYSTICK2           = $AFE802   ;(R) Joystick 2 - J9
=$afe803					JOYSTICK3           = $AFE803   ;(R) Joystick 3 - J10 (Next to Buzzer)
=$afe804					JOYSTICK_MODE       = $AFE804
=$01						NES_SNES_EN0        = $01       ; Enable the NES/SNES Mode on Port 0
=$02						NES_SNES_EN1        = $02       ; Enable the NES/SNES Mode on Port 1
=$04						NES_SNES_JOY        = $04       ; 0 = NES, 1 = SNES
=$40						NES_SNES_DONE       = $40       ; Poll to see if the Deserializer is done
=$80						NES_SNES_TRIG       = $80       ; Set to start the Serializer
=$afe805					REVOFPCB_C          = $AFE805   ; You should read the ASCCII for "C"
=$afe806					REVOFPCB_4          = $AFE806   ; You should read the ASCCII for "4"
=$afe807					REVOFPCB_A          = $AFE807   ; You should read the ASCCII for "A"
=$afe808					NES_SNES0_DAT_LO    = $AFE808   ; Contains the 8bits From NES and SNES
=$afe809					SNES0_DAT_HI0       = $AFE809   ; Contains the extra 4 bit from the SNES Controller
=$afe80a					NES_SNES1_DAT_LO    = $AFE80A
=$afe80b					SNES1_DAT_HI0       = $AFE80B
=$afe80c					CFP9301_REV         = $AFE80C   ; Hardware Revision of the CPLD Code
=$afe80d					DIP_USER            = $AFE80D   ; Dip Switch 3/4/5 can be user Defined
=$afe80e					DIP_BOOTMODE        = $AFE80E
=$01						BOOT_MODE0          = $01
=$02						BOOT_MODE1          = $02
=$80						HD_INSTALLED        = $80
=$00						DIP_BOOT_IDE        = $00
=$01						DIP_BOOT_SDCARD     = $01
=$02						DIP_BOOT_FLOPPY     = $02
=$03						DIP_BOOT_BASIC      = $03

;******  Return to file: src\kernel.asm


;******  Processing file: src\Unity_CFP9307_def.asm

=$afe830					IDE_DATA      = $AFE830 ; 8-Bit Access here Only
=$afe831					IDE_ERROR     = $AFE831 ; Error Information register (only read when there is an error ) - Probably clears Error Bits
=$afe832					IDE_SECT_CNT  = $AFE832 ; Sector Count Register (also used to pass parameter for timeout for IDLE modus Command)
=$afe833					IDE_SECT_SRT  = $AFE833 ; Start Sector Register (0 = 256), so start @ 1
=$afe834					IDE_CLDR_LO   = $AFE834 ; Low Byte of Cylinder Numnber {7:0}
=$afe835					IDE_CLDR_HI   = $AFE835 ;  Hi Byte of Cylinder Number {9:8} (1023-0).
=$afe836					IDE_HEAD      = $AFE836 ; Head, device select, {3:0} HEad Number, 4 -> 0:Master, 1:Slave, {7:5} = 101 (legacy);
=$afe837					IDE_CMD_STAT  = $AFE837 ; Command/Status Register - Reading this will clear the Interrupt Registers
=$afe838					IDE_DATA_LO   = $AFE838 ; 16-bit access here
=$afe839					IDE_DATA_HI   = $AFE839 ;
=$01						IDE_ERR_AMNF = $01      ; Error: Address mark not found
=$02						IDE_ERR_TKZNF = $02     ; Error: Track 0 not found
=$04						IDE_ERR_ABRT = $04      ; Error: Aborted command
=$08						IDE_ERR_MCR = $08       ; Error: Media change request
=$10						IDE_ERR_IDNF = $10      ; Error: ID not found
=$20						IDE_ERR_MC = $20        ; Error: Media change
=$40						IDE_ERR_UNC = $40       ; Error: Uncorrectable data error
=$80						IDE_ERR_BBK = $80       ; Error: Bad block detected
=$80						IDE_STAT_BSY = $80      ; BSY (Busy) is set whenever the device has control of the command Block Registers.
=$40						IDE_STAT_DRDY = $40     ; DRDY (Device Ready) is set to indicate that the device is capable of accepting all command codes.
=$20						IDE_STAT_DF = $20       ; DF (Device Fault) indicates a device fault error has been detected.
=$10						IDE_STAT_DSC = $10      ; DSC (Device Seek Complete) indicates that the device heads are settled over a track.
=$08						IDE_STAT_DRQ = $08      ; DRQ (Data Request) indicates that the device is ready to transfer a word or byte of data between
=$04						IDE_STAT_CORR = $04     ; CORR (Corrected Data) is used to indicate a correctable data error.
=$02						IDE_STAT_IDX = $02      ; Vendor specific bit
=$01						IDE_STAT_ERR = $01      ; ERR (Error) indicates that an error occurred during execution of the previous command.
=$ec						IDE_CMD_IDENTIFY = $EC      ; Get device identification data
=$21						IDE_CMD_READ_SECTOR = $21   ; Read 1 or more sectors
=$30						IDE_CMD_WRITE_SECTOR = $30  ; Write 1 or more sectors

;******  Return to file: src\kernel.asm


;******  Processing file: src\GABE_Control_Registers_def.asm

=$afe880					GABE_MSTR_CTRL      = $AFE880
=$01						GABE_CTRL_PWR_LED   = $01     ; Controls the LED in the Front of the case (Next to the reset button)
=$02						GABE_CTRL_SDC_LED   = $02     ; Controls the LED in the Front of the Case (Next to SDCard)
=$10						GABE_CTRL_BUZZER    = $10     ; Controls the Buzzer
=$80						GABE_CTRL_WRM_RST   = $80     ; Warm Reset (needs to Setup other registers)
=$afe881					GABE_NOTUSED        = $AFE881 ; Reserved for future use
=$afe882					GABE_RST_AUTH0      = $AFE882 ; Must Contain the BYTE $AD for Reset to Activate
=$afe883					GABE_RST_AUTH1      = $AFE883 ; Must Contain the BYTE $DE for Reset to Activate
=$afe884					GABE_RNG_DAT_LO     = $AFE884 ; Low Part of 16Bit RNG Generator
=$afe885					GABE_RNG_DAT_HI     = $AFE885 ; Hi Part of 16Bit RNG Generator
=$afe884					GABE_RNG_SEED_LO    = $AFE884 ; Low Part of 16Bit RNG Generator
=$afe885					GABE_RNG_SEED_HI    = $AFE885 ; Hi Part of 16Bit RNG Generator
=$afe886					GABE_RNG_STAT       = $AFE886 ;
=$80						GABE_RNG_LFSR_DONE  = $80     ; indicates that Output = SEED Database
=$afe886					GABE_RNG_CTRL       = $AFE886 ;
=$01						GABE_RNG_CTRL_EN    = $01     ; Enable the LFSR BLOCK_LEN
=$02						GABE_RNG_CTRL_DV    = $02     ; After Setting the Seed Value, Toggle that Bit for it be registered
=$afe887					GABE_SYS_STAT       = $AFE887 ;
=$01						GABE_SYS_STAT_MID0  = $01     ; Machine ID -- LSB
=$02						GABE_SYS_STAT_MID1  = $02     ; Machine ID -- MSB
=$08						GABE_SYS_STAT_EXP   = $08     ; if Zero, there is an Expansion Card Preset
=$40						GABE_SYS_STAT_CPUA  = $40     ; Indicates the (8bit/16bit) Size of the Accumulator
=$80						GABE_SYS_STAT_CPUX  = $80     ; Indicates the (8bit/16bit) Size of the Accumulator

;******  Return to file: src\kernel.asm


;******  Processing file: src\fdc_inc.asm

=$af13f0					SIO_FDC  = $AF13F0
=$af13f0					SIO_FDC_SRA = $AF13F0 ; Read Only - Status Register A (not used in AT mode)
=$af13f1					SIO_FDC_SRB = $AF13F1 ; Read Only - Status Register B (not used in AT mode)
=$af13f2					SIO_FDC_DOR = $AF13F2 ; Read/Write - Digital Output Register
=$01						FDC_DOR_DSEL0 = $01     ; Drive 0 Select
=$02						FDC_DOR_DSEL1 = $02     ; Drive 1 Select
=$04						FDC_DOR_NRESET = $04    ; Reset the FDC
=$08						FDC_DOR_DMAEN = $08     ; Enable DMA
=$10						FDC_DOR_MOT0  = $10     ; Turn on motor 0
=$20						FDC_DOR_MOT1  = $20     ; Turn on motor 1
=$40						FDC_DOR_MOT2  = $40     ; Turn on motor 2
=$80						FDC_DOR_MOT3  = $80     ; Turn on motor 3
=$af13f3					SIO_FDC_TSR = $AF13F3   ; Read/Write - Tape Drive Status (not used on the C256)
=$af13f4					SIO_FDC_MSR = $AF13F4   ; Read - Main Status Register
=$01						FDC_MSR_DRV0BSY = $01   ; Indicates if drive 0 is busy
=$02						FDC_MSR_DRV1BSY = $02   ; Indicates if drive 1 is busy
=$10						FDC_MSR_CMDBSY = $10    ; Indicates if a command is in progress
=$20						FDC_MSR_NONDMA = $20    ;
=$40						FDC_MSR_DIO = $40       ; Data direction: 1 = read, 0 = write
=$80						FDC_MSR_RQM = $80       ; 1 = host can transfer data, 0 = host must wait
=$af13f4					SIO_FDC_DSR = $AF13F4   ; Write - Data Select Register
=$40						FDC_DSR_LOPWR = $40     ; Turn on low power mode
=$80						FDC_DSR_RESET = $80     ; Software reset of the FDC
=$af13f5					SIO_FDC_DTA = $AF13F5   ; Read/Write - Data - FIFO
=$af13f6					SIO_FDC_RSV = $AF13F6   ; Reserved
=$af13f7					SIO_FDC_DIR = $AF13F7   ; Read - Digital Input Register
=$80						FDC_DIR_DSKCHG = $80    ; Indicates if the disk has changed
=$af13f7					SIO_FDC_CCR = $AF13F7   ; Write - Configuration Control Register
=$03						FDC_ST0_DRVSEL = $03    ; Mask for the current selected drive
=$04						FDC_ST0_HEAD = $04      ; Bit for the current selected head
=$08						FDC_ST0_EC = $08        ; Bit for EQUIPMENT CHECK, error in recalibrate or relative seek
=$10						FDC_ST0_SEEKEND = $10   ; The FDC completed a seek, relative seek, or recalibrate
=$c0						FDC_ST0_INTCODE = $C0   ; Mask for interrupt code:
=$01						FDC_ST1_MA = $01        ; Missing address mark
=$02						FDC_ST1_NW = $02        ; Not writable (disk is write protected)
=$04						FDC_ST1_ND = $04        ; No data
=$10						FDC_ST1_OR = $10        ; Overrun/underrun of the data
=$20						FDC_ST1_DE = $20        ; Data error... a CRC check failed
=$80						FDC_ST1_EN = $80        ; End of cylinder: tried to acess a sector not on the track
=$01						FDC_ST2_MD = $01        ; Missing address mark: FDC cannot detect a data address mark
=$02						FDC_ST2_BC = $02        ; Bad cylinder
=$10						FDC_ST2_WC = $10        ; Wrong cylinder: track is not the same as expected
=$20						FDC_ST2_DD = $20        ; Data error in field: CRC error
=$40						FDC_ST2_CM = $40        ; Control mark
=$03						FDC_ST3_DRVSEL = $03    ; Drive select mask
=$04						FDC_ST3_HEAD = $04      ; Head address bit
=$10						FDC_ST3_TRACK0 = $10    ; Track 0: Status of the TRK0 pin
=$40						FDC_ST3_WP = $40        ; Write Protect: status of the WP pin
=2						FDC_CMD_READ_TRACK          = 2
=3						FDC_CMD_SPECIFY             = 3
=4						FDC_CMD_SENSE_DRIVE_STATUS  = 4
=5						FDC_CMD_WRITE_DATA          = 5
=6						FDC_CMD_READ_DATA           = 6
=7						FDC_CMD_RECALIBRATE         = 7
=8						FDC_CMD_SENSE_INTERRUPT     = 8
=9						FDC_CMD_WRITE_DELETED_DATA  = 9
=10						FDC_CMD_READ_ID             = 10
=12						FDC_CMD_READ_DELETED_DATA   = 12
=13						FDC_CMD_FORMAT_TRACK        = 13
=14						FDC_CMD_DUMPREG             = 14
=15						FDC_CMD_SEEK                = 15
=16						FDC_CMD_VERSION             = 16
=17						FDC_CMD_SCAN_EQUAL          = 17
=18						FDC_CMD_PERPENDICULAR_MODE  = 18
=19						FDC_CMD_CONFIGURE           = 19
=20						FDC_CMD_LOCK                = 20
=22						FDC_CMD_VERIFY              = 22
=25						FDC_CMD_SCAN_LOW_OR_EQUAL   = 25
=29						FDC_CMD_SCAN_HIGH_OR_EQUAL  = 29
=$80						FDC_CMD_MT = $80                    ; Command bit to turn on multi-track
=$40						FDC_CMD_MFM = $40                   ; Command bit to operate in MFM format
=$20						FDC_CMD_SK = $20                    ; Command bit to skip deleted sectors
=$40						FDC_CMD_EIS = $40                   ; Command bit to turn on implied seek
=1						FDC_DEVCMD_MOTOR_ON         = 1     ; Device code to turn the motor on
=2						FDC_DEVCMD_MOTOR_OFF        = 2     ; Device code to turn the motor off
=3						FDC_DEVCMD_RECAL            = 3     ; Device code to recalibrate the drive

;******  Return to file: src\kernel.asm


;******  Processing file: src\timer_def.asm

=$000160					TIMER0_CTRL_REG   = $000160 ; (Write - Control, Read Status)
=$01						TMR0_EN     = $01
=$02						TMR0_SCLR   = $02
=$04						TMR0_SLOAD  = $04 ; Use SLOAD is
=$08						TMR0_UPDWN  = $08
=$000161					TIMER0_CHARGE_L   = $000161 ; Use if you want to Precharge and countdown
=$000162					TIMER0_CHARGE_M   = $000162 ;
=$000163					TIMER0_CHARGE_H   = $000163 ;
=$000164					TIMER0_CMP_REG    = $000164 ;
=$01						TMR0_CMP_RECLR     = $01 ; set to one for it to cycle when Counting up
=$02						TMR0_CMP_RELOAD    = $02 ; Set to one for it to reload when Counting Down
=$000165					TIMER0_CMP_L      = $000165 ; Load this Value for Countup
=$000166					TIMER0_CMP_M      = $000166 ;
=$000167					TIMER0_CMP_H      = $000167 ;
=$000168					TIMER1_CTRL_REG   = $000168 ;
=$01						TMR1_EN     = $01
=$02						TMR1_SCLR   = $02
=$04						TMR1_SLOAD  = $04
=$08						TMR1_UPDWN  = $08 ; 1 = Up, 0 = Down
=$000169					TIMER1_CHARGE_L   = $000169 ; Use if you want to Precharge and countdown
=$00016a					TIMER1_CHARGE_M   = $00016A ;
=$00016b					TIMER1_CHARGE_H   = $00016B ;
=$00016c					TIMER1_CMP_REG    = $00016C ;
=$01						TMR1_CMP_RECLR     = $01 ; set to one for it to cycle when Counting up
=$02						TMR1_CMP_RELOAD    = $02 ; Set to one for it to reload when Counting Down
=$00016d					TIMER1_CMP_L      = $00016D ;
=$00016e					TIMER1_CMP_M      = $00016E ;
=$00016f					TIMER1_CMP_H      = $00016F ;

;******  Return to file: src\kernel.asm


;******  Processing file: src\basic_inc.asm

=$3a0000					BASIC = $3A0000
=3801092					MONITOR = BASIC + 4

;******  Return to file: src\kernel.asm


;******  Processing file: src\kernel_jumptable.asm

.381000	1000	5c 00 04 39	jmp $390400	BOOT            JML IBOOT
.381004	1004	5c ac 05 39	jmp $3905ac	RESTORE         JML IRESTORE
.381008	1008	5c a4 06 39	jmp $3906a4	BREAK           JML IBREAK
.38100c	100c	5c eb 06 39	jmp $3906eb	READY           JML IREADY
.381010	1010	5c d1 16 39	jmp $3916d1	SCINIT          JML ISCINIT
.381014	1014	5c d2 16 39	jmp $3916d2	IOINIT          JML IIOINIT
.381018	1018	5c 9e 07 39	jmp $39079e	PUTC            JML IPUTC
.38101c	101c	5c 87 07 39	jmp $390787	PUTS            JML IPUTS
.381020	1020	5c 16 09 39	jmp $390916	PUTB            JML IPUTB
.381024	1024	5c b6 41 39	jmp $3941b6	PUTBLOCK        JML IPUTBLOCK
.381028	1028	5c d3 16 39	jmp $3916d3	SETLFS          JML ISETLFS
.38102c	102c	5c d4 16 39	jmp $3916d4	SETNAM          JML ISETNAM
.381030	1030	5c d5 16 39	jmp $3916d5	OPEN            JML IOPEN
.381034	1034	5c d6 16 39	jmp $3916d6	CLOSE           JML ICLOSE
.381038	1038	5c 06 07 39	jmp $390706	SETIN           JML ISETIN
.38103c	103c	5c 0f 07 39	jmp $39070f	SETOUT          JML ISETOUT
.381040	1040	5c d7 16 39	jmp $3916d7	GETB            JML IGETB
.381044	1044	5c 53 41 39	jmp $394153	GETBLOCK        JML IGETBLOCK
.381048	1048	5c 48 07 39	jmp $390748	GETCH           JML IGETCH
.38104c	104c	5c 21 07 39	jmp $390721	GETCHW          JML IGETCHW
.381050	1050	5c 18 07 39	jmp $390718	GETCHE          JML IGETCHE
.381054	1054	5c d8 16 39	jmp $3916d8	GETS            JML IGETS
.381058	1058	5c d9 16 39	jmp $3916d9	GETLINE         JML IGETLINE
.38105c	105c	5c da 16 39	jmp $3916da	GETFIELD        JML IGETFIELD
.381060	1060	5c db 16 39	jmp $3916db	TRIM            JML ITRIM
.381064	1064	5c dc 16 39	jmp $3916dc	PRINTC          JML IPRINTC
.381068	1068	5c dd 16 39	jmp $3916dd	PRINTS          JML IPRINTS
.38106c	106c	5c 17 09 39	jmp $390917	PRINTCR         JML IPRINTCR
.381070	1070	5c de 16 39	jmp $3916de	PRINTF          JML IPRINTF
.381074	1074	5c df 16 39	jmp $3916df	PRINTI          JML IPRINTI
.381078	1078	5c d7 0a 39	jmp $390ad7	PRINTH          JML IPRINTH
.38107c	107c	5c e0 16 39	jmp $3916e0	PRINTAI         JML IPRINTAI
.381080	1080	5c f4 0a 39	jmp $390af4	PRINTAH         JML IPRINTAH
.381084	1084	5c 1b 0a 39	jmp $390a1b	LOCATE          JML ILOCATE
.381088	1088	5c e1 16 39	jmp $3916e1	PUSHKEY         JML IPUSHKEY
.38108c	108c	5c e2 16 39	jmp $3916e2	PUSHKEYS        JML IPUSHKEYS
.381090	1090	5c 77 09 39	jmp $390977	CSRRIGHT        JML ICSRRIGHT
.381094	1094	5c aa 09 39	jmp $3909aa	CSRLEFT         JML ICSRLEFT
.381098	1098	5c d0 09 39	jmp $3909d0	CSRUP           JML ICSRUP
.38109c	109c	5c f6 09 39	jmp $3909f6	CSRDOWN         JML ICSRDOWN
.3810a0	10a0	5c 66 09 39	jmp $390966	CSRHOME         JML ICSRHOME
.3810a4	10a4	5c 67 0a 39	jmp $390a67	SCROLLUP        JML ISCROLLUP
.3810a8	10a8	5c 42 0b 39	jmp $390b42	CLRSCREEN       JML ICLRSCREEN
.3810ac	10ac	5c 0d 0c 39	jmp $390c0d	INITCHLUT	    JML IINITCHLUT
.3810b0	10b0	5c f9 0f 39	jmp $390ff9	INITSUPERIO	    JML IINITSUPERIO
.3810b4	10b4	5c f8 10 39	jmp $3910f8	INITKEYBOARD    JML IINITKEYBOARD
.3810b8	10b8	5c 63 12 39	jmp $391263	TESTSID         JML ITESTSID
.3810bc	10bc	5c d8 0f 39	jmp $390fd8	INITCURSOR      JML IINITCURSOR
.3810c0	10c0	5c a0 0f 39	jmp $390fa0	INITFONTSET     JML IINITFONTSET
.3810c4	10c4	5c 3c 0c 39	jmp $390c3c	INITGAMMATABLE  JML IINITGAMMATABLE
.3810c8	10c8	5c 5c 0c 39	jmp $390c5c	INITALLLUT      JML IINITALLLUT
.3810cc	10cc	5c 1e 0d 39	jmp $390d1e	INITVKYTXTMODE  JML IINITVKYTXTMODE
.3810d0	10d0	5c 2b 0e 39	jmp $390e2b	INITVKYGRPMODE  JML IINITVKYGRPMODE
.3810d4	10d4	5c 62 0e 39	jmp $390e62	INITTILEMODE    JML IINITTILEMODE
.3810d8	10d8	5c 63 0e 39	jmp $390e63	INITSPRITE      JML IINITSPRITE
.3810dc	10dc	5c 32 13 39	jmp $391332	INITCODEC       JML IINITCODEC
.3810e0	10e0	5c ae 13 39	jmp $3913ae	RESETCODEC      JML IRESETCODEC
.3810e4	10e4	5c 1c 14 39	jmp $39141c	BMP_PARSER      JML IBMP_PARSER
.3810e8	10e8	5c d1 13 39	jmp $3913d1	BM_FILL_SCREEN  JML IBM_FILL_SCREEN
.3810ec	10ec	5c 5f 37 39	jmp $39375f	OPL2_TONE_TEST  JML IOPL2_TONE_TEST
.3810f0	10f0	5c 35 54 39	jmp $395435	F_OPEN          JML IF_OPEN         ; open a file for reading/writing/creating
.3810f4	10f4	5c c8 54 39	jmp $3954c8	F_CREATE        JML IF_CREATE       ; create a new file
.3810f8	10f8	5c 02 55 39	jmp $395502	F_CLOSE         JML IF_CLOSE        ; close a file (make sure last cluster is written)
.3810fc	10fc	5c 9b 55 39	jmp $39559b	F_WRITE         JML IF_WRITE        ; write the current cluster to the file
.381100	1100	5c 36 55 39	jmp $395536	F_READ          JML IF_READ         ; read the next cluster from the file
.381104	1104	5c 45 56 39	jmp $395645	F_DELETE        JML IF_DELETE       ; delete a file / directory
.381108	1108	5c 07 56 39	jmp $395607	F_DIROPEN       JML IF_DIROPEN      ; open a directory and seek the first directory entry
.38110c	110c	5c 41 56 39	jmp $395641	F_DIRNEXT       JML IF_DIRNEXT      ; seek to the next directory of an open directory
.381110	1110	5c de 56 39	jmp $3956de	F_DIRREAD       JML IF_DIRREAD      ; Read the directory entry for the specified file
.381114	1114	5c 05 57 39	jmp $395705	F_DIRWRITE      JML IF_DIRWRITE     ; Write any changes in the current directory cluster back to the drive
.381118	1118	5c 09 57 39	jmp $395709	F_LOAD          JML IF_LOAD         ; load a binary file into memory, supports multiple file formats
.38111c	111c	5c f9 58 39	jmp $3958f9	F_SAVE          JML IF_SAVE         ; Save memory to a binary file
.381120	1120	5c 29 41 39	jmp $394129	CMDBLOCK        JML ICMDBLOCK       ; Send a command to a block device
.381124	1124	5c 92 59 39	jmp $395992	F_RUN           JML IF_RUN          ; Load an run a binary file
.381128	1128	5c 54 45 39	jmp $394554	F_MOUNT         JML DOS_MOUNT       ; Mount the designated block device
.38112c	112c	5c 78 0d 39	jmp $390d78	SETSIZES        JML ISETSIZES
.381130	1130	5c bb 5a 39	jmp $395abb	F_COPY          JML IF_COPY         ; Copy a file
.381134	1134	5c 1d 5a 39	jmp $395a1d	F_ALLOCFD       JML IF_ALLOCFD      ; Allocate a file descriptor
.381138	1138	5c 71 5a 39	jmp $395a71	F_FREEFD        JML IF_FREEFD       ; Free a file descriptor
.381700	1700	5c 13 6a 39	jmp $396a13	VEC_INT00_SOF   JML FDC_TIME_HANDLE ; IRQ 0, 0 --- Start Of Frame interrupt
.381704	1704	5c e5 16 39	jmp $3916e5	VEC_INT01_SOL   JML IRQHANDLESTUB   ; IRQ 0, 1 --- Start Of Line interrupt
.381708	1708	5c e5 16 39	jmp $3916e5	VEC_INT02_TMR0  JML IRQHANDLESTUB   ; IRQ 0, 2 --- Timer 0 interrupt
.38170c	170c	5c e5 16 39	jmp $3916e5	VEC_INT03_TMR1  JML IRQHANDLESTUB   ; IRQ 0, 3 --- Timer 1 interrupt
.381710	1710	5c e5 16 39	jmp $3916e5	VEC_INT04_TMR2  JML IRQHANDLESTUB   ; IRQ 0, 4 --- Timer 2 interrupt

;******  Return to file: src\kernel.asm


;******  Processing file: src\Interrupt_Handler.asm

.381714						IRQ_HANDLER
.381714		e2 20		sep #$20	                SEP #$20        ; set A short
.381716		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.38171a		c9 00		cmp #$00	                CMP #$00
.38171c		f0 7d		beq $38179b	                BEQ CHECK_PENDING_REG1
.38171e		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.381722		29 01		and #$01	                AND #FNX0_INT00_SOF
.381724		c9 01		cmp #$01	                CMP #FNX0_INT00_SOF
.381726		d0 09		bne $381731	                BNE SERVICE_NEXT_IRQ1
.381728		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.38172c		20 09 18	jsr $381809	                JSR SOF_INTERRUPT
.38172f		e2 20		sep #$20	                SEP #$20        ; set A short
.381731						SERVICE_NEXT_IRQ1
.381731		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.381735		29 02		and #$02	                AND #FNX0_INT01_SOL
.381737		c9 02		cmp #$02	                CMP #FNX0_INT01_SOL
.381739		d0 07		bne $381742	                BNE SERVICE_NEXT_IRQ2
.38173b		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.38173f		20 1a 18	jsr $38181a	                JSR SOL_INTERRUPT
.381742						SERVICE_NEXT_IRQ2
.381742		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.381746		29 04		and #$04	                AND #FNX0_INT02_TMR0
.381748		c9 04		cmp #$04	                CMP #FNX0_INT02_TMR0
.38174a		d0 07		bne $381753	                BNE SERVICE_NEXT_IRQ3
.38174c		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.381750		20 2b 18	jsr $38182b	                JSR TIMER0_INTERRUPT
.381753						SERVICE_NEXT_IRQ3
.381753		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.381757		29 08		and #$08	                AND #FNX0_INT03_TMR1
.381759		c9 08		cmp #$08	                CMP #FNX0_INT03_TMR1
.38175b		d0 07		bne $381764	                BNE SERVICE_NEXT_IRQ4
.38175d		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.381761		20 3c 18	jsr $38183c	                JSR TIMER1_INTERRUPT
.381764						SERVICE_NEXT_IRQ4
.381764		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.381768		29 10		and #$10	                AND #FNX0_INT04_TMR2
.38176a		c9 10		cmp #$10	                CMP #FNX0_INT04_TMR2
.38176c		d0 09		bne $381777	                BNE SERVICE_NEXT_IRQ6
.38176e		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.381772		20 4d 18	jsr $38184d	                JSR TIMER2_INTERRUPT
.381775		e2 20		sep #$20	                SEP #$20        ; set A short
.381777						SERVICE_NEXT_IRQ6
.381777		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.38177b		29 40		and #$40	                AND #FNX0_INT06_FDC
.38177d		c9 40		cmp #$40	                CMP #FNX0_INT06_FDC
.38177f		d0 09		bne $38178a	                BNE SERVICE_NEXT_IRQ7
.381781		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.381785		20 9e 18	jsr $38189e	                JSR FDC_INTERRUPT
.381788		e2 20		sep #$20	                SEP #$20        ; set A short
.38178a						SERVICE_NEXT_IRQ7
.38178a		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.38178e		29 80		and #$80	                AND #FNX0_INT07_MOUSE
.381790		c9 80		cmp #$80	                CMP #FNX0_INT07_MOUSE
.381792		d0 07		bne $38179b	                BNE CHECK_PENDING_REG1
.381794		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.381798		20 5e 18	jsr $38185e	                JSR MOUSE_INTERRUPT
.38179b						CHECK_PENDING_REG1
.38179b		e2 20		sep #$20	                SEP #$20        ; set A short
.38179d		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3817a1		c9 00		cmp #$00	                CMP #$00
.3817a3		f0 61		beq $381806	                BEQ EXIT_IRQ_HANDLE
.3817a5						SERVICE_NEXT_IRQ8
.3817a5		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3817a9		29 01		and #$01	                AND #FNX1_INT00_KBD
.3817ab		c9 01		cmp #$01	                CMP #FNX1_INT00_KBD
.3817ad		d0 0d		bne $3817bc	                BNE SERVICE_NEXT_IRQ11
.3817af		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.3817b3		8b		phb		                PHB
.3817b4		0b		phd		                PHD
.3817b5		20 d6 18	jsr $3818d6	                JSR KEYBOARD_INTERRUPT
.3817b8		2b		pld		                PLD
.3817b9		ab		plb		                PLB
.3817ba		e2 20		sep #$20	                SEP #$20        ; set A short
.3817bc						SERVICE_NEXT_IRQ11
.3817bc		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3817c0		29 08		and #$08	                AND #FNX1_INT03_COM2
.3817c2		c9 08		cmp #$08	                CMP #FNX1_INT03_COM2
.3817c4		d0 09		bne $3817cf	                BNE SERVICE_NEXT_IRQ12
.3817c6		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.3817ca		20 a9 18	jsr $3818a9	                JSR COM2_INTERRUPT
.3817cd		e2 20		sep #$20	                SEP #$20        ; set A short
.3817cf						SERVICE_NEXT_IRQ12
.3817cf		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3817d3		29 10		and #$10	                AND #FNX1_INT04_COM1
.3817d5		c9 10		cmp #$10	                CMP #FNX1_INT04_COM1
.3817d7		d0 09		bne $3817e2	                BNE SERVICE_NEXT_IRQ13
.3817d9		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.3817dd		20 b4 18	jsr $3818b4	                JSR COM1_INTERRUPT
.3817e0		e2 20		sep #$20	                SEP #$20        ; set A short
.3817e2						SERVICE_NEXT_IRQ13
.3817e2		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3817e6		29 20		and #$20	                AND #FNX1_INT05_MPU401
.3817e8		c9 20		cmp #$20	                CMP #FNX1_INT05_MPU401
.3817ea		d0 09		bne $3817f5	                BNE SERVICE_NEXT_IRQ14
.3817ec		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.3817f0		20 bf 18	jsr $3818bf	                JSR MPU401_INTERRUPT
.3817f3		e2 20		sep #$20	                SEP #$20        ; set A short
.3817f5						SERVICE_NEXT_IRQ14
.3817f5		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3817f9		29 40		and #$40	                AND #FNX1_INT06_LPT
.3817fb		c9 40		cmp #$40	                CMP #FNX1_INT06_LPT
.3817fd		d0 07		bne $381806	                BNE EXIT_IRQ_HANDLE
.3817ff		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.381803		20 ca 18	jsr $3818ca	                JSR LPT1_INTERRUPT
.381806						EXIT_IRQ_HANDLE
.381806		c2 30		rep #$30	                REP #$30        ; set A&X long
.381808		6b		rtl		                RTL
.381809						SOF_INTERRUPT
.381809		e2 20		sep #$20	                SEP #$20        ; set A short
.38180b		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.38180f		29 01		and #$01	                AND #FNX0_INT00_SOF
.381811		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.381815		22 00 17 00	jsl $001700	                JSL VEC_INT00_SOF
.381819		60		rts		                RTS
.38181a						SOL_INTERRUPT
.38181a		e2 20		sep #$20	                SEP #$20        ; set A short
.38181c		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.381820		29 02		and #$02	                AND #FNX0_INT01_SOL
.381822		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.381826		22 04 17 00	jsl $001704	                JSL VEC_INT01_SOL
.38182a		60		rts		                RTS
.38182b						TIMER0_INTERRUPT
.38182b		e2 20		sep #$20	                SEP #$20        ; set A short
.38182d		af 05 07 00	lda $000705	                LDA @l TIMERFLAGS               ; Flag that the interrupt has happened
.381831		09 80		ora #$80	                ORA #TIMER0TRIGGER
.381833		8f 05 07 00	sta $000705	                STA @l TIMERFLAGS
.381837		22 08 17 00	jsl $001708	                JSL VEC_INT02_TMR0
.38183b		60		rts		                RTS
.38183c						TIMER1_INTERRUPT
.38183c		e2 20		sep #$20	                SEP #$20        ; set A short
.38183e		af 05 07 00	lda $000705	                LDA @l TIMERFLAGS               ; Flag that the interrupt has happened
.381842		09 40		ora #$40	                ORA #TIMER1TRIGGER
.381844		8f 05 07 00	sta $000705	                STA @l TIMERFLAGS
.381848		22 0c 17 00	jsl $00170c	                JSL VEC_INT03_TMR1
.38184c		60		rts		                RTS
.38184d						TIMER2_INTERRUPT
.38184d		e2 20		sep #$20	                SEP #$20        ; set A short
.38184f		af 05 07 00	lda $000705	                LDA @l TIMERFLAGS               ; Flag that the interrupt has happened
.381853		09 20		ora #$20	                ORA #TIMER2TRIGGER
.381855		8f 05 07 00	sta $000705	                STA @l TIMERFLAGS
.381859		22 10 17 00	jsl $001710	                JSL VEC_INT04_TMR2
.38185d		60		rts		                RTS
.38185e						MOUSE_INTERRUPT
.38185e		e2 30		sep #$30	                SEP #$30        ; set A&X short
.381860		af e0 00 00	lda $0000e0	                LDA @l MOUSE_PTR
.381864		aa		tax		                TAX
.381865		af 60 10 af	lda $af1060	                LDA @l KBD_INPT_BUF
.381869		9f 06 07 af	sta $af0706,x	                STA @lMOUSE_PTR_BYTE0, X
.38186d		e8		inx		                INX
.38186e		e0 03		cpx #$03	                CPX #$03
.381870		d0 24		bne $381896	                BNE EXIT_FOR_NEXT_VALUE
.381872		af 02 07 af	lda $af0702	                LDA @l MOUSE_PTR_X_POS_L
.381876		8f e1 00 00	sta $0000e1	                STA @l MOUSE_POS_X_LO
.38187a		af 03 07 af	lda $af0703	                LDA @l MOUSE_PTR_X_POS_H
.38187e		8f e2 00 00	sta $0000e2	                STA @l MOUSE_POS_X_HI
.381882		af 04 07 af	lda $af0704	                LDA @l MOUSE_PTR_Y_POS_L
.381886		8f e3 00 00	sta $0000e3	                STA @l MOUSE_POS_Y_LO
.38188a		af 05 07 af	lda $af0705	                LDA @l MOUSE_PTR_Y_POS_H
.38188e		8f e4 00 00	sta $0000e4	                STA @l MOUSE_POS_Y_HI
.381892		e2 20		sep #$20	                SEP #$20        ; set A short
.381894		a2 00		ldx #$00	                LDX #$00
.381896						EXIT_FOR_NEXT_VALUE
.381896		8a		txa		                TXA
.381897		8f e0 00 00	sta $0000e0	                STA @l MOUSE_PTR
.38189b		c2 10		rep #$10	                REP #$10        ; set X long
.38189d		60		rts		                RTS
.38189e						FDC_INTERRUPT
.38189e		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
.3818a2		29 40		and #$40	                AND #FNX0_INT06_FDC
.3818a4		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
.3818a8		60		rts		                RTS
.3818a9						COM2_INTERRUPT
.3818a9		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3818ad		29 08		and #$08	                AND #FNX1_INT03_COM2
.3818af		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.3818b3		60		rts		                RTS
.3818b4						COM1_INTERRUPT
.3818b4		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3818b8		29 10		and #$10	                AND #FNX1_INT04_COM1
.3818ba		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.3818be		60		rts		                RTS
.3818bf						MPU401_INTERRUPT
.3818bf		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3818c3		29 20		and #$20	                AND #FNX1_INT05_MPU401
.3818c5		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.3818c9		60		rts		                RTS
.3818ca						LPT1_INTERRUPT
.3818ca		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3818ce		29 40		and #$40	                AND #FNX1_INT06_LPT
.3818d0		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.3818d4		60		rts		                RTS
.3818d5						NMI_HANDLER
.3818d5		6b		rtl		                RTL

;******  Return to file: src\kernel.asm


;******  Processing file: src\keyboard.asm

.3818d6						KEYBOARD_INTERRUPT
.3818d6		48		pha		                PHA             ; begin setdp macro
.3818d7		08		php		                PHP
.3818d8		c2 20		rep #$20	                REP #$20        ; set A long
.3818da		a9 00 0f	lda #$0f00	                LDA #KEY_BUFFER         ; set DP to page 0
.3818dd		5b		tcd		                TCD
.3818de		28		plp		                PLP
.3818df		68		pla		                PLA             ; end setdp macro
.3818e0		a2 00 00	ldx #$0000	                ldx #$0000
.3818e3		e2 10		sep #$10	                SEP #$10        ; set X short
.3818e5		e2 20		sep #$20	                SEP #$20        ; set A short
.3818e7		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
.3818eb		29 01		and #$01	                AND #FNX1_INT00_KBD
.3818ed		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
.3818f1						IRQ_HANDLER_FETCH
.3818f1		af 60 10 af	lda $af1060	                LDA @lKBD_INPT_BUF      ; Get Scan Code from KeyBoard
.3818f5		85 88		sta $0f88	                STA KEYBOARD_SC_TMP     ; Save Code Immediately
.3818f7		a5 87		lda $0f87	                LDA KEYBOARD_SC_FLG     ; Check to See if the Prefix was picked up before
.3818f9		29 80		and #$80	                AND #$80
.3818fb		c9 80		cmp #$80	                CMP #$80
.3818fd		d0 10		bne $38190f	                BNE CHK_LSHIFT          ; No: do normal scan-code checks
.3818ff		a5 87		lda $0f87	PREFIX_ON       LDA KEYBOARD_SC_FLG     ; Otherwise: clear prefix
.381901		29 7f		and #$7f	                AND #$7F
.381903		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
.381905		a5 88		lda $0f88	                LDA KEYBOARD_SC_TMP     ; Get the prefixed scan-code's character
.381907		aa		tax		                TAX
.381908		bf 80 75 39	lda $397580,x	                LDA @lScanCode_Prefix_Set1, x
.38190c		4c b2 19	jmp $3819b2	                JMP KB_WR_2_SCREEN      ; And save it
.38190f		a5 88		lda $0f88	CHK_LSHIFT      LDA KEYBOARD_SC_TMP
.381911		c9 2a		cmp #$2a	                CMP #$2A                ; Left Shift Pressed
.381913		d0 03		bne $381918	                BNE NOT_KB_SET_LSHIFT
.381915		82 ad 00	brl $3819c5	                BRL KB_SET_SHIFT
.381918						NOT_KB_SET_LSHIFT
.381918		c9 aa		cmp #$aa	                CMP #$AA                ; Left Shift Unpressed
.38191a		d0 03		bne $38191f	                BNE NOT_KB_CLR_LSHIFT
.38191c		82 af 00	brl $3819ce	                BRL KB_CLR_SHIFT
.38191f						NOT_KB_CLR_LSHIFT
.38191f		c9 36		cmp #$36	                CMP #$36                ; Right Shift Pressed
.381921		d0 03		bne $381926	                BNE NOT_KB_SET_RSHIFT
.381923		82 9f 00	brl $3819c5	                BRL KB_SET_SHIFT
.381926						NOT_KB_SET_RSHIFT
.381926		c9 b6		cmp #$b6	                CMP #$B6                ; Right Shift Unpressed
.381928		d0 03		bne $38192d	                BNE NOT_KB_CLR_RSHIFT
.38192a		82 a1 00	brl $3819ce	                BRL KB_CLR_SHIFT
.38192d						NOT_KB_CLR_RSHIFT
.38192d		c9 1d		cmp #$1d	                CMP #$1D                ; Left CTRL pressed
.38192f		d0 03		bne $381934	                BNE NOT_KB_SET_CTRL
.381931		82 a3 00	brl $3819d7	                BRL KB_SET_CTRL
.381934						NOT_KB_SET_CTRL
.381934		c9 9d		cmp #$9d	                CMP #$9D                ; Left CTRL Unpressed
.381936		d0 03		bne $38193b	                BNE NOT_KB_CLR_CTRL
.381938		82 a5 00	brl $3819e0	                BRL KB_CLR_CTRL
.38193b						NOT_KB_CLR_CTRL
.38193b		c9 38		cmp #$38	                CMP #$38                ; Left ALT Pressed
.38193d		d0 03		bne $381942	                BNE NOT_KB_SET_ALT
.38193f		82 a7 00	brl $3819e9	                BRL KB_SET_ALT
.381942						NOT_KB_SET_ALT
.381942		c9 b8		cmp #$b8	                CMP #$B8                ; Left ALT Unpressed
.381944		d0 03		bne $381949	                BNE NOT_KB_CLR_ALT
.381946		82 a9 00	brl $3819f2	                BRL KB_CLR_ALT
.381949		c9 e0		cmp #$e0	NOT_KB_CLR_ALT  CMP #$E0                ; Prefixed scan code
.38194b		d0 03		bne $381950	                BNE NOT_PREFIXED
.38194d		82 ab 00	brl $3819fb	                BRL KB_SET_PREFIX
.381950		c9 45		cmp #$45	NOT_PREFIXED    CMP #$45                ; Numlock Pressed
.381952		d0 03		bne $381957	                BNE NOT_KB_SET_NUM
.381954		82 b6 00	brl $381a0d	                BRL KB_TOG_NUMLOCK
.381957		c9 46		cmp #$46	NOT_KB_SET_NUM  CMP #$46                ; Scroll Lock Pressed
.381959		d0 03		bne $38195e	                BNE NOT_KB_SET_SCR
.38195b		82 a6 00	brl $381a04	                BRL KB_TOG_SCRLOCK
.38195e		c9 3a		cmp #$3a	NOT_KB_SET_SCR  CMP #$3A                ; Caps Lock Pressed
.381960		d0 03		bne $381965	                BNE NOT_KB_CAPSLOCK
.381962		82 bc 00	brl $381a21	                BRL KB_TOG_CAPLOCK
.381965		c9 58		cmp #$58	NOT_KB_CAPSLOCK CMP #$58                ; F12 Pressed
.381967		d0 09		bne $381972	                BNE KB_UNPRESSED
.381969		a9 60		lda #$60	                LDA #KB_CREDITS         ; Yes: flag that the CREDITS key has been pressed
.38196b		8f 8a 0f 00	sta $000f8a	                STA @lKEYFLAG
.38196f		82 b5 00	brl $381a27	                BRL KB_CHECK_B_DONE
.381972		29 80		and #$80	KB_UNPRESSED    AND #$80                ; See if the Scan Code is press or Depressed
.381974		c9 80		cmp #$80	                CMP #$80                ; Depress Status - We will not do anything at this point
.381976		d0 03		bne $38197b	                BNE KB_NORM_SC
.381978		82 ac 00	brl $381a27	                BRL KB_CHECK_B_DONE
.38197b		a5 88		lda $0f88	KB_NORM_SC      LDA KEYBOARD_SC_TMP       ;
.38197d		aa		tax		                TAX
.38197e		a5 87		lda $0f87	                LDA KEYBOARD_SC_FLG     ; Check to See if the SHIFT Key is being Pushed
.381980		29 10		and #$10	                AND #$10
.381982		c9 10		cmp #$10	                CMP #$10
.381984		f0 17		beq $38199d	                BEQ SHIFT_KEY_ON
.381986		a5 87		lda $0f87	                LDA KEYBOARD_SC_FLG     ; Check to See if the CTRL Key is being Pushed
.381988		29 20		and #$20	                AND #$20
.38198a		c9 20		cmp #$20	                CMP #$20
.38198c		f0 16		beq $3819a4	                BEQ CTRL_KEY_ON
.38198e		a5 87		lda $0f87	                LDA KEYBOARD_SC_FLG     ; Check to See if the ALT Key is being Pushed
.381990		29 40		and #$40	                AND #$40
.381992		c9 40		cmp #$40	                CMP #$40
.381994		f0 15		beq $3819ab	                BEQ ALT_KEY_ON
.381996		bf 00 73 39	lda $397300,x	                LDA @lScanCode_Press_Set1, x
.38199a		82 15 00	brl $3819b2	                BRL KB_WR_2_SCREEN
.38199d		bf 80 73 39	lda $397380,x	SHIFT_KEY_ON    LDA @lScanCode_Shift_Set1, x
.3819a1		82 0e 00	brl $3819b2	                BRL KB_WR_2_SCREEN
.3819a4		bf 00 74 39	lda $397400,x	CTRL_KEY_ON     LDA @lScanCode_Ctrl_Set1, x
.3819a8		82 07 00	brl $3819b2	                BRL KB_WR_2_SCREEN
.3819ab		bf 80 74 39	lda $397480,x	ALT_KEY_ON      LDA @lScanCode_Alt_Set1, x
.3819af		82 00 00	brl $3819b2	                BRL KB_WR_2_SCREEN
.3819b2		c9 18		cmp #$18	KB_WR_2_SCREEN  CMP #$18                ; Is it SysRq?
.3819b4		d0 03		bne $3819b9	                BNE savechar
.3819b6		4c 37 1a	jmp $381a37	                JMP programmerKey       ; Yes: trigger the programmer key
.3819b9		48		pha		savechar        PHA
.3819ba		c2 10		rep #$10	                REP #$10        ; set X long
.3819bc		20 43 1a	jsr $381a43	                JSR SAVEKEY
.3819bf		e2 20		sep #$20	                SEP #$20        ; set A short
.3819c1		68		pla		                PLA
.3819c2		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.3819c5		a5 87		lda $0f87	KB_SET_SHIFT    LDA KEYBOARD_SC_FLG
.3819c7		09 10		ora #$10	                ORA #$10
.3819c9		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
.3819cb		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.3819ce		a5 87		lda $0f87	KB_CLR_SHIFT    LDA KEYBOARD_SC_FLG
.3819d0		29 ef		and #$ef	                AND #$EF
.3819d2		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
.3819d4		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.3819d7		a5 87		lda $0f87	KB_SET_CTRL     LDA KEYBOARD_SC_FLG
.3819d9		09 20		ora #$20	                ORA #$20
.3819db		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
.3819dd		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.3819e0		a5 87		lda $0f87	KB_CLR_CTRL     LDA KEYBOARD_SC_FLG
.3819e2		29 df		and #$df	                AND #$DF
.3819e4		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
.3819e6		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.3819e9		a5 87		lda $0f87	KB_SET_ALT      LDA KEYBOARD_SC_FLG
.3819eb		09 40		ora #$40	                ORA #$40
.3819ed		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
.3819ef		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.3819f2		a5 87		lda $0f87	KB_CLR_ALT      LDA KEYBOARD_SC_FLG
.3819f4		29 bf		and #$bf	                AND #$BF
.3819f6		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
.3819f8		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.3819fb		a5 87		lda $0f87	KB_SET_PREFIX   LDA KEYBOARD_SC_FLG
.3819fd		09 80		ora #$80	                ORA #$80
.3819ff		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
.381a01		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.381a04		a5 89		lda $0f89	KB_TOG_SCRLOCK  LDA KEYBOARD_LOCKS
.381a06		49 01		eor #$01	                EOR #KB_SCROLL_LOCK         ; toggle the Scroll Lock flag
.381a08		85 89		sta $0f89	                STA KEYBOARD_LOCKS
.381a0a		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.381a0d		a5 87		lda $0f87	KB_TOG_NUMLOCK  LDA KEYBOARD_SC_FLG         ; Check flags...
.381a0f		29 60		and #$60	                AND #$60                    ; ... is control-alt pressed?
.381a11		c9 60		cmp #$60	                CMP #$60
.381a13		d0 03		bne $381a18	                BNE KB_TOG_NUMLOC2
.381a15		82 63 ff	brl $38197b	                BRL KB_NORM_SC              ; No: treat as a BREAK key
.381a18		a5 89		lda $0f89	KB_TOG_NUMLOC2  LDA KEYBOARD_LOCKS
.381a1a		49 02		eor #$02	                EOR #KB_NUM_LOCK            ; toggle the Num Lock flag
.381a1c		85 89		sta $0f89	                STA KEYBOARD_LOCKS
.381a1e		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
.381a21		a5 89		lda $0f89	KB_TOG_CAPLOCK  LDA KEYBOARD_LOCKS
.381a23		49 04		eor #$04	                EOR #KB_CAPS_LOCK           ; toggle the Caps Lock flag
.381a25		85 89		sta $0f89	                STA KEYBOARD_LOCKS
.381a27						KB_CHECK_B_DONE
.381a27		af 64 10 af	lda $af1064	                LDA STATUS_PORT
.381a2b		29 01		and #$01	                AND #OUT_BUF_FULL           ; Test bit $01 (if 1, Full)
.381a2d		c9 01		cmp #$01	                CMP #OUT_BUF_FULL           ; if Still Byte in the Buffer, fetch it out
.381a2f		d0 03		bne $381a34	                BNE SET_LED
.381a31		4c f1 18	jmp $3818f1	                JMP IRQ_HANDLER_FETCH
.381a34						SET_LED
.381a34						KB_DONE
.381a34		c2 30		rep #$30	                REP #$30        ; set A&X long
.381a36		60		rts		                RTS
.381a37						programmerKey
.381a37		c2 30		rep #$30	                REP #$30        ; set A&X long
.381a39		68		pla		                PLA                     ; Get and throw-away the return address to the interrupt handler
.381a3a		2b		pld		                PLD                     ; Restore the registers that were present when the handler was invoked
.381a3b		ab		plb		                PLB
.381a3c		7a		ply		                PLY
.381a3d		fa		plx		                PLX
.381a3e		68		pla		                PLA
.381a3f		5c 08 10 00	jmp $001008	                JML BREAK               ; And go to the BRK handler directly to open the monitor
.381a43						SAVEKEY
.381a43		e2 20		sep #$20	                SEP #$20        ; set A short
.381a45		48		pha		                PHA                     ; Save the character
.381a46		a5 89		lda $0f89	                LDA KEYBOARD_LOCKS      ; Check the keyboard lock flags
.381a48		29 04		and #$04	                AND #KB_CAPS_LOCK       ; Is CAPS lock on?
.381a4a		f0 0d		beq $381a59	                BEQ no_caps             ; No... just use the character as-is
.381a4c		68		pla		                PLA                     ; Get the character back
.381a4d		c9 61		cmp #$61	                CMP #'a'                ; Is it < 'a'
.381a4f		90 09		bcc $381a5a	                BLT check_break         ; Yes: just use as-is
.381a51		c9 7b		cmp #$7b	                CMP #'z'+1              ; Is it > 'z'
.381a53		b0 05		bcs $381a5a	                BGE check_break         ; Yes: just us as-is
.381a55		29 df		and #$df	                AND #%11011111          ; Conver to upper case
.381a57		80 01		bra $381a5a	                BRA check_break
.381a59		68		pla		no_caps         PLA                     ; Restore the character
.381a5a		c9 00		cmp #$00	check_break     CMP #0
.381a5c		f0 18		beq $381a76	                BEQ done
.381a5e		c9 03		cmp #$03	                CMP #CHAR_CTRL_C        ; Is it CTRL-C?
.381a60		f0 15		beq $381a77	                BEQ flag_break          ; Yes: flag a break
.381a62		a6 8d		ldx $0f8d	no_break        LDX KEY_BUFFER_WPOS     ; So the Receive Character is saved in the Buffer
.381a64		e0 80 00	cpx #$0080	                CPX #KEY_BUFFER_SIZE    ; Make sure we haven't been overboard.
.381a67		b0 0d		bcs $381a76	                BCS done                ; Stop storing - An error should ensue here...
.381a69		9f 00 0f 00	sta $000f00,x	                STA @lKEY_BUFFER,X
.381a6d		e8		inx		                INX
.381a6e		86 8d		stx $0f8d	                STX KEY_BUFFER_WPOS
.381a70		a9 00		lda #$00	                LDA #$00
.381a72		9f 00 0f 00	sta $000f00,x	                STA @lKEY_BUFFER, X       ; Store a EOL in the following location for good measure
.381a76		60		rts		done            RTS
.381a77						flag_break
.381a77		e2 20		sep #$20	                SEP #$20        ; set A short
.381a79		a9 80		lda #$80	                LDA #KB_CTRL_C          ; Flag that an interrupt key has been pressed
.381a7b		85 8a		sta $0f8a	                STA KEYFLAG             ; The interpreter should see this soon and throw a BREAK
.381a7d		60		rts		                RTS
.381a7e						KBD_GETC
.381a7e		da		phx		                PHX
.381a7f		0b		phd		                PHD
.381a80		08		php		                PHP
.381a81		48		pha		                PHA             ; begin setdp macro
.381a82		08		php		                PHP
.381a83		c2 20		rep #$20	                REP #$20        ; set A long
.381a85		a9 00 0f	lda #$0f00	                LDA #KEY_BUFFER         ; set DP to page 0
.381a88		5b		tcd		                TCD
.381a89		28		plp		                PLP
.381a8a		68		pla		                PLA             ; end setdp macro
.381a8b		e2 20		sep #$20	                SEP #$20        ; set A short
.381a8d		c2 10		rep #$10	                REP #$10        ; set X long
.381a8f		58		cli		                CLI                     ; Make sure interrupts can happen
.381a90		af 8a 0f 00	lda $000f8a	get_wait        LDA @lKEYFLAG           ; Check the keyboard control flag
.381a94		29 60		and #$60	                AND #KB_CREDITS         ; Are the credits flagged?
.381a96		c9 60		cmp #$60	                CMP #KB_CREDITS
.381a98		d0 0a		bne $381aa4	                BNE check_buffer        ; No: check the key buffer
.381a9a		a9 00		lda #$00	                LDA #0                  ; Yes: clear the flags
.381a9c		8f 8a 0f 00	sta $000f8a	                STA @lKEYFLAG
.381aa0		22 8b 16 39	jsl $39168b	                JSL SHOW_CREDITS        ; Then show the credits screen and wait for a key press
.381aa4		a6 8b		ldx $0f8b	check_buffer    LDX KEY_BUFFER_RPOS     ; Is KEY_BUFFER_RPOS < KEY_BUFFER_WPOS
.381aa6		e4 8d		cpx $0f8d	                CPX KEY_BUFFER_WPOS
.381aa8		90 02		bcc $381aac	                BCC read_buff           ; Yes: a key is present, read it
.381aaa		80 e4		bra $381a90	                BRA get_wait            ; Otherwise, keep waiting
.381aac		78		sei		read_buff       SEI                     ; Don't interrupt me!
.381aad		b5 00		lda $0f00,x	                LDA KEY_BUFFER,X        ; Get the key
.381aaf		e8		inx		                INX                     ; And move to the next key
.381ab0		e4 8d		cpx $0f8d	                CPX KEY_BUFFER_WPOS     ; Did we just read the last key?
.381ab2		f0 07		beq $381abb	                BEQ reset_indexes       ; Yes: return to 0 position
.381ab4		86 8b		stx $0f8b	                STX KEY_BUFFER_RPOS     ; Otherwise: Update the read index
.381ab6		58		cli		                CLI
.381ab7		28		plp		done            PLP                     ; Restore status and interrupts
.381ab8		2b		pld		                PLD
.381ab9		fa		plx		                PLX
.381aba		6b		rtl		                RTL
.381abb		64 8b		stz $0f8b	reset_indexes   STZ KEY_BUFFER_RPOS     ; Reset read index to the beginning
.381abd		64 8d		stz $0f8d	                STZ KEY_BUFFER_WPOS     ; Reset the write index to the beginning
.381abf		80 f6		bra $381ab7	                BRA done

;******  Return to file: src\kernel.asm

.390400						IBOOT
.390400		18		clc		                CLC               ; clear the carry flag
.390401		fb		xce		                XCE               ; move carry to emulation flag.
.390402		78		sei		                SEI               ; Disable interrupts
.390403		c2 30		rep #$30	                REP #$30        ; set A&X long
.390405		a9 ff fe	lda #$feff	                LDA #STACK_END    ; initialize stack pointer
.390408		1b		tcs		                TAS
.390409		a2 00 10	ldx #$1000	                LDX #<>BOOT       ; Copy the kernel jump table to bank 0
.39040c		a0 00 10	ldy #$1000	                LDY #<>BOOT       ; Ordinarily, this is done by GAVIN, but
.39040f		a9 00 20	lda #$2000	                LDA #$2000        ; this is ensures it can be reloaded in case of errors
.390412		54 00 38	mvn $38,$00	                MVN $38,$00       ; Or during soft loading of the kernel from the debug port
.390415		48		pha		                PHA             ; begin setdp macro
.390416		08		php		                PHP
.390417		c2 20		rep #$20	                REP #$20        ; set A long
.390419		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.39041c		5b		tcd		                TCD
.39041d		28		plp		                PLP
.39041e		68		pla		                PLA             ; end setdp macro
.39041f		e2 20		sep #$20	                SEP #$20        ; set A short
.390421		a2 00 00	ldx #$0000	                LDX #$0000
.390424		a9 00		lda #$00	                LDA #$00
.390426						CLEAR_MEM_LOOP
.390426		95 00		sta $00,x	                STA $0000, X
.390428		e8		inx		                INX
.390429		e0 00 01	cpx #$0100	                CPX #$0100
.39042c		d0 f8		bne $390426	                BNE CLEAR_MEM_LOOP
.39042e		ea		nop		                NOP
.39042f		a9 ff		lda #$ff	                LDA #$FF
.390431		8f 48 01 00	sta $000148	                STA @lINT_EDGE_REG0
.390435		8f 49 01 00	sta $000149	                STA @lINT_EDGE_REG1
.390439		8f 4a 01 00	sta $00014a	                STA @lINT_EDGE_REG2
.39043d		8f 4b 01 00	sta $00014b	                STA @lINT_EDGE_REG3
.390441		8f 4c 01 00	sta $00014c	                STA @lINT_MASK_REG0
.390445		8f 4d 01 00	sta $00014d	                STA @lINT_MASK_REG1
.390449		8f 4e 01 00	sta $00014e	                STA @lINT_MASK_REG2
.39044d		8f 4f 01 00	sta $00014f	                STA @lINT_MASK_REG3
.390451		22 48 12 39	jsl $391248	                JSL INITRTC               ; Initialize the RTC
.390455		c2 30		rep #$30	                REP #$30        ; set A&X long
.390457		a9 00 a0	lda #$a000	                LDA #<>SCREEN_PAGE0      ; store the initial screen buffer location
.39045a		85 0c		sta $0c		                STA SCREENBEGIN
.39045c		85 17		sta $17		                STA CURSORPOS
.39045e		a9 00 c0	lda #$c000	                LDA #<>CS_COLOR_MEM_PTR   ; Set the initial COLOR cursor position
.390461		85 1f		sta $1f		                STA COLORPOS
.390463		e2 20		sep #$20	                SEP #$20        ; set A short
.390465		a9 af		lda #$af	                LDA #`SCREEN_PAGE0
.390467		85 0e		sta $0e		                STA SCREENBEGIN+2
.390469		85 19		sta $19		                STA CURSORPOS+2
.39046b		a9 af		lda #$af	                LDA #`CS_COLOR_MEM_PTR    ; Set the initial COLOR cursor position
.39046d		85 21		sta $21		                STA COLORPOS+2
.39046f		e2 20		sep #$20	                SEP #$20        ; set A short
.390471		a9 00		lda #$00	                LDA #$00
.390473		8d 87 0f	sta $0f87	                STA KEYBOARD_SC_FLG     ; Clear the Keyboard Flag
.390476		a9 9f		lda #$9f	                LDA #$9F ; Channel Two - No Atteniation
.390478		8f 00 f1 af	sta $aff100	                STA $AFF100
.39047c		a9 bf		lda #$bf	                LDA #$BF ; Channel Two - No Atteniation
.39047e		8f 00 f1 af	sta $aff100	                STA $AFF100
.390482		a9 df		lda #$df	                LDA #$DF ; Channel Two - No Atteniation
.390484		8f 00 f1 af	sta $aff100	                STA $AFF100
.390488		a9 ff		lda #$ff	                LDA #$FF ; Channel Two - No Atteniation
.39048a		8f 00 f1 af	sta $aff100	                STA $AFF100
.39048e		c2 30		rep #$30	                REP #$30        ; set A&X long
.390490		a2 48 00	ldx #$0048	                LDX #72
.390493		86 0f		stx $0f		                STX COLS_VISIBLE
.390495		a0 34 00	ldy #$0034	                LDY #52
.390498		84 13		sty $13		                STY LINES_VISIBLE
.39049a		a2 80 00	ldx #$0080	                LDX #128
.39049d		86 11		stx $11		                STX COLS_PER_LINE
.39049f		a0 40 00	ldy #$0040	                LDY #64
.3904a2		84 15		sty $15		                STY LINES_MAX
.3904a4		a9 ed 00	lda #$00ed	                LDA #$ED                  ; Set the default text color to light gray on dark gray
.3904a7		85 1e		sta $1e		                STA CURCOLOR
.3904a9		22 dc 10 00	jsl $0010dc	                JSL INITCODEC
.3904ad		22 b0 10 00	jsl $0010b0	                JSL INITSUPERIO
.3904b1		22 c4 10 00	jsl $0010c4	                JSL INITGAMMATABLE
.3904b5		22 c8 10 00	jsl $0010c8	                JSL INITALLLUT
.3904b9		22 ac 10 00	jsl $0010ac	                JSL INITCHLUT
.3904bd		22 b9 0f 39	jsl $390fb9	                JSL INITMOUSEPOINTER
.3904c1		22 bc 10 00	jsl $0010bc	                JSL INITCURSOR
.3904c5		22 cc 10 00	jsl $0010cc	                JSL INITVKYTXTMODE
.3904c9		22 a0 0f 39	jsl $390fa0	                JSL IINITFONTSET
.3904cd		22 42 0b 39	jsl $390b42	                JSL ICLRSCREEN  ; Clear Screen and Set a standard color in Color Memory
.3904d1		a9 01 00	lda #$0001	                LDA #CHAN_COM1    ; Initialize COM1
.3904d4		22 d2 5b 39	jsl $395bd2	                JSL UART_SELECT
.3904d8		22 3e 5c 39	jsl $395c3e	                JSL UART_INIT
.3904dc		a9 02 00	lda #$0002	                LDA #CHAN_COM2    ; Initialize COM2
.3904df		22 d2 5b 39	jsl $395bd2	                JSL UART_SELECT
.3904e3		22 3e 5c 39	jsl $395c3e	                JSL UART_INIT
.3904e7		a9 00 00	lda #$0000	                LDA #0
.3904ea		22 38 10 00	jsl $001038	                JSL SETIN
.3904ee		22 3c 10 00	jsl $00103c	                JSL SETOUT
.3904f2		c2 20		rep #$20	                REP #$20        ; set A long
.3904f4		a2 00 00	ldx #$0000	                LDX #0
.3904f7		a0 00 00	ldy #$0000	                LDY #0
.3904fa		22 1b 0a 39	jsl $390a1b	                JSL ILOCATE
.3904fe		c2 30		rep #$30	                REP #$30        ; set A&X long
.390500						greet
.390500		48		pha		                PHA             ; begin setdbr macro
.390501		08		php		                PHP
.390502		e2 20		sep #$20	                SEP #$20        ; set A short
.390504		a9 39		lda #$39	                LDA #`greet_msg
.390506		48		pha		                PHA
.390507		ab		plb		                PLB
.390508		28		plp		                PLP
.390509		68		pla		                PLA             ; end setdbr macro
.39050a		a2 13 6e	ldx #$6e13	                LDX #<>greet_msg
.39050d		22 7e 07 39	jsl $39077e	                JSL IPRINT       ; print the first line
.390511		22 8d 0b 39	jsl $390b8d	                JSL ICOLORFLAG  ; This is to set the Color Memory for the Logo
.390515		48		pha		                PHA             ; begin setdp macro
.390516		08		php		                PHP
.390517		c2 20		rep #$20	                REP #$20        ; set A long
.390519		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.39051c		5b		tcd		                TCD
.39051d		28		plp		                PLP
.39051e		68		pla		                PLA             ; end setdp macro
.39051f		22 b4 10 00	jsl $0010b4	                JSL INITKEYBOARD ;
.390523		e2 20		sep #$20	                SEP #$20        ; set A short
.390525		c2 10		rep #$10	                REP #$10        ; set X long
.390527		a9 9f		lda #$9f	                LDA #$9F ; Channel Two - No Atteniation
.390529		8f 00 f1 af	sta $aff100	                STA $AFF100
.39052d		a9 bf		lda #$bf	                LDA #$BF ; Channel Two - No Atteniation
.39052f		8f 00 f1 af	sta $aff100	                STA $AFF100
.390533		a9 df		lda #$df	                LDA #$DF ; Channel Two - No Atteniation
.390535		8f 00 f1 af	sta $aff100	                STA $AFF100
.390539		a9 ff		lda #$ff	                LDA #$FF ; Channel Two - No Atteniation
.39053b		8f 00 f1 af	sta $aff100	                STA $AFF100
.39053f		a9 83		lda #$83	                LDA #$83 ; Channel Zero - No Atteniation
.390541		8f 00 f1 af	sta $aff100	                STA $AFF100
.390545		a9 12		lda #$12	                LDA #$12 ; Channel Zero - No Atteniation
.390547		8f 00 f1 af	sta $aff100	                STA $AFF100
.39054b		a9 90		lda #$90	                LDA #$90 ; Channel One - No Atteniation
.39054d		8f 00 f1 af	sta $aff100	                STA $AFF100
.390551		a2 00 40	ldx #$4000	                LDX #16384      ; 400ms
.390554		22 19 16 39	jsl $391619	          		 	JSL ILOOP_MS
.390558		a9 9f		lda #$9f	                LDA #$9F ; Channel Two - No Atteniation
.39055a		8f 00 f1 af	sta $aff100	                STA $AFF100
.39055e		58		cli		                CLI                   ; Make sure no Interrupt will come and fuck up Init before this point.
.39055f		e2 20		sep #$20	                SEP #$20        ; set A short
.390561		c2 10		rep #$10	                REP #$10        ; set X long
.390563		48		pha		                PHA             ; begin setdbr macro
.390564		08		php		                PHP
.390565		e2 20		sep #$20	                SEP #$20        ; set A short
.390567		a9 39		lda #$39	                LDA #`greet_msg
.390569		48		pha		                PHA
.39056a		ab		plb		                PLB
.39056b		28		plp		                PLP
.39056c		68		pla		                PLA             ; end setdbr macro
.39056d		a2 00 00	ldx #$0000	                LDX #0
.390570		bf 00 10 00	lda $001000,x	jmpcopy         LDA @l BOOT,X
.390574		9f 00 10 00	sta $001000,x	                STA @l $001000,X
.390578		e8		inx		                INX
.390579		e0 00 10	cpx #$1000	                CPX #$1000
.39057c		d0 f2		bne $390570	                BNE jmpcopy
.39057e		22 82 44 39	jsl $394482	retry_boot      JSL DOS_INIT          ; Initialize the "disc operating system"
.390582		22 2c 06 39	jsl $39062c	                JSL BOOT_MENU         ; Show the splash screen / boot menu and wait for key presses
.390586		c9 20		cmp #$20	                CMP #CHAR_SP          ; Did the user press SPACE?
.390588		f0 10		beq $39059a	                BEQ BOOT_DIP          ; Yes: boot via the DIP switches
.39058a		c9 0d		cmp #$0d	                CMP #CHAR_CR          ; Did the user press RETURN?
.39058c		f0 1e		beq $3905ac	                BEQ BOOTBASIC         ; Yes: go straight to BASIC
.39058e		c9 81		cmp #$81	                CMP #CHAR_F1          ; Did the user press F1?
.390590		f0 54		beq $3905e6	                BEQ BOOTFLOPPY        ; Yes: boot via the floppy
.390592		c9 82		cmp #$82	                CMP #CHAR_F2          ; Did the user press F2?
.390594		f0 1d		beq $3905b3	                BEQ BOOTSDC           ; Yes: boot via the SDC
.390596		c9 83		cmp #$83	                CMP #CHAR_F3          ; Did the user press F3?
.390598		f0 32		beq $3905cc	                BEQ BOOTIDE           ; Yes: boot via the IDE
.39059a		af 0e e8 af	lda $afe80e	BOOT_DIP        LDA @lDIP_BOOTMODE    ; {HD_INSTALLED, 5'b0_0000, BOOT_MODE[1], BOOT_MODE[0]}
.39059e		29 03		and #$03	                AND #%00000011        ; Look at the mode bits
.3905a0		c9 00		cmp #$00	                CMP #DIP_BOOT_IDE     ; DIP set for IDE?
.3905a2		f0 28		beq $3905cc	                BEQ BOOTIDE           ; Yes: Boot from the IDE
.3905a4		c9 01		cmp #$01	                CMP #DIP_BOOT_SDCARD  ; DIP set for SD card?
.3905a6		f0 0b		beq $3905b3	                BEQ BOOTSDC           ; Yes: try to boot from the SD card
.3905a8		c9 02		cmp #$02	                CMP #DIP_BOOT_FLOPPY  ; DIP set for floppy?
.3905aa		f0 3a		beq $3905e6	                BEQ BOOTFLOPPY        ; Yes: try to boot from the floppy
.3905ac						IRESTORE
.3905ac		5c 00 00 3a	jmp $3a0000	BOOTBASIC       JML BASIC             ; Cold start of the BASIC interpreter (or its replacement)
.3905b0		ea		nop		CREDIT_LOCK     NOP
.3905b1		80 fd		bra $3905b0	                BRA CREDIT_LOCK
.3905b3						BOOTSDC
.3905b3		e2 20		sep #$20	                SEP #$20        ; set A short
.3905b5		a9 02		lda #$02	                LDA #BIOS_DEV_SD
.3905b7		8f 21 03 00	sta $000321	                STA @l BIOS_DEV
.3905bb		22 54 45 39	jsl $394554	                JSL DOS_MOUNT         ; Mount the SDC
.3905bf		90 06		bcc $3905c7	                BCC sdc_error         ; Print an error message if couldn't get anything
.3905c1		22 0f 47 39	jsl $39470f	                JSL DOS_TESTBOOT      ; Try to boot from the SDC's MBR
.3905c5		80 e5		bra $3905ac	                BRA BOOTBASIC         ; If we couldn't fall, into BASIC
.3905c7		a2 f1 71	ldx #$71f1	sdc_error       LDX #<>sdc_err_boot   ; Print a message saying SD card booting is not implemented
.3905ca		80 39		bra $390605	                BRA PR_BOOT_ERROR
.3905cc						BOOTIDE
.3905cc		e2 20		sep #$20	                SEP #$20        ; set A short
.3905ce		a9 06		lda #$06	                LDA #BIOS_DEV_HD0
.3905d0		8f 21 03 00	sta $000321	                STA @l BIOS_DEV
.3905d4		22 54 45 39	jsl $394554	                JSL DOS_MOUNT         ; Mount the IDE drive
.3905d8		90 07		bcc $3905e1	                BCC hdc_error         ; Print an error message if couldn't get anything
.3905da		22 0f 47 39	jsl $39470f	                JSL DOS_TESTBOOT      ; Try to boot from the IDE's MBR
.3905de		82 cb ff	brl $3905ac	                BRL BOOTBASIC         ; If we couldn't fall, into BASIC
.3905e1		a2 0d 72	ldx #$720d	hdc_error       LDX #<>ide_err_boot   ; Print a message saying SD card booting is not implemented
.3905e4		80 1f		bra $390605	                BRA PR_BOOT_ERROR
.3905e6		a2 56 72	ldx #$7256	BOOTFLOPPY      LDX #<>fdc_boot
.3905e9		22 7e 07 39	jsl $39077e	                JSL IPRINT
.3905ed		e2 20		sep #$20	                SEP #$20        ; set A short
.3905ef		a9 00		lda #$00	                LDA #BIOS_DEV_FDC
.3905f1		8f 21 03 00	sta $000321	                STA @l BIOS_DEV
.3905f5		22 ac 67 39	jsl $3967ac	                JSL FDC_MOUNT         ; Mount the floppy drive
.3905f9		90 07		bcc $390602	                BCC fdc_error         ; Print an error message if couldn't get anything
.3905fb		22 0f 47 39	jsl $39470f	                JSL DOS_TESTBOOT      ; Try to boot from the FDC's MBR
.3905ff		82 aa ff	brl $3905ac	                BRL BOOTBASIC         ; If we couldn't, fall into BASIC
.390602		a2 30 72	ldx #$7230	fdc_error       LDX #<>fdc_err_boot   ; Print a message saying SD card booting is not implemented
.390605		22 7e 07 39	jsl $39077e	PR_BOOT_ERROR   JSL IPRINT            ; Print the error message in X
.390609		a2 cc 71	ldx #$71cc	                LDX #<>boot_retry     ; Print the boot retry prompt
.39060c		22 7e 07 39	jsl $39077e	                JSL IPRINT
.390610		22 21 07 39	jsl $390721	boot_wait_key   JSL IGETCHW           ; Wait for a keypress
.390614		c9 52		cmp #$52	                CMP #'R'              ; Was "R" pressed?
.390616		d0 03		bne $39061b	                BNE chk_r_lc
.390618		82 63 ff	brl $39057e	                BRL retry_boot        ; Yes: retry the boot sequence
.39061b		c9 72		cmp #$72	chk_r_lc        CMP #'r'
.39061d		d0 03		bne $390622	                BNE chk_b_lc
.39061f		82 5c ff	brl $39057e	                BRL retry_boot
.390622		c9 62		cmp #$62	chk_b_lc        CMP #'b'              ; Was "B" pressed?
.390624		f0 86		beq $3905ac	                BEQ BOOTBASIC         ; Yes: try going to BASIC
.390626		c9 42		cmp #$42	                CMP #'B'
.390628		f0 82		beq $3905ac	                BEQ BOOTBASIC
.39062a		80 e4		bra $390610	                BRA boot_wait_key     ; No: keep waiting
.39062c						BOOT_MENU
.39062c		8b		phb		                PHB
.39062d		08		php		                PHP
.39062e		e2 20		sep #$20	                SEP #$20        ; set A short
.390630		c2 10		rep #$10	                REP #$10        ; set X long
.390632		a9 39		lda #$39	                LDA #`bootmenu          ; Point DBR:X to the boot menu
.390634		48		pha		                PHA
.390635		ab		plb		                PLB
.390636		a2 6f 06	ldx #$066f	                LDX #<>bootmenu
.390639		22 1c 10 00	jsl $00101c	                JSL PUTS                ; Display the boot menu
.39063d		c2 10		rep #$10	                REP #$10        ; set X long
.39063f		a0 e8 03	ldy #$03e8	                LDY #1000               ; Number of cycles we'll wait... total wait time is about 30s (ish)
.390642		e2 20		sep #$20	                SEP #$20        ; set A short
.390644		a2 e8 03	ldx #$03e8	wait_key        LDX #1000
.390647		22 19 16 39	jsl $391619	                JSL ILOOP_MS            ; Wait ...
.39064b		88		dey		                DEY                     ; Count down the tenths of seconds
.39064c		f0 1c		beq $39066a	                BEQ timeout             ; If we've got to 0, we're done
.39064e		22 48 10 00	jsl $001048	                JSL GETCH               ; Try to get a character
.390652		c9 00		cmp #$00	                CMP #0                  ; Did we get anything
.390654		f0 ee		beq $390644	                BEQ wait_key            ; No: keep waiting until timeout
.390656		c9 81		cmp #$81	                CMP #CHAR_F1            ; Did the user press F1?
.390658		f0 12		beq $39066c	                BEQ return              ; Yes: return it
.39065a		c9 82		cmp #$82	                CMP #CHAR_F2            ; Did the user press F2?
.39065c		f0 0e		beq $39066c	                BEQ return              ; Yes: return it
.39065e		c9 83		cmp #$83	                CMP #CHAR_F3            ; Did the user press F3?
.390660		f0 0a		beq $39066c	                BEQ return              ; Yes: return it
.390662		c9 0d		cmp #$0d	                CMP #CHAR_CR            ; Did the user press CR?
.390664		f0 06		beq $39066c	                BEQ return              ; Yes: return it
.390666		c9 20		cmp #$20	                CMP #CHAR_SP            ; Did the user press SPACE?
.390668		d0 da		bne $390644	                BNE wait_key            ; No: keep waiting
.39066a		a9 00		lda #$00	timeout         LDA #0                  ; Return 0 for a timeout / SPACE
.39066c		28		plp		return          PLP
.39066d		ab		plb		                PLB
.39066e		6b		rtl		                RTL
>39066f		46 31 3d 46 44 43 2c 20		bootmenu        .null "F1=FDC, F2=SDC, F3=IDE, RETURN=BASIC, SPACE=DEFAULT", CHAR_CR
>390677		46 32 3d 53 44 43 2c 20 46 33 3d 49 44 45 2c 20
>390687		52 45 54 55 52 4e 3d 42 41 53 49 43 2c 20 53 50
>390697		41 43 45 3d 44 45 46 41 55 4c 54 0d 00
.3906a4						IBREAK
.3906a4		48		pha		                PHA             ; begin setdp macro
.3906a5		08		php		                PHP
.3906a6		c2 20		rep #$20	                REP #$20        ; set A long
.3906a8		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.3906ab		5b		tcd		                TCD
.3906ac		28		plp		                PLP
.3906ad		68		pla		                PLA             ; end setdp macro
.3906ae		68		pla		                PLA             ; Pull .Y and stuff it in the CPUY variable
.3906af		8f 48 02 00	sta $000248	                STA CPUY
.3906b3		68		pla		                PLA             ; Pull .X and stuff it in the CPUY variable
.3906b4		8f 46 02 00	sta $000246	                STA CPUX
.3906b8		68		pla		                PLA             ; Pull .A and stuff it in the CPUY variable
.3906b9		8f 44 02 00	sta $000244	                STA CPUA
.3906bd		68		pla		                PLA
.3906be		8f 4c 02 00	sta $00024c	                STA CPUDP       ; Pull Direct page
.3906c2		e2 20		sep #$20	                SEP #$20        ; set A short
.3906c4		68		pla		                PLA             ; Pull Data Bank (8 bits)
.3906c5		8f 4e 02 00	sta $00024e	                STA CPUDBR
.3906c9		68		pla		                PLA             ; Pull Flags (8 bits)
.3906ca		8f 4f 02 00	sta $00024f	                STA CPUFLAGS
.3906ce		c2 20		rep #$20	                REP #$20        ; set A long
.3906d0		68		pla		                PLA             ; Pull Program Counter (16 bits)
.3906d1		8f 40 02 00	sta $000240	                STA CPUPC
.3906d5		e2 20		sep #$20	                SEP #$20        ; set A short
.3906d7		68		pla		                PLA             ; Pull Program Bank (8 bits)
.3906d8		8f 42 02 00	sta $000242	                STA CPUPBR
.3906dc		c2 20		rep #$20	                REP #$20        ; set A long
.3906de		3b		tsc		                TSA             ; Get the stack
.3906df		8f 4a 02 00	sta $00024a	                STA CPUSTACK    ; Store the stack at immediately before the interrupt was asserted
.3906e3		a9 ff fe	lda #$feff	                LDA #<>STACK_END   ; initialize stack pointer back to the bootup value
.3906e6		1b		tcs		                TAS
.3906e7		5c 04 00 3a	jmp $3a0004	                JML MONITOR
.3906eb						IREADY
.3906eb		48		pha		                PHA             ; begin setdbr macro
.3906ec		08		php		                PHP
.3906ed		e2 20		sep #$20	                SEP #$20        ; set A short
.3906ef		a9 39		lda #$39	                LDA #`ready_msg
.3906f1		48		pha		                PHA
.3906f2		ab		plb		                PLB
.3906f3		28		plp		                PLP
.3906f4		68		pla		                PLA             ; end setdbr macro
.3906f5		e2 20		sep #$20	                SEP #$20        ; set A short
.3906f7		a2 6d 72	ldx #$726d	                LDX #<>ready_msg
.3906fa		22 7e 07 39	jsl $39077e	                JSL IPRINT
.3906fe						IREADYWAIT
.3906fe		22 18 07 39	jsl $390718	                JSL IGETCHE
.390702		80 fa		bra $3906fe	                BRA IREADYWAIT
.390704		db		stp		IKEYDOWN        STP             ; Keyboard key pressed
.390705		db		stp		IRETURN         STP
.390706		08		php		ISETIN          PHP
.390707		e2 20		sep #$20	                SEP #$20        ; set A short
.390709		8f 04 07 00	sta $000704	                STA @lCHAN_IN   ; Save the channel number
.39070d		28		plp		                PLP
.39070e		6b		rtl		                RTL
.39070f		08		php		ISETOUT         PHP
.390710		e2 20		sep #$20	                SEP #$20        ; set A short
.390712		8f 03 07 00	sta $000703	                STA @lCHAN_OUT  ; Save the channel number
.390716		28		plp		                PLP
.390717		6b		rtl		                RTL
.390718		22 21 07 39	jsl $390721	IGETCHE         JSL IGETCHW
.39071c		22 9e 07 39	jsl $39079e	                JSL IPUTC
.390720		6b		rtl		                RTL
.390721						IGETCHW
.390721		08		php		                PHP
.390722		e2 20		sep #$20	                SEP #$20        ; set A short
.390724		af 04 07 00	lda $000704	                LDA @lCHAN_IN       ; Get the current input channel
.390728		f0 17		beq $390741	                BEQ getc_keyboard   ; If it's keyboard, read from the key buffer
.39072a		c9 01		cmp #$01	                CMP #CHAN_COM1      ; Check to see if it's the COM1 port
.39072c		f0 09		beq $390737	                BEQ getc_uart       ; Yes: handle reading from the UART
.39072e		c9 02		cmp #$02	                CMP #CHAN_COM2      ; Check to see if it's the COM2 port
.390730		f0 05		beq $390737	                BEQ getc_uart       ; Yes: handle reading from the UART
.390732		a9 00		lda #$00	                LDA #0              ; Return 0 if no valid device
.390734		28		plp		                PLP
.390735		38		sec		                SEC                 ; And return carry set
.390736		6b		rtl		                RTL
.390737		22 d2 5b 39	jsl $395bd2	getc_uart       JSL UART_SELECT     ; Select the correct COM port
.39073b		22 86 5c 39	jsl $395c86	                JSL UART_GETC       ; Get the charater from the COM port
.39073f		80 04		bra $390745	                BRA done
.390741		22 7e 1a 38	jsl $381a7e	getc_keyboard   JSL KBD_GETC        ; Get the character from the keyboard
.390745		28		plp		done            PLP
.390746		18		clc		                CLC                 ; Return carry clear for valid data
.390747		6b		rtl		                RTL
.390748						IGETCH
.390748		da		phx		                PHX
.390749		5a		phy		                PHY
.39074a		8b		phb		                PHB
.39074b		0b		phd		                PHD
.39074c		08		php		                PHP
.39074d		48		pha		                PHA             ; begin setdbr macro
.39074e		08		php		                PHP
.39074f		e2 20		sep #$20	                SEP #$20        ; set A short
.390751		a9 00		lda #$00	                LDA #0
.390753		48		pha		                PHA
.390754		ab		plb		                PLB
.390755		28		plp		                PLP
.390756		68		pla		                PLA             ; end setdbr macro
.390757		e2 20		sep #$20	                SEP #$20        ; set A short
.390759		ad 04 07	lda $0704	                LDA @w CHAN_IN          ; Check the channel
.39075c		c9 00		cmp #$00	                CMP #CHAN_CONSOLE       ; Is it the console
.39075e		f0 03		beq $390763	                BEQ getch_console       ; Yes: dispatch on the console
.390760		82 10 00	brl $390773	                BRL ret_nothing         ; Unhandled device: return 0
.390763						getch_console
.390763		c2 20		rep #$20	                REP #$20        ; set A long
.390765		ad 8b 0f	lda $0f8b	                LDA @w KEY_BUFFER_RPOS  ; Is KEY_BUFFER_RPOS < KEY_BUFFER_WPOS
.390768		cd 8d 0f	cmp $0f8d	                CMP @w KEY_BUFFER_WPOS
.39076b		b0 06		bcs $390773	                BCS ret_nothing         ; No: there's nothing ready yet... return 0
.39076d		22 4c 10 00	jsl $00104c	                JSL GETCHW              ; Otherwise: retrieve the character
.390771		80 05		bra $390778	                BRA done                ; And return it
.390773						ret_nothing
.390773		c2 20		rep #$20	                REP #$20        ; set A long
.390775		a9 00 00	lda #$0000	                LDA #0                  ; Return 0 for no key
.390778		28		plp		done            PLP
.390779		2b		pld		                PLD
.39077a		ab		plb		                PLB
.39077b		7a		ply		                PLY
.39077c		fa		plx		                PLX
.39077d		6b		rtl		                RTL
.39077e		22 87 07 39	jsl $390787	IPRINT          JSL IPUTS
.390782		22 17 09 39	jsl $390917	                JSL IPRINTCR
.390786		6b		rtl		                RTL
.390787		48		pha		IPUTS           PHA
.390788		08		php		                PHP
.390789		e2 20		sep #$20	                SEP #$20        ; set A short
.39078b		c2 10		rep #$10	                REP #$10        ; set X long
.39078d		bd 00 00	lda $0000,x	iputs1          LDA $0,b,x      ; read from the string
.390790		f0 08		beq $39079a	                BEQ iputs_done
.390792		22 9e 07 39	jsl $39079e	iputs2          JSL IPUTC
.390796		e8		inx		iputs3          INX
.390797		4c 8d 07	jmp $39078d	                JMP iputs1
.39079a		e8		inx		iputs_done      INX
.39079b		28		plp		                PLP
.39079c		68		pla		                PLA
.39079d		6b		rtl		                RTL
.39079e						IPUTC
.39079e		da		phx		                PHX
.39079f		5a		phy		                PHY
.3907a0		0b		phd		                PHD
.3907a1		8b		phb		                PHB
.3907a2		08		php		                PHP                 ; stash the flags (we'll be changing M)
.3907a3		48		pha		                PHA             ; begin setdp macro
.3907a4		08		php		                PHP
.3907a5		c2 20		rep #$20	                REP #$20        ; set A long
.3907a7		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.3907aa		5b		tcd		                TCD
.3907ab		28		plp		                PLP
.3907ac		68		pla		                PLA             ; end setdp macro
.3907ad		48		pha		                PHA             ; begin setdbr macro
.3907ae		08		php		                PHP
.3907af		e2 20		sep #$20	                SEP #$20        ; set A short
.3907b1		a9 00		lda #$00	                LDA #0
.3907b3		48		pha		                PHA
.3907b4		ab		plb		                PLB
.3907b5		28		plp		                PLP
.3907b6		68		pla		                PLA             ; end setdbr macro
.3907b7		e2 20		sep #$20	                SEP #$20        ; set A short
.3907b9		c2 10		rep #$10	                REP #$10        ; set X long
.3907bb		48		pha		                PHA                 ; Save the character to print
.3907bc		af 03 07 00	lda $000703	                LDA @lCHAN_OUT      ; Check the output channel #
.3907c0		f0 16		beq $3907d8	                BEQ putc_screen     ; If it's 0: print to the screen
.3907c2		c9 01		cmp #$01	                CMP #CHAN_COM1      ; Check to see if it's the COM1 port
.3907c4		f0 07		beq $3907cd	                BEQ putc_uart       ; Yes: handle printing to the UART
.3907c6		c9 02		cmp #$02	                CMP #CHAN_COM2      ; Check to see if it's the COM2 port
.3907c8		f0 03		beq $3907cd	                BEQ putc_uart       ; Yes: handle printing to the UART
.3907ca		68		pla		                PLA                 ; Otherwise, just exit
.3907cb		80 57		bra $390824	                BRA done
.3907cd		22 d2 5b 39	jsl $395bd2	putc_uart       JSL UART_SELECT     ; Point to the correct UART
.3907d1		68		pla		                PLA                 ; Recover the character to send
.3907d2		22 a7 5c 39	jsl $395ca7	                JSL UART_PUTC       ; Send the character
.3907d6		80 4c		bra $390824	                BRA done
.3907d8		68		pla		putc_screen     PLA                 ; Get the character to print
.3907d9		c9 0a		cmp #$0a	                CMP #CHAR_LF        ; Linefeed moves cursor down one line
.3907db		f0 69		beq $390846	                BEQ go_down
.3907dd		c9 20		cmp #$20	                CMP #$20
.3907df		90 19		bcc $3907fa	                BCC check_ctrl0     ; [$00..$1F]: check for arrows
.3907e1		c9 7f		cmp #$7f	                CMP #$7F
.3907e3		f0 45		beq $39082a	                BEQ do_del
.3907e5		b0 02		bcs $3907e9	                BCS check_A0        ; [$20..$7E]: print it
.3907e7		80 31		bra $39081a	                BRA printc
.3907e9		c9 a0		cmp #$a0	check_A0        CMP #$A0
.3907eb		90 02		bcc $3907ef	                BCC check_ctrl1
.3907ed		80 2b		bra $39081a	                BRA printc          ; [$A0..$FF]: print it
.3907ef		c9 91		cmp #$91	check_ctrl1     CMP #CHAR_DOWN      ; If the down arrow key was pressed
.3907f1		f0 53		beq $390846	                BEQ go_down         ; ... move the cursor down one row
.3907f3		c9 9d		cmp #$9d	                CMP #CHAR_LEFT      ; If the left arrow key was pressed
.3907f5		f0 61		beq $390858	                BEQ go_left         ; ... move the cursor left one column
.3907f7		4c 24 08	jmp $390824	                JMP done
.3907fa		c9 09		cmp #$09	check_ctrl0     CMP #CHAR_TAB       ; If it's a TAB...
.3907fc		f0 69		beq $390867	                BEQ do_TAB          ; ... move to the next TAB stop
.3907fe		c9 08		cmp #$08	                CMP #CHAR_BS        ; If it's a backspace...
.390800		f0 34		beq $390836	                BEQ backspace       ; ... move the cursor back and replace with a space
.390802		c9 0d		cmp #$0d	                CMP #CHAR_CR        ; If the carriage return was pressed
.390804		f0 3a		beq $390840	                BEQ do_cr           ; ... move cursor down and to the first column
.390806		c9 11		cmp #$11	                CMP #CHAR_UP        ; If the up arrow key was pressed
.390808		f0 42		beq $39084c	                BEQ go_up           ; ... move the cursor up one row
.39080a		c9 1d		cmp #$1d	                CMP #CHAR_RIGHT     ; If the right arrow key was pressed
.39080c		f0 44		beq $390852	                BEQ go_right        ; ... move the cursor right one column
.39080e		c9 0f		cmp #$0f	                CMP #CHAR_INS       ; If the insert key was pressed
.390810		f0 1e		beq $390830	                BEQ do_ins          ; ... insert a space
.390812		c9 01		cmp #$01	                CMP #CHAR_CTRL_A    ; Check for CTRL-A (start of line)
.390814		f0 48		beq $39085e	                BEQ go_sol          ; ... move the cursor to the start of the line
.390816		c9 05		cmp #$05	                CMP #CHAR_CTRL_E    ; Check for CTRL-E (end of line)
.390818		f0 74		beq $39088e	                BEQ go_eol          ; ... move the cursor to the end of the line
.39081a		87 17		sta [$17]	printc          STA [CURSORPOS]     ; Save the character on the screen
.39081c		a5 1e		lda $1e		                LDA CURCOLOR        ; Set the color based on CURCOLOR
.39081e		87 1f		sta [$1f]	                STA [COLORPOS]
.390820		22 77 09 39	jsl $390977	                JSL ICSRRIGHT       ; And advance the cursor
.390824		28		plp		done            PLP
.390825		ab		plb		                PLB
.390826		2b		pld		                PLD
.390827		7a		ply		                PLY
.390828		fa		plx		                PLX
.390829		6b		rtl		                RTL
.39082a		22 bb 08 39	jsl $3908bb	do_del          JSL SCRSHIFTLL      ; Shift the current line left one space into the cursor
.39082e		80 f4		bra $390824	                BRA done
.390830		22 df 08 39	jsl $3908df	do_ins          JSL SCRSHIFTLR      ; Shift the current line right one space from the cursor
.390834		80 ee		bra $390824	                BRA done
.390836		22 aa 09 39	jsl $3909aa	backspace       JSL ICSRLEFT
.39083a		22 bb 08 39	jsl $3908bb	                JSL SCRSHIFTLL      ; Shift the current line left one space into the cursor
.39083e		80 e4		bra $390824	                BRA done
.390840		22 17 09 39	jsl $390917	do_cr           JSL IPRINTCR        ; Move the cursor to the beginning of the next line
.390844		80 de		bra $390824	                BRA done
.390846		22 f6 09 39	jsl $3909f6	go_down         JSL ICSRDOWN        ; Move the cursor down one row (might force a scroll)
.39084a		80 d8		bra $390824	                BRA done
.39084c		22 d0 09 39	jsl $3909d0	go_up           JSL ICSRUP          ; Move the cursor up one line
.390850		80 d2		bra $390824	                BRA done
.390852		22 77 09 39	jsl $390977	go_right        JSL ICSRRIGHT       ; Move the cursor right one column
.390856		80 cc		bra $390824	                BRA done
.390858		22 aa 09 39	jsl $3909aa	go_left         JSL ICSRLEFT        ; Move the cursor left one column
.39085c		80 c6		bra $390824	                BRA done
.39085e						go_sol
.39085e		c2 20		rep #$20	                REP #$20        ; set A long
.390860		a2 00 00	ldx #$0000	                LDX #0
.390863		a4 1c		ldy $1c		                LDY CURSORY
.390865		80 21		bra $390888	                BRA do_locate
.390867						do_TAB
.390867		c2 20		rep #$20	                REP #$20        ; set A long
.390869		a5 1a		lda $1a		                LDA CURSORX         ; Get the current column
.39086b		29 f8 ff	and #$fff8	                AND #$FFF8          ; See which group of 8 it's in
.39086e		18		clc		                CLC
.39086f		69 08 00	adc #$0008	                ADC #$0008          ; And move it to the next one
.390872		aa		tax		                TAX
.390873		a4 1c		ldy $1c		                LDY CURSORY
.390875		e2 20		sep #$20	                SEP #$20        ; set A short
.390877		e4 0f		cpx $0f		set_xy          CPX COLS_VISIBLE    ; Check if we're still on screen horizontally
.390879		90 04		bcc $39087f	                BCC check_row       ; Yes: check the row
.39087b		a2 00 00	ldx #$0000	                LDX #0              ; No: move to the first column...
.39087e		c8		iny		                INY                 ; ... and the next row
.39087f		c4 13		cpy $13		check_row       CPY LINES_VISIBLE   ; Check if we're still on the screen vertically
.390881		90 05		bcc $390888	                BCC do_locate       ; Yes: reposition the cursor
.390883		22 67 0a 39	jsl $390a67	                JSL ISCROLLUP       ; No: scroll the screen
.390887		88		dey		                DEY                 ; And set the row to the last one
.390888		22 1b 0a 39	jsl $390a1b	do_locate       JSL ILOCATE         ; Set the cursor position
.39088c		80 96		bra $390824	                BRA done
.39088e		a6 0f		ldx $0f		go_eol          LDX COLS_VISIBLE    ; Move the cursor to the right most column
.390890		ca		dex		                DEX
.390891		a4 1c		ldy $1c		                LDY CURSORY
.390893		22 1b 0a 39	jsl $390a1b	                JSL ILOCATE
.390897		e2 20		sep #$20	                SEP #$20        ; set A short
.390899		a7 17		lda [$17]	eol_loop        LDA [CURSORPOS]     ; Get the character under the cursor
.39089b		c9 20		cmp #$20	                CMP #CHAR_SP        ; Is it blank?
.39089d		d0 0b		bne $3908aa	                BNE eol_done        ; No: exit the loop
.39089f		22 aa 09 39	jsl $3909aa	                JSL ICSRLEFT        ; Yes: move to the left
.3908a3		a6 1a		ldx $1a		                LDX CURSORX         ; Are we at column 0?
.3908a5		d0 f2		bne $390899	                BNE eol_loop        ; No: try again
.3908a7		82 7a ff	brl $390824	                BRL done            ; Yes: we're done
.3908aa		a6 1a		ldx $1a		eol_done        LDX CURSORX         ; Check the column
.3908ac		e8		inx		                INX
.3908ad		e4 0f		cpx $0f		                CPX COLS_VISIBLE    ; Is it the right most?
.3908af		d0 03		bne $3908b4	                BNE eol_right
.3908b1		82 70 ff	brl $390824	                BRL done            ; Yes: we're done
.3908b4		22 77 09 39	jsl $390977	eol_right       JSL ICSRRIGHT       ; No: move right one column
.3908b8		82 69 ff	brl $390824	                BRL done
.3908bb		da		phx		SCRSHIFTLL      PHX
.3908bc		5a		phy		                PHY
.3908bd		48		pha		                PHA
.3908be		0b		phd		                PHD
.3908bf		08		php		                PHP
.3908c0		48		pha		                PHA             ; begin setdp macro
.3908c1		08		php		                PHP
.3908c2		c2 20		rep #$20	                REP #$20        ; set A long
.3908c4		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.3908c7		5b		tcd		                TCD
.3908c8		28		plp		                PLP
.3908c9		68		pla		                PLA             ; end setdp macro
.3908ca		c2 30		rep #$30	                REP #$30        ; set A&X long
.3908cc		a5 17		lda $17		                LDA CURSORPOS       ; Get the current cursor position
.3908ce		a8		tay		                TAY                 ; Set it as the destination
.3908cf		aa		tax		                TAX
.3908d0		e8		inx		                INX                 ; And set the next cell as the source
.3908d1		18		clc		                CLC                 ; Calculate the length of the block to move
.3908d2		a5 0f		lda $0f		                LDA COLS_VISIBLE    ; as columns visible - X
.3908d4		e5 1a		sbc $1a		                SBC CURSORX
.3908d6		54 af af	mvn $af,$af	                MVN $AF, $AF        ; And move the block
.3908d9		28		plp		                PLP
.3908da		2b		pld		                PLD
.3908db		68		pla		                PLA
.3908dc		7a		ply		                PLY
.3908dd		fa		plx		                PLX
.3908de		6b		rtl		                RTL
.3908df		da		phx		SCRSHIFTLR      PHX
.3908e0		48		pha		                PHA
.3908e1		0b		phd		                PHD
.3908e2		08		php		                PHP
.3908e3		48		pha		                PHA             ; begin setdp macro
.3908e4		08		php		                PHP
.3908e5		c2 20		rep #$20	                REP #$20        ; set A long
.3908e7		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.3908ea		5b		tcd		                TCD
.3908eb		28		plp		                PLP
.3908ec		68		pla		                PLA             ; end setdp macro
.3908ed		c2 30		rep #$30	                REP #$30        ; set A&X long
.3908ef		a5 1a		lda $1a		                LDA CURSORX         ; What column are we on
.3908f1		1a		inc a		                INC A
.3908f2		c5 0f		cmp $0f		                CMP COLS_VISIBLE    ; >= the # visible?
.3908f4		b0 1b		bcs $390911	                BGE done            ; Yes: just skip the whole thing
.3908f6		38		sec		                SEC                 ; Calculate the length of the block to move
.3908f7		a5 0f		lda $0f		                LDA COLS_VISIBLE
.3908f9		e5 1a		sbc $1a		                SBC CURSORX
.3908fb		1a		inc a		                INC A
.3908fc		18		clc		                CLC
.3908fd		65 17		adc $17		                ADC CURSORPOS       ; Add the current cursor position
.3908ff		3a		dec a		                DEC A
.390900		a8		tay		                TAY                 ; Make it the destination
.390901		3a		dec a		                DEC A               ; Move to the previous column
.390902		aa		tax		                TAX                 ; Make it the source
.390903		38		sec		                SEC                 ; Calculate the length of the block to move
.390904		a5 0f		lda $0f		                LDA COLS_VISIBLE    ; as columns visible - X
.390906		e5 1a		sbc $1a		                SBC CURSORX
.390908		44 af af	mvp $af,$af	                MVP $AF, $AF        ; And move the block
.39090b		e2 20		sep #$20	                SEP #$20        ; set A short
.39090d		a9 20		lda #$20	                LDA #CHAR_SP        ; Put a blank space at the cursor position
.39090f		87 17		sta [$17]	                STA [CURSORPOS]
.390911		28		plp		done            PLP
.390912		2b		pld		                PLD
.390913		68		pla		                PLA
.390914		fa		plx		                PLX
.390915		6b		rtl		                RTL
.390916						IPUTB
.390916		6b		rtl		                RTL
.390917						IPRINTCR
.390917		da		phx		                PHX
.390918		5a		phy		                PHY
.390919		8b		phb		                PHB
.39091a		0b		phd		                PHD
.39091b		08		php		                PHP
.39091c		48		pha		                PHA             ; begin setdbr macro
.39091d		08		php		                PHP
.39091e		e2 20		sep #$20	                SEP #$20        ; set A short
.390920		a9 00		lda #$00	                LDA #0
.390922		48		pha		                PHA
.390923		ab		plb		                PLB
.390924		28		plp		                PLP
.390925		68		pla		                PLA             ; end setdbr macro
.390926		48		pha		                PHA             ; begin setdp macro
.390927		08		php		                PHP
.390928		c2 20		rep #$20	                REP #$20        ; set A long
.39092a		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.39092d		5b		tcd		                TCD
.39092e		28		plp		                PLP
.39092f		68		pla		                PLA             ; end setdp macro
.390930		e2 20		sep #$20	                SEP #$20        ; set A short
.390932		c2 10		rep #$10	                REP #$10        ; set X long
.390934		af 03 07 00	lda $000703	                LDA @lCHAN_OUT
.390938		f0 1c		beq $390956	                BEQ scr_printcr
.39093a		c9 01		cmp #$01	                CMP #CHAN_COM1      ; Check to see if it's the COM1 port
.39093c		f0 06		beq $390944	                BEQ uart_printcr    ; Yes: handle printing to the UART
.39093e		c9 02		cmp #$02	                CMP #CHAN_COM2      ; Check to see if it's the COM2 port
.390940		f0 02		beq $390944	                BEQ uart_printcr    ; Yes: handle printing to the UART
.390942		80 1c		bra $390960	                BRA done
.390944		22 d2 5b 39	jsl $395bd2	uart_printcr    JSL UART_SELECT
.390948		a9 0d		lda #$0d	                LDA #CHAR_CR
.39094a		22 9e 07 39	jsl $39079e	                JSL IPUTC
.39094e		a9 0a		lda #$0a	                LDA #CHAR_LF
.390950		22 9e 07 39	jsl $39079e	                JSL IPUTC
.390954		80 0a		bra $390960	                BRA done
.390956		a2 00 00	ldx #$0000	scr_printcr     LDX #0
.390959		a4 1c		ldy $1c		                LDY CURSORY
.39095b		c8		iny		                INY
.39095c		22 1b 0a 39	jsl $390a1b	                JSL ILOCATE
.390960		28		plp		done            PLP
.390961		2b		pld		                PLD
.390962		ab		plb		                PLB
.390963		7a		ply		                PLY
.390964		fa		plx		                PLX
.390965		6b		rtl		                RTL
.390966		da		phx		ICSRHOME        PHX
.390967		5a		phy		                PHY
.390968		08		php		                PHP
.390969		a2 00 00	ldx #$0000	                LDX #0
.39096c		a0 00 00	ldy #$0000	                LDY #0
.39096f		22 1b 0a 39	jsl $390a1b	                JSL ILOCATE
.390973		28		plp		                PLP
.390974		7a		ply		                PLY
.390975		fa		plx		                PLX
.390976		6b		rtl		                RTL
.390977		da		phx		ICSRRIGHT       PHX
.390978		5a		phy		                PHY
.390979		48		pha		                PHA
.39097a		0b		phd		                PHD
.39097b		08		php		                PHP
.39097c		c2 20		rep #$20	                REP #$20        ; set A long
.39097e		c2 10		rep #$10	                REP #$10        ; set X long
.390980		48		pha		                PHA             ; begin setdp macro
.390981		08		php		                PHP
.390982		c2 20		rep #$20	                REP #$20        ; set A long
.390984		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
.390987		5b		tcd		                TCD
.390988		28		plp		                PLP
.390989		68		pla		                PLA             ; end setdp macro
.39098a		a6 1a		ldx $1a		                LDX CURSORX           ; Get the new column
.39098c		e8		inx		                INX
.39098d		a4 1c		ldy $1c		                LDY CURSORY           ; Get the current row
.39098f		e4 0f		cpx $0f		                CPX COLS_VISIBLE      ; Are we off screen?
.390991		90 0d		bcc $3909a0	                BCC icsrright_nowrap  ; No: just set the position
.390993		a2 00 00	ldx #$0000	                LDX #0                ; Yes: move to the first column
.390996		c8		iny		                INY                   ; And move to the next row
.390997		c4 13		cpy $13		                CPY LINES_VISIBLE     ; Are we still off screen?
.390999		90 05		bcc $3909a0	                BCC icsrright_nowrap  ; No: just set the position
.39099b		88		dey		                DEY                   ; Yes: lock to the last row
.39099c		22 67 0a 39	jsl $390a67	                JSL ISCROLLUP         ; But scroll the screen up
.3909a0						icsrright_nowrap
.3909a0		22 1b 0a 39	jsl $390a1b	                JSL ILOCATE           ; Set the cursor position
.3909a4		28		plp		                PLP
.3909a5		2b		pld		                PLD
.3909a6		68		pla		                PLA
.3909a7		7a		ply		                PLY
.3909a8		fa		plx		                PLX
.3909a9		6b		rtl		                RTL
.3909aa						ICSRLEFT
.3909aa		da		phx		                PHX
.3909ab		5a		phy		                PHY
.3909ac		48		pha		                PHA
.3909ad		0b		phd		                PHD
.3909ae		08		php		                PHP
.3909af		c2 30		rep #$30	                REP #$30        ; set A&X long
.3909b1		48		pha		                PHA             ; begin setdp macro
.3909b2		08		php		                PHP
.3909b3		c2 20		rep #$20	                REP #$20        ; set A long
.3909b5		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
.3909b8		5b		tcd		                TCD
.3909b9		28		plp		                PLP
.3909ba		68		pla		                PLA             ; end setdp macro
.3909bb		a5 1a		lda $1a		                LDA CURSORX
.3909bd		f0 0b		beq $3909ca	                BEQ icsrleft_done_already_zero ; Check that we are not already @ Zero
.3909bf		a6 1a		ldx $1a		                LDX CURSORX
.3909c1		ca		dex		                DEX
.3909c2		86 1a		stx $1a		                STX CURSORX
.3909c4		a4 1c		ldy $1c		                LDY CURSORY
.3909c6		22 1b 0a 39	jsl $390a1b	                JSL ILOCATE
.3909ca						icsrleft_done_already_zero
.3909ca		28		plp		                PLP
.3909cb		2b		pld		                PLD
.3909cc		68		pla		                PLA
.3909cd		7a		ply		                PLY
.3909ce		fa		plx		                PLX
.3909cf		6b		rtl		                RTL
.3909d0						ICSRUP
.3909d0		da		phx		                PHX
.3909d1		5a		phy		                PHY
.3909d2		48		pha		                PHA
.3909d3		0b		phd		                PHD
.3909d4		08		php		                PHP
.3909d5		c2 30		rep #$30	                REP #$30        ; set A&X long
.3909d7		48		pha		                PHA             ; begin setdp macro
.3909d8		08		php		                PHP
.3909d9		c2 20		rep #$20	                REP #$20        ; set A long
.3909db		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
.3909de		5b		tcd		                TCD
.3909df		28		plp		                PLP
.3909e0		68		pla		                PLA             ; end setdp macro
.3909e1		a5 1c		lda $1c		                LDA CURSORY
.3909e3		f0 0b		beq $3909f0	                BEQ isrup_done_already_zero ; Check if we are not already @ Zero
.3909e5		a4 1c		ldy $1c		                LDY CURSORY
.3909e7		88		dey		                DEY
.3909e8		84 1c		sty $1c		                STY CURSORY
.3909ea		a6 1a		ldx $1a		                LDX CURSORX
.3909ec		22 1b 0a 39	jsl $390a1b	                JSL ILOCATE
.3909f0						isrup_done_already_zero
.3909f0		28		plp		                PLP
.3909f1		2b		pld		                PLD
.3909f2		68		pla		                PLA
.3909f3		7a		ply		                PLY
.3909f4		fa		plx		                PLX
.3909f5		6b		rtl		                RTL
.3909f6		da		phx		ICSRDOWN        PHX
.3909f7		5a		phy		                PHY
.3909f8		0b		phd		                PHD
.3909f9		c2 30		rep #$30	                REP #$30        ; set A&X long
.3909fb		48		pha		                PHA             ; begin setdp macro
.3909fc		08		php		                PHP
.3909fd		c2 20		rep #$20	                REP #$20        ; set A long
.3909ff		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
.390a02		5b		tcd		                TCD
.390a03		28		plp		                PLP
.390a04		68		pla		                PLA             ; end setdp macro
.390a05		a6 1a		ldx $1a		                LDX CURSORX                 ; Get the current column
.390a07		a4 1c		ldy $1c		                LDY CURSORY                 ; Get the new row
.390a09		c8		iny		                INY
.390a0a		c4 13		cpy $13		                CPY LINES_VISIBLE           ; Check to see if we're off screen
.390a0c		90 05		bcc $390a13	                BCC icsrdown_noscroll       ; No: go ahead and set the position
.390a0e		88		dey		                DEY                         ; Yes: go back to the last row
.390a0f		22 67 0a 39	jsl $390a67	                JSL ISCROLLUP               ; But scroll the screen up
.390a13						icsrdown_noscroll
.390a13		22 1b 0a 39	jsl $390a1b	                JSL ILOCATE                 ; And set the cursor position
.390a17		2b		pld		                PLD
.390a18		7a		ply		                PLY
.390a19		fa		plx		                PLX
.390a1a		6b		rtl		                RTL
.390a1b		48		pha		ILOCATE         PHA
.390a1c		0b		phd		                PHD
.390a1d		08		php		                PHP
.390a1e		48		pha		                PHA             ; begin setdp macro
.390a1f		08		php		                PHP
.390a20		c2 20		rep #$20	                REP #$20        ; set A long
.390a22		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.390a25		5b		tcd		                TCD
.390a26		28		plp		                PLP
.390a27		68		pla		                PLA             ; end setdp macro
.390a28		c2 30		rep #$30	                REP #$30        ; set A&X long
.390a2a						ilocate_scroll
.390a2a		c4 13		cpy $13		                CPY LINES_VISIBLE
.390a2c		90 07		bcc $390a35	                BCC ilocate_scrolldone
.390a2e		22 67 0a 39	jsl $390a67	                JSL ISCROLLUP
.390a32		88		dey		                DEY
.390a33		80 f5		bra $390a2a	                BRA ilocate_scroll
.390a35						ilocate_scrolldone
.390a35		86 1a		stx $1a		                STX CURSORX
.390a37		84 1c		sty $1c		                STY CURSORY
.390a39		a5 0c		lda $0c		                LDA SCREENBEGIN
.390a3b						ilocate_row
.390a3b		c0 00 00	cpy #$0000	                CPY #$0
.390a3e		f0 08		beq $390a48	                BEQ ilocate_right
.390a40		18		clc		ilocate_down    CLC
.390a41		65 11		adc $11		                ADC COLS_PER_LINE
.390a43		88		dey		                DEY
.390a44		f0 02		beq $390a48	                BEQ ilocate_right
.390a46		80 f8		bra $390a40	                BRA ilocate_down
.390a48		18		clc		ilocate_right   CLC
.390a49		65 1a		adc $1a		                ADC CURSORX             ; move the cursor right X columns
.390a4b		85 17		sta $17		                STA CURSORPOS
.390a4d		a4 1c		ldy $1c		                LDY CURSORY
.390a4f		98		tya		                TYA
.390a50		8f 16 00 af	sta $af0016	                STA @lVKY_TXT_CURSOR_Y_REG_L  ;Store in Vicky's registers
.390a54		8a		txa		                TXA
.390a55		8f 14 00 af	sta $af0014	                STA @lVKY_TXT_CURSOR_X_REG_L  ;Store in Vicky's register
.390a59		c2 20		rep #$20	                REP #$20        ; set A long
.390a5b		18		clc		                CLC
.390a5c		a5 17		lda $17		                LDA CURSORPOS
.390a5e		69 00 20	adc #$2000	                ADC #<>(CS_COLOR_MEM_PTR - CS_TEXT_MEM_PTR)
.390a61		85 1f		sta $1f		                STA COLORPOS
.390a63		28		plp		ilocate_done    PLP
.390a64		2b		pld		                PLD
.390a65		68		pla		                PLA
.390a66		6b		rtl		                RTL
.390a67						ISCROLLUP
.390a67		48		pha		                PHA
.390a68		da		phx		                PHX
.390a69		5a		phy		                PHY
.390a6a		8b		phb		                PHB
.390a6b		0b		phd		                PHD
.390a6c		08		php		                PHP
.390a6d		48		pha		                PHA             ; begin setdp macro
.390a6e		08		php		                PHP
.390a6f		c2 20		rep #$20	                REP #$20        ; set A long
.390a71		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.390a74		5b		tcd		                TCD
.390a75		28		plp		                PLP
.390a76		68		pla		                PLA             ; end setdp macro
.390a77		c2 30		rep #$30	                REP #$30        ; set A&X long
.390a79		a5 11		lda $11		                LDA COLS_PER_LINE
.390a7b		8f 00 01 00	sta $000100	                STA @l UNSIGNED_MULT_A_LO
.390a7f		a5 13		lda $13		                LDA LINES_VISIBLE
.390a81		8f 02 01 00	sta $000102	                STA @l UNSIGNED_MULT_B_LO
.390a85		af 04 01 00	lda $000104	                LDA @l UNSIGNED_MULT_AL_LO
.390a89		85 00		sta $00		                STA TMPPTR1
.390a8b		18		clc		                CLC
.390a8c		a9 00 a0	lda #$a000	                LDA #$A000
.390a8f		a8		tay		                TAY
.390a90		65 11		adc $11		                ADC COLS_PER_LINE
.390a92		aa		tax		                TAX
.390a93		a5 00		lda $00		                LDA TMPPTR1
.390a95		54 af af	mvn $af,$af	                MVN $AF,$AF
.390a98		c2 30		rep #$30	                REP #$30        ; set A&X long
.390a9a		18		clc		                CLC
.390a9b		a9 00 c0	lda #$c000	                LDA #$C000
.390a9e		a8		tay		                TAY
.390a9f		65 11		adc $11		                ADC COLS_PER_LINE
.390aa1		aa		tax		                TAX
.390aa2		a5 00		lda $00		                LDA TMPPTR1
.390aa4		54 af af	mvn $af,$af	                MVN $AF,$AF
.390aa7		a5 00		lda $00		                LDA TMPPTR1
.390aa9		48		pha		                PHA
.390aaa		18		clc		                CLC
.390aab		69 00 a0	adc #$a000	                ADC #<>CS_TEXT_MEM_PTR
.390aae		85 00		sta $00		                STA TMPPTR1
.390ab0		a0 00 00	ldy #$0000	                LDY #0
.390ab3		a9 20 00	lda #$0020	                LDA #' '
.390ab6		97 00		sta [$00],y	clr_text        STA [TMPPTR1],Y
.390ab8		c8		iny		                INY
.390ab9		c4 0f		cpy $0f		                CPY COLS_VISIBLE
.390abb		d0 f9		bne $390ab6	                BNE clr_text
.390abd		68		pla		                PLA
.390abe		18		clc		                CLC
.390abf		69 00 c0	adc #$c000	                ADC #<>CS_COLOR_MEM_PTR
.390ac2		85 00		sta $00		                STA TMPPTR1
.390ac4		a0 00 00	ldy #$0000	                LDY #0
.390ac7		a5 1e		lda $1e		                LDA CURCOLOR
.390ac9		97 00		sta [$00],y	clr_color       STA [TMPPTR1],Y
.390acb		c8		iny		                INY
.390acc		c4 0f		cpy $0f		                CPY COLS_VISIBLE
.390ace		d0 f9		bne $390ac9	                BNE clr_color
.390ad0		28		plp		                PLP
.390ad1		2b		pld		                PLD
.390ad2		ab		plb		                PLB
.390ad3		7a		ply		                PLY
.390ad4		fa		plx		                PLX
.390ad5		68		pla		                PLA
.390ad6		6b		rtl		                RTL
.390ad7		08		php		IPRINTH         PHP
.390ad8		48		pha		                PHA
.390ad9						iprinth1
.390ad9		e2 20		sep #$20	                SEP #$20        ; set A short
.390adb		bd 00 00	lda $0000,x	                LDA #0,b,x      ; Read the value to be printed
.390ade		4a		lsr a		                LSR
.390adf		4a		lsr a		                LSR
.390ae0		4a		lsr a		                LSR
.390ae1		4a		lsr a		                LSR
.390ae2		22 31 0b 39	jsl $390b31	                JSL iprint_digit
.390ae6		bd 00 00	lda $0000,x	                LDA #0,b,x
.390ae9		22 31 0b 39	jsl $390b31	                JSL iprint_digit
.390aed		ca		dex		                DEX
.390aee		88		dey		                DEY
.390aef		d0 e8		bne $390ad9	                BNE iprinth1
.390af1		68		pla		                PLA
.390af2		28		plp		                PLP
.390af3		6b		rtl		                RTL
.390af4						IPRINTAH
.390af4		48		pha		                PHA
.390af5		08		php		                PHP
.390af6		8f 44 02 00	sta $000244	                STA @lCPUA            ; Save A where we can use it multiple times
.390afa		08		php		                PHP                   ; Get the processor status into A
.390afb		e2 20		sep #$20	                SEP #$20        ; set A short
.390afd		c2 10		rep #$10	                REP #$10        ; set X long
.390aff		68		pla		                PLA
.390b00		29 20		and #$20	                AND #%00100000        ; Is M = 1?
.390b02		c9 20		cmp #$20	                CMP #%00100000
.390b04		f0 14		beq $390b1a	                BEQ eight_bit
.390b06		af 46 02 00	lda $000246	                LDA @lCPUA+2          ; Get nibble [15..12]
.390b0a		4a		lsr a		                LSR A
.390b0b		4a		lsr a		                LSR A
.390b0c		4a		lsr a		                LSR A
.390b0d		4a		lsr a		                LSR A
.390b0e		22 31 0b 39	jsl $390b31	                JSL iprint_digit      ; And print it
.390b12		af 46 02 00	lda $000246	                LDA @lCPUA+2          ; Get nibble [11..8]
.390b16		22 31 0b 39	jsl $390b31	                JSL iprint_digit      ; And print it
.390b1a		af 44 02 00	lda $000244	eight_bit       LDA @lCPUA            ; Get nibble [7..4]
.390b1e		4a		lsr a		                LSR A
.390b1f		4a		lsr a		                LSR A
.390b20		4a		lsr a		                LSR A
.390b21		4a		lsr a		                LSR A
.390b22		22 31 0b 39	jsl $390b31	                JSL iprint_digit      ; And print it
.390b26		af 44 02 00	lda $000244	                LDA @lCPUA            ; Get nibble [3..0]
.390b2a		22 31 0b 39	jsl $390b31	                JSL iprint_digit      ; And print it
.390b2e		28		plp		                PLP
.390b2f		68		pla		                PLA
.390b30		6b		rtl		                RTL
.390b31		da		phx		iprint_digit    PHX
.390b32		c2 20		rep #$20	                REP #$20        ; set A long
.390b34		29 0f 00	and #$000f	                AND #$0F
.390b37		aa		tax		                TAX
.390b38		bf 81 72 39	lda $397281,x	                LDA hex_digits,X
.390b3c		22 9e 07 39	jsl $39079e	                JSL IPUTC       ; Print the digit
.390b40		fa		plx		                PLX
.390b41		6b		rtl		                RTL
.390b42		48		pha		ICLRSCREEN	    PHA
.390b43		da		phx		                PHX
.390b44		08		php		                PHP
.390b45		e2 20		sep #$20	                SEP #$20        ; set A short
.390b47		c2 10		rep #$10	                REP #$10        ; set X long
.390b49		a2 00 00	ldx #$0000	                LDX #$0000		          ; Only Use One Pointer
.390b4c		a9 20		lda #$20	                LDA #$20		            ; Fill the Entire Screen with Space
.390b4e		9f 00 a0 af	sta $afa000,x	iclearloop0	    STA CS_TEXT_MEM_PTR, x	;
.390b52		e8		inx		                inx
.390b53		e0 00 20	cpx #$2000	                cpx #$2000
.390b56		d0 f6		bne $390b4e	                bne iclearloop0
.390b58		a2 00 00	ldx #$0000	                LDX	#$0000		          ; Only Use One Pointer
.390b5b		af 1e 00 00	lda $00001e	                LDA @lCURCOLOR          ; Fill the Color Memory with the current color
.390b5f		9f 00 c0 af	sta $afc000,x	iclearloop1	    STA CS_COLOR_MEM_PTR, x	;
.390b63		e8		inx		                inx
.390b64		e0 00 20	cpx #$2000	                cpx #$2000
.390b67		d0 f6		bne $390b5f	                bne iclearloop1
.390b69		28		plp		                PLP
.390b6a		fa		plx		                PLX
.390b6b		68		pla		                PLA
.390b6c		6b		rtl		                RTL
.390b6d						COPYBYTES42
.390b6d		08		php		                PHP
.390b6e		0b		phd		                PHD
.390b6f		48		pha		                PHA             ; begin setdp macro
.390b70		08		php		                PHP
.390b71		c2 20		rep #$20	                REP #$20        ; set A long
.390b73		a9 00 00	lda #$0000	                LDA #TMPPTR1         ; set DP to page 0
.390b76		5b		tcd		                TCD
.390b77		28		plp		                PLP
.390b78		68		pla		                PLA             ; end setdp macro
.390b79		e2 20		sep #$20	                SEP #$20        ; set A short
.390b7b		c2 10		rep #$10	                REP #$10        ; set X long
.390b7d		a0 00 00	ldy #$0000	                LDY #0
.390b80		b7 00		lda [$00],y	copy_loop       LDA [TMPPTR1],Y
.390b82		97 04		sta [$04],y	                STA [TMPPTR2],Y
.390b84		c8		iny		                INY
.390b85		c0 2a 00	cpy #$002a	                CPY #42
.390b88		d0 f6		bne $390b80	                BNE copy_loop
.390b8a		2b		pld		                PLD
.390b8b		28		plp		                PLP
.390b8c		60		rts		                RTS
.390b8d						ICOLORFLAG
.390b8d		48		pha		                PHA
.390b8e		da		phx		                PHX
.390b8f		5a		phy		                PHY
.390b90		08		php		                PHP
.390b91		8b		phb		                PHB
.390b92		0b		phd		                PHD
.390b93		48		pha		                PHA             ; begin setdp macro
.390b94		08		php		                PHP
.390b95		c2 20		rep #$20	                REP #$20        ; set A long
.390b97		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
.390b9a		5b		tcd		                TCD
.390b9b		28		plp		                PLP
.390b9c		68		pla		                PLA             ; end setdp macro
.390b9d		c2 30		rep #$30	                REP #$30        ; set A&X long
.390b9f		a9 00 c0	lda #$c000	                LDA #<>CS_COLOR_MEM_PTR
.390ba2		85 04		sta $04		                STA TMPPTR2
.390ba4		a9 af 00	lda #$00af	                LDA #`CS_COLOR_MEM_PTR
.390ba7		85 06		sta $06		                STA TMPPTR2+2
.390ba9		a9 58 6f	lda #$6f58	                LDA #<>greet_clr_line1
.390bac		85 00		sta $00		                STA TMPPTR1
.390bae		a9 39 00	lda #$0039	                LDA #`greet_clr_line1
.390bb1		85 02		sta $02		                STA TMPPTR1+2
.390bb3		20 6d 0b	jsr $390b6d	                JSR COPYBYTES42
.390bb6		18		clc		                CLC
.390bb7		a5 04		lda $04		                LDA TMPPTR2
.390bb9		65 11		adc $11		                ADC COLS_PER_LINE
.390bbb		85 04		sta $04		                STA TMPPTR2
.390bbd		a9 82 6f	lda #$6f82	                LDA #<>greet_clr_line2
.390bc0		85 00		sta $00		                STA TMPPTR1
.390bc2		a9 39 00	lda #$0039	                LDA #`greet_clr_line2
.390bc5		85 02		sta $02		                STA TMPPTR1+2
.390bc7		20 6d 0b	jsr $390b6d	                JSR COPYBYTES42
.390bca		18		clc		                CLC
.390bcb		a5 04		lda $04		                LDA TMPPTR2
.390bcd		65 11		adc $11		                ADC COLS_PER_LINE
.390bcf		85 04		sta $04		                STA TMPPTR2
.390bd1		a9 ac 6f	lda #$6fac	                LDA #<>greet_clr_line3
.390bd4		85 00		sta $00		                STA TMPPTR1
.390bd6		a9 39 00	lda #$0039	                LDA #`greet_clr_line3
.390bd9		85 02		sta $02		                STA TMPPTR1+2
.390bdb		20 6d 0b	jsr $390b6d	                JSR COPYBYTES42
.390bde		18		clc		                CLC
.390bdf		a5 04		lda $04		                LDA TMPPTR2
.390be1		65 11		adc $11		                ADC COLS_PER_LINE
.390be3		85 04		sta $04		                STA TMPPTR2
.390be5		a9 d6 6f	lda #$6fd6	                LDA #<>greet_clr_line4
.390be8		85 00		sta $00		                STA TMPPTR1
.390bea		a9 39 00	lda #$0039	                LDA #`greet_clr_line4
.390bed		85 02		sta $02		                STA TMPPTR1+2
.390bef		20 6d 0b	jsr $390b6d	                JSR COPYBYTES42
.390bf2		18		clc		                CLC
.390bf3		a5 04		lda $04		                LDA TMPPTR2
.390bf5		65 11		adc $11		                ADC COLS_PER_LINE
.390bf7		85 04		sta $04		                STA TMPPTR2
.390bf9		a9 00 70	lda #$7000	                LDA #<>greet_clr_line5
.390bfc		85 00		sta $00		                STA TMPPTR1
.390bfe		a9 39 00	lda #$0039	                LDA #`greet_clr_line5
.390c01		85 02		sta $02		                STA TMPPTR1+2
.390c03		20 6d 0b	jsr $390b6d	                JSR COPYBYTES42
.390c06		2b		pld		                PLD
.390c07		ab		plb		                PLB
.390c08		28		plp		                PLP
.390c09		7a		ply		                PLY
.390c0a		fa		plx		                PLX
.390c0b		68		pla		                PLA
.390c0c		6b		rtl		                RTL
.390c0d		0b		phd		IINITCHLUT		  PHD
.390c0e		08		php		                PHP
.390c0f		48		pha		                PHA
.390c10		da		phx		                PHX
.390c11		e2 20		sep #$20	                SEP #$20        ; set A short
.390c13		e2 10		sep #$10	                SEP #$10        ; set X short
.390c15		a2 00		ldx #$00					        LDX	#$00
.390c17		bf 2a 70 39	lda $39702a,x	lutinitloop0	  LDA @lfg_color_lut,x		; get Local Data
.390c1b		9f 40 1f af	sta $af1f40,x	                STA FG_CHAR_LUT_PTR,x	; Write in LUT Memory
.390c1f		e8		inx		                inx
.390c20		e0 40		cpx #$40	                cpx #$40
.390c22		d0 f3		bne $390c17	                bne lutinitloop0
.390c24		a2 00		ldx #$00	                LDX	#$00
.390c26		bf 6a 70 39	lda $39706a,x	lutinitloop1	  LDA @lbg_color_lut,x		; get Local Data
.390c2a		9f 80 1f af	sta $af1f80,x	                STA BG_CHAR_LUT_PTR,x	; Write in LUT Memory
.390c2e		e8		inx		                INX
.390c2f		e0 40		cpx #$40	                CPX #$40
.390c31		d0 f3		bne $390c26	                bne lutinitloop1
.390c33		c2 20		rep #$20	                REP #$20        ; set A long
.390c35		c2 10		rep #$10	                REP #$10        ; set X long
.390c37		fa		plx		                PLX
.390c38		68		pla		                PLA
.390c39		28		plp		                PLP
.390c3a		2b		pld		                PLD
.390c3b		6b		rtl		                RTL
.390c3c						IINITGAMMATABLE
.390c3c		e2 20		sep #$20	                SEP #$20        ; set A short
.390c3e		c2 10		rep #$10	                REP #$10        ; set X long
.390c40		a2 00 00	ldx #$0000	                ldx #$0000
.390c43		bf 00 77 39	lda $397700,x	initgammaloop   LDA GAMMA_1_8_Tbl, x
.390c47		9f 00 40 af	sta $af4000,x	                STA GAMMA_B_LUT_PTR, x
.390c4b		9f 00 41 af	sta $af4100,x	                STA GAMMA_G_LUT_PTR, x
.390c4f		9f 00 42 af	sta $af4200,x	                STA GAMMA_R_LUT_PTR, x
.390c53		e8		inx		                inx
.390c54		e0 00 01	cpx #$0100	                cpx #$0100
.390c57		d0 ea		bne $390c43	                bne initgammaloop
.390c59		c2 30		rep #$30	                REP #$30        ; set A&X long
.390c5b		6b		rtl		                RTL
.390c5c		48		pha		IINITALLLUT     PHA
.390c5d		da		phx		                PHX
.390c5e		a2 00 00	ldx #$0000	                LDX #$0000
.390c61		e2 20		sep #$20	                SEP #$20        ; set A short
.390c63		a9 00		lda #$00	                LDA #$00
.390c65		85 0a		sta $0a		                STA $0A     ; Temp Location
.390c67						iinit_lut_loop
.390c67		86 02		stx $02		                STX $02
.390c69		a6 0a		ldx $0a		                LDX $0A
.390c6b		bf 00 76 39	lda $397600,x	                LDA GAMMA_2_2_Tbl, x
.390c6f		49 55		eor #$55	                EOR  #$55
.390c71		a6 02		ldx $02		                LDX $02
.390c73		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR, x
.390c77		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR, x
.390c7b		9f 00 28 af	sta $af2800,x	                STA @lGRPH_LUT2_PTR, x
.390c7f		9f 00 2c af	sta $af2c00,x	                STA @lGRPH_LUT3_PTR, x
.390c83		9f 00 30 af	sta $af3000,x	                STA @lGRPH_LUT4_PTR, x
.390c87		9f 00 34 af	sta $af3400,x	                STA @lGRPH_LUT5_PTR, x
.390c8b		9f 00 38 af	sta $af3800,x	                STA @lGRPH_LUT6_PTR, x
.390c8f		9f 00 3c af	sta $af3c00,x	                STA @lGRPH_LUT7_PTR, x
.390c93		e8		inx		                inx
.390c94		86 02		stx $02		                STX $02
.390c96		a6 0a		ldx $0a		                LDX $0A
.390c98		bf 00 78 39	lda $397800,x	                LDA RANDOM_LUT_Tbl, x
.390c9c		a6 02		ldx $02		                LDX $02
.390c9e		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR, x
.390ca2		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR, x
.390ca6		9f 00 28 af	sta $af2800,x	                STA @lGRPH_LUT2_PTR, x
.390caa		9f 00 2c af	sta $af2c00,x	                STA @lGRPH_LUT3_PTR, x
.390cae		9f 00 30 af	sta $af3000,x	                STA @lGRPH_LUT4_PTR, x
.390cb2		9f 00 34 af	sta $af3400,x	                STA @lGRPH_LUT5_PTR, x
.390cb6		9f 00 38 af	sta $af3800,x	                STA @lGRPH_LUT6_PTR, x
.390cba		9f 00 3c af	sta $af3c00,x	                STA @lGRPH_LUT7_PTR, x
.390cbe		e8		inx		                inx
.390cbf		86 02		stx $02		                STX $02
.390cc1		a6 0a		ldx $0a		                LDX $0A
.390cc3		bf 00 77 39	lda $397700,x	                LDA GAMMA_1_8_Tbl, x
.390cc7		49 aa		eor #$aa	                EOR  #$AA
.390cc9		a6 02		ldx $02		                LDX $02
.390ccb		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR, x
.390ccf		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR, x
.390cd3		9f 00 28 af	sta $af2800,x	                STA @lGRPH_LUT2_PTR, x
.390cd7		9f 00 2c af	sta $af2c00,x	                STA @lGRPH_LUT3_PTR, x
.390cdb		9f 00 30 af	sta $af3000,x	                STA @lGRPH_LUT4_PTR, x
.390cdf		9f 00 34 af	sta $af3400,x	                STA @lGRPH_LUT5_PTR, x
.390ce3		9f 00 38 af	sta $af3800,x	                STA @lGRPH_LUT6_PTR, x
.390ce7		9f 00 3c af	sta $af3c00,x	                STA @lGRPH_LUT7_PTR, x
.390ceb		e8		inx		                inx
.390cec		a9 ff		lda #$ff	                LDA #$FF
.390cee		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR, x
.390cf2		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR, x
.390cf6		9f 00 28 af	sta $af2800,x	                STA @lGRPH_LUT2_PTR, x
.390cfa		9f 00 2c af	sta $af2c00,x	                STA @lGRPH_LUT3_PTR, x
.390cfe		9f 00 30 af	sta $af3000,x	                STA @lGRPH_LUT4_PTR, x
.390d02		9f 00 34 af	sta $af3400,x	                STA @lGRPH_LUT5_PTR, x
.390d06		9f 00 38 af	sta $af3800,x	                STA @lGRPH_LUT6_PTR, x
.390d0a		9f 00 3c af	sta $af3c00,x	                STA @lGRPH_LUT7_PTR, x
.390d0e		e6 0a		inc $0a		                inc $0A
.390d10		e8		inx		                inx
.390d11		e0 00 04	cpx #$0400	                cpx #$0400
.390d14		f0 03		beq $390d19	                beq iinit_lut_exit
.390d16		82 4e ff	brl $390c67	                brl iinit_lut_loop
.390d19						iinit_lut_exit
.390d19		c2 30		rep #$30	                REP #$30        ; set A&X long
.390d1b		fa		plx		                PLX
.390d1c		68		pla		                PLA
.390d1d		6b		rtl		                RTL
.390d1e		48		pha		IINITVKYTXTMODE PHA
.390d1f		08		php		                PHP
.390d20		e2 20		sep #$20	                SEP #$20        ; set A short
.390d22		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H
.390d26		29 01		and #$01	                AND #$01
.390d28		c9 01		cmp #$01	                CMP #$01
.390d2a		d0 15		bne $390d41	                BNE INITVICKYMODE
.390d2c		a9 00		lda #$00	                LDA #$00
.390d2e		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H
.390d32		ea		nop		                NOP
.390d33		ea		nop		                NOP
.390d34		ea		nop		                NOP
.390d35		ea		nop		                NOP
.390d36		ea		nop		                NOP
.390d37		a9 01		lda #$01	                LDA #$01
.390d39		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H
.390d3d		ea		nop		                NOP
.390d3e		ea		nop		                NOP
.390d3f		ea		nop		                NOP
.390d40		ea		nop		                NOP
.390d41						INITVICKYMODE
.390d41		a9 00		lda #$00	                LDA #$00
.390d43		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H
.390d47		a9 01		lda #$01	                LDA #Mstr_Ctrl_Text_Mode_En       ; Set it to 640x480 for real
.390d49		8f 00 00 af	sta $af0000	                STA @L MASTER_CTRL_REG_L
.390d4d		e2 20		sep #$20	                SEP #$20        ; set A short
.390d4f		a9 20		lda #$20	                LDA #$20
.390d51		8f 05 00 af	sta $af0005	                STA BORDER_COLOR_B
.390d55		8f 07 00 af	sta $af0007	                STA BORDER_COLOR_R
.390d59		a9 00		lda #$00	                LDA #$00
.390d5b		8f 06 00 af	sta $af0006	                STA BORDER_COLOR_G
.390d5f		a9 01		lda #$01	                LDA #Border_Ctrl_Enable           ; Enable the Border
.390d61		8f 04 00 af	sta $af0004	                STA BORDER_CTRL_REG
.390d65		a9 20		lda #$20	                LDA #32                           ; Set the border to the standard 32 pixels
.390d67		8f 08 00 af	sta $af0008	                STA BORDER_X_SIZE
.390d6b		8f 09 00 af	sta $af0009	                STA BORDER_Y_SIZE
.390d6f		c2 30		rep #$30	                REP #$30        ; set A&X long
.390d71		22 78 0d 39	jsl $390d78	                JSL ISETSIZES                     ; Calculate the size of the text screen
.390d75		28		plp		                PLP
.390d76		68		pla		                PLA
.390d77		6b		rtl		                RTL
.390d78						ISETSIZES
.390d78		48		pha		                PHA
.390d79		da		phx		                PHX
.390d7a		5a		phy		                PHY
.390d7b		8b		phb		                PHB
.390d7c		0b		phd		                PHD
.390d7d		08		php		                PHP
.390d7e		48		pha		                PHA             ; begin setdp macro
.390d7f		08		php		                PHP
.390d80		c2 20		rep #$20	                REP #$20        ; set A long
.390d82		a9 00 00	lda #$0000	                LDA #<>BANK0_BEGIN         ; set DP to page 0
.390d85		5b		tcd		                TCD
.390d86		28		plp		                PLP
.390d87		68		pla		                PLA             ; end setdp macro
.390d88		48		pha		                PHA             ; begin setdbr macro
.390d89		08		php		                PHP
.390d8a		e2 20		sep #$20	                SEP #$20        ; set A short
.390d8c		a9 00		lda #$00	                LDA #0
.390d8e		48		pha		                PHA
.390d8f		ab		plb		                PLB
.390d90		28		plp		                PLP
.390d91		68		pla		                PLA             ; end setdbr macro
.390d92		e2 30		sep #$30	                SEP #$30        ; set A&X short
.390d94		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H
.390d98		29 03		and #$03	                AND #$03                    ; Mask off the resolution bits
.390d9a		0a		asl a		                ASL A
.390d9b		aa		tax		                TAX                         ; Index to the col/line count in X
.390d9c		c2 20		rep #$20	                REP #$20        ; set A long
.390d9e		bf 1b 0e 39	lda $390e1b,x	                LDA cols_by_res,X           ; Get the number of columns
.390da2		85 11		sta $11		                STA COLS_PER_LINE           ; This is how many columns there are per line in the memory
.390da4		85 0f		sta $0f		                STA COLS_VISIBLE            ; This is how many would be visible with no border
.390da6		bf 23 0e 39	lda $390e23,x	                LDA lines_by_res,X          ; Get the number of lines
.390daa		85 15		sta $15		                STA LINES_MAX               ; This is the total number of lines in memory
.390dac		85 13		sta $13		                STA LINES_VISIBLE           ; This is how many lines would be visible with no border
.390dae		e2 20		sep #$20	                SEP #$20        ; set A short
.390db0		af 04 00 af	lda $af0004	                LDA @l BORDER_CTRL_REG      ; Check to see if we have a border
.390db4		89 01		bit #$01	                BIT #Border_Ctrl_Enable
.390db6		f0 5c		beq $390e14	                BEQ done                    ; No border... the sizes are correct now
.390db8		af 08 00 af	lda $af0008	                LDA @l BORDER_X_SIZE        ; Get the horizontal border width
.390dbc		29 3f		and #$3f	                AND #$3F
.390dbe		89 03		bit #$03	                BIT #$03                    ; Check the lower two bits... indicates a partial column is eaten
.390dc0		d0 04		bne $390dc6	                BNE frac_width
.390dc2		4a		lsr a		                LSR A                       ; COLUMNS_HIDDEN := BORDER_X_SIZE / 4
.390dc3		4a		lsr a		                LSR A
.390dc4		80 03		bra $390dc9	                BRA store_width
.390dc6		4a		lsr a		frac_width      LSR A                       ; COLUMNS_HIDDEN := BORDER_X_SIZE / 4 + 1
.390dc7		4a		lsr a		                LSR A                       ; because a column is partially hidden
.390dc8		1a		inc a		                INC A
.390dc9		85 00		sta $00		store_width     STA TMPPTR1
.390dcb		64 01		stz $01		                STZ TMPPTR1+1
.390dcd		e2 20		sep #$20	                SEP #$20        ; set A short
.390dcf		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H    ; Check if we're pixel doubling
.390dd3		89 02		bit #$02	                BIT #Mstr_Ctrl_Video_Mode1
.390dd5		f0 04		beq $390ddb	                BEQ adjust_width            ; No... just adjust the width of the screen
.390dd7		c2 20		rep #$20	                REP #$20        ; set A long
.390dd9		46 00		lsr $00		                LSR TMPPTR1                 ; Yes... cut the adjustment in half
.390ddb						adjust_width
.390ddb		c2 20		rep #$20	                REP #$20        ; set A long
.390ddd		38		sec		                SEC
.390dde		a5 11		lda $11		                LDA COLS_PER_LINE
.390de0		e5 00		sbc $00		                SBC TMPPTR1
.390de2		85 0f		sta $0f		                STA COLS_VISIBLE
.390de4		af 09 00 af	lda $af0009	                LDA @l BORDER_Y_SIZE        ; Get the horizontal border width
.390de8		29 3f 00	and #$003f	                AND #$3F
.390deb		89 03 00	bit #$0003	                BIT #$03                    ; Check the lower two bits... indicates a partial column is eaten
.390dee		d0 04		bne $390df4	                BNE frac_height
.390df0		4a		lsr a		                LSR A                       ; COLUMNS_HIDDEN := BORDER_X_SIZE / 4
.390df1		4a		lsr a		                LSR A
.390df2		80 03		bra $390df7	                BRA store_height
.390df4		4a		lsr a		frac_height     LSR A                       ; COLUMNS_HIDDEN := BORDER_X_SIZE / 4 + 1
.390df5		4a		lsr a		                LSR A                       ; because a column is partially hidden
.390df6		1a		inc a		                INC A
.390df7		85 00		sta $00		store_height    STA TMPPTR1
.390df9		64 01		stz $01		                STZ TMPPTR1+1
.390dfb		e2 20		sep #$20	                SEP #$20        ; set A short
.390dfd		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H    ; Check if we're pixel doubling
.390e01		89 02		bit #$02	                BIT #Mstr_Ctrl_Video_Mode1
.390e03		f0 04		beq $390e09	                BEQ adjust_height           ; No... just adjust the height of the screen
.390e05		c2 20		rep #$20	                REP #$20        ; set A long
.390e07		46 00		lsr $00		                LSR TMPPTR1                 ; Yes... cut the adjustment in half
.390e09						adjust_height
.390e09		c2 20		rep #$20	                REP #$20        ; set A long
.390e0b		38		sec		                SEC
.390e0c		a5 15		lda $15		                LDA LINES_MAX
.390e0e		e5 00		sbc $00		                SBC TMPPTR1
.390e10		85 13		sta $13		                STA LINES_VISIBLE
.390e12		c2 30		rep #$30	                REP #$30        ; set A&X long
.390e14		28		plp		done            PLP
.390e15		2b		pld		                PLD
.390e16		ab		plb		                PLB
.390e17		7a		ply		                PLY
.390e18		fa		plx		                PLX
.390e19		68		pla		                PLA
.390e1a		6b		rtl		                RTL
>390e1b		50 00 64 00 28 00 32 00		cols_by_res     .word 80,100,40,50
>390e23		3c 00 4b 00 1e 00 25 00		lines_by_res    .word 60,75,30,37
.390e2b						IINITVKYGRPMODE
.390e2b		48		pha		                PHA
.390e2c		e2 20		sep #$20	                SEP #$20        ; set A short
.390e2e		a9 00		lda #$00	                LDA #$00          ; Enable Bit-Map and uses LUT0
.390e30		8f 00 01 af	sta $af0100	                STA @lBM0_CONTROL_REG
.390e34		a9 00		lda #$00	                LDA #$00          ;; (L)Load Base Address of where Bitmap begins
.390e36		8f 01 01 af	sta $af0101	                STA @lBM0_START_ADDY_L
.390e3a		a9 c0		lda #$c0	                LDA #$C0
.390e3c		8f 02 01 af	sta $af0102	                STA @lBM0_START_ADDY_M
.390e40		a9 00		lda #$00	                LDA #$00
.390e42		8f 03 01 af	sta $af0103	                STA @lBM0_START_ADDY_H ; This address is always base from
.390e46		a9 00		lda #$00	                LDA #$00          ; Enable Bit-Map and uses LUT0
.390e48		8f 08 01 af	sta $af0108	                STA @lBM1_CONTROL_REG
.390e4c		a9 00		lda #$00	                LDA #$00          ;; (L)Load Base Address of where Bitmap begins
.390e4e		8f 09 01 af	sta $af0109	                STA @lBM1_START_ADDY_L
.390e52		a9 c0		lda #$c0	                LDA #$C0
.390e54		8f 0a 01 af	sta $af010a	                STA @lBM1_START_ADDY_M
.390e58		a9 00		lda #$00	                LDA #$00
.390e5a		8f 0b 01 af	sta $af010b	                STA @lBM1_START_ADDY_H ; This address is always base from
.390e5e		c2 30		rep #$30	                REP #$30        ; set A&X long
.390e60		68		pla		                PLA
.390e61		6b		rtl		                RTL
.390e62						IINITTILEMODE
.390e62		6b		rtl		                RTL
.390e63		48		pha		IINITSPRITE     PHA
.390e64		e2 20		sep #$20	                SEP #$20        ; set A short
.390e66		a9 03		lda #$03	                LDA #$03    ; Enable 17 Sprites
.390e68		8f 00 0c af	sta $af0c00	                STA SP00_CONTROL_REG
.390e6c		8f 08 0c af	sta $af0c08	                STA SP01_CONTROL_REG
.390e70		8f 10 0c af	sta $af0c10	                STA SP02_CONTROL_REG
.390e74		8f 18 0c af	sta $af0c18	                STA SP03_CONTROL_REG
.390e78		8f 20 0c af	sta $af0c20	                STA SP04_CONTROL_REG
.390e7c		8f 28 0c af	sta $af0c28	                STA SP05_CONTROL_REG
.390e80		8f 30 0c af	sta $af0c30	                STA SP06_CONTROL_REG
.390e84		8f 38 0c af	sta $af0c38	                STA SP07_CONTROL_REG
.390e88		8f 40 0c af	sta $af0c40	                STA SP08_CONTROL_REG
.390e8c		8f 48 0c af	sta $af0c48	                STA SP09_CONTROL_REG
.390e90		8f 50 0c af	sta $af0c50	                STA SP10_CONTROL_REG
.390e94		8f 58 0c af	sta $af0c58	                STA SP11_CONTROL_REG
.390e98		8f 60 0c af	sta $af0c60	                STA SP12_CONTROL_REG
.390e9c		8f 68 0c af	sta $af0c68	                STA SP13_CONTROL_REG
.390ea0		8f 70 0c af	sta $af0c70	                STA SP14_CONTROL_REG
.390ea4		8f 78 0c af	sta $af0c78	                STA SP15_CONTROL_REG
.390ea8		8f 80 0c af	sta $af0c80	                STA SP16_CONTROL_REG
.390eac		a9 09		lda #$09	                LDA #$09
.390eae		8f 03 0c af	sta $af0c03	                STA SP00_ADDY_PTR_H
.390eb2		8f 0b 0c af	sta $af0c0b	                STA SP01_ADDY_PTR_H
.390eb6		8f 13 0c af	sta $af0c13	                STA SP02_ADDY_PTR_H
.390eba		8f 1b 0c af	sta $af0c1b	                STA SP03_ADDY_PTR_H
.390ebe		8f 23 0c af	sta $af0c23	                STA SP04_ADDY_PTR_H
.390ec2		8f 2b 0c af	sta $af0c2b	                STA SP05_ADDY_PTR_H
.390ec6		8f 33 0c af	sta $af0c33	                STA SP06_ADDY_PTR_H
.390eca		8f 3b 0c af	sta $af0c3b	                STA SP07_ADDY_PTR_H
.390ece		8f 43 0c af	sta $af0c43	                STA SP08_ADDY_PTR_H
.390ed2		8f 4b 0c af	sta $af0c4b	                STA SP09_ADDY_PTR_H
.390ed6		8f 53 0c af	sta $af0c53	                STA SP10_ADDY_PTR_H
.390eda		8f 5b 0c af	sta $af0c5b	                STA SP11_ADDY_PTR_H
.390ede		8f 63 0c af	sta $af0c63	                STA SP12_ADDY_PTR_H
.390ee2		8f 6b 0c af	sta $af0c6b	                STA SP13_ADDY_PTR_H
.390ee6		8f 73 0c af	sta $af0c73	                STA SP14_ADDY_PTR_H
.390eea		8f 7b 0c af	sta $af0c7b	                STA SP15_ADDY_PTR_H
.390eee		8f 83 0c af	sta $af0c83	                STA SP16_ADDY_PTR_H
.390ef2		a9 00		lda #$00	                LDA #$00
.390ef4		8f 02 0c af	sta $af0c02	                STA SP00_ADDY_PTR_M
.390ef8		a9 04		lda #$04	                LDA #$04
.390efa		8f 0a 0c af	sta $af0c0a	                STA SP01_ADDY_PTR_M
.390efe		a9 08		lda #$08	                LDA #$08
.390f00		8f 12 0c af	sta $af0c12	                STA SP02_ADDY_PTR_M
.390f04		a9 0c		lda #$0c	                LDA #$0C
.390f06		8f 1a 0c af	sta $af0c1a	                STA SP03_ADDY_PTR_M
.390f0a		a9 10		lda #$10	                LDA #$10
.390f0c		8f 22 0c af	sta $af0c22	                STA SP04_ADDY_PTR_M
.390f10		a9 14		lda #$14	                LDA #$14
.390f12		8f 2a 0c af	sta $af0c2a	                STA SP05_ADDY_PTR_M
.390f16		a9 18		lda #$18	                LDA #$18
.390f18		8f 32 0c af	sta $af0c32	                STA SP06_ADDY_PTR_M
.390f1c		a9 1c		lda #$1c	                LDA #$1C
.390f1e		8f 3a 0c af	sta $af0c3a	                STA SP07_ADDY_PTR_M
.390f22		a9 20		lda #$20	                LDA #$20
.390f24		8f 42 0c af	sta $af0c42	                STA SP08_ADDY_PTR_M
.390f28		a9 24		lda #$24	                LDA #$24
.390f2a		8f 4a 0c af	sta $af0c4a	                STA SP09_ADDY_PTR_M
.390f2e		a9 28		lda #$28	                LDA #$28
.390f30		8f 52 0c af	sta $af0c52	                STA SP10_ADDY_PTR_M
.390f34		a9 2c		lda #$2c	                LDA #$2C
.390f36		8f 5a 0c af	sta $af0c5a	                STA SP11_ADDY_PTR_M
.390f3a		a9 30		lda #$30	                LDA #$30
.390f3c		8f 62 0c af	sta $af0c62	                STA SP12_ADDY_PTR_M
.390f40		a9 34		lda #$34	                LDA #$34
.390f42		8f 6a 0c af	sta $af0c6a	                STA SP13_ADDY_PTR_M
.390f46		a9 38		lda #$38	                LDA #$38
.390f48		8f 72 0c af	sta $af0c72	                STA SP14_ADDY_PTR_M
.390f4c		a9 3c		lda #$3c	                LDA #$3C
.390f4e		8f 7a 0c af	sta $af0c7a	                STA SP15_ADDY_PTR_M
.390f52		a9 40		lda #$40	                LDA #$40
.390f54		8f 82 0c af	sta $af0c82	                STA SP16_ADDY_PTR_M
.390f58		a9 00		lda #$00	                LDA #$00
.390f5a		8f 01 0c af	sta $af0c01	                STA SP00_ADDY_PTR_L
.390f5e		8f 09 0c af	sta $af0c09	                STA SP01_ADDY_PTR_L
.390f62		8f 11 0c af	sta $af0c11	                STA SP02_ADDY_PTR_L
.390f66		8f 19 0c af	sta $af0c19	                STA SP03_ADDY_PTR_L
.390f6a		8f 21 0c af	sta $af0c21	                STA SP04_ADDY_PTR_L
.390f6e		8f 29 0c af	sta $af0c29	                STA SP05_ADDY_PTR_L
.390f72		8f 31 0c af	sta $af0c31	                STA SP06_ADDY_PTR_L
.390f76		8f 39 0c af	sta $af0c39	                STA SP07_ADDY_PTR_L
.390f7a		8f 41 0c af	sta $af0c41	                STA SP08_ADDY_PTR_L
.390f7e		8f 49 0c af	sta $af0c49	                STA SP09_ADDY_PTR_L
.390f82		8f 51 0c af	sta $af0c51	                STA SP10_ADDY_PTR_L
.390f86		8f 59 0c af	sta $af0c59	                STA SP11_ADDY_PTR_L
.390f8a		8f 61 0c af	sta $af0c61	                STA SP12_ADDY_PTR_L
.390f8e		8f 69 0c af	sta $af0c69	                STA SP13_ADDY_PTR_L
.390f92		8f 71 0c af	sta $af0c71	                STA SP14_ADDY_PTR_L
.390f96		8f 79 0c af	sta $af0c79	                STA SP15_ADDY_PTR_L
.390f9a		8f 81 0c af	sta $af0c81	                STA SP16_ADDY_PTR_L
.390f9e		68		pla		                PLA
.390f9f		6b		rtl		                RTL
.390fa0						IINITFONTSET
.390fa0		48		pha		                PHA
.390fa1		da		phx		                PHX
.390fa2		5a		phy		                PHY
.390fa3		8b		phb		                PHB
.390fa4		08		php		                PHP
.390fa5		c2 30		rep #$30	                REP #$30        ; set A&X long
.390fa7		a2 00 f0	ldx #$f000	                LDX #<>FONT_4_BANK0         ; Font data to load
.390faa		a0 00 80	ldy #$8000	                LDY #<>FONT_MEMORY_BANK0    ; Location to load the font data
.390fad		a9 00 08	lda #$0800	                LDA #8 * 256                ; Size of a FONT in bytes
.390fb0		54 af 3f	mvn $3f,$af	                MVN #`FONT_4_BANK0, #`FONT_MEMORY_BANK0
.390fb3		28		plp		                PLP
.390fb4		ab		plb		                PLB
.390fb5		7a		ply		                PLY
.390fb6		fa		plx		                PLX
.390fb7		68		pla		                PLA
.390fb8		6b		rtl		                RTL
.390fb9						INITMOUSEPOINTER
.390fb9		e2 20		sep #$20	                SEP #$20        ; set A short
.390fbb		c2 10		rep #$10	                REP #$10        ; set X long
.390fbd		a2 00 00	ldx #$0000	                LDX #$0000
.390fc0						FILL_MOUSE_MARKER
.390fc0		bf 00 79 39	lda $397900,x	                LDA @lMOUSE_POINTER_PTR,X
.390fc4		9f 00 05 af	sta $af0500,x	                STA @lMOUSE_PTR_GRAP0_START, X
.390fc8		e8		inx		                INX
.390fc9		e0 00 01	cpx #$0100	                CPX #$0100
.390fcc		d0 f2		bne $390fc0	                BNE FILL_MOUSE_MARKER
.390fce		ea		nop		                nop
.390fcf		a9 01		lda #$01	                LDA #$01
.390fd1		8f 00 07 af	sta $af0700	                STA @lMOUSE_PTR_CTRL_REG_L  ; Enable Mouse, Mouse Pointer Graphic Bank 0
.390fd5		c2 30		rep #$30	                REP #$30        ; set A&X long
.390fd7		6b		rtl		                RTL
.390fd8		48		pha		IINITCURSOR     PHA
.390fd9		e2 20		sep #$20	                SEP #$20        ; set A short
.390fdb		a9 b1		lda #$b1	                LDA #$B1      ;The Cursor Character will be a Fully Filled Block
.390fdd		8f 12 00 af	sta $af0012	                STA VKY_TXT_CURSOR_CHAR_REG
.390fe1		a9 03		lda #$03	                LDA #$03      ;Set Cursor Enable And Flash Rate @1Hz
.390fe3		8f 10 00 af	sta $af0010	                STA VKY_TXT_CURSOR_CTRL_REG ;
.390fe7		c2 30		rep #$30	                REP #$30        ; set A&X long
.390fe9		a9 00 00	lda #$0000	                LDA #$0000;
.390fec		8f 14 00 af	sta $af0014	                STA VKY_TXT_CURSOR_X_REG_L; // Set the X to Position 1
.390ff0		a9 06 00	lda #$0006	                LDA #$0006;
.390ff3		8f 16 00 af	sta $af0016	                STA VKY_TXT_CURSOR_Y_REG_L; // Set the Y to Position 6 (Below)
.390ff7		68		pla		                PLA
.390ff8		6b		rtl		                RTL
.390ff9		0b		phd		IINITSUPERIO	  PHD
.390ffa		08		php		                PHP
.390ffb		48		pha		                PHA
.390ffc		e2 20		sep #$20	                SEP #$20        ; set A short
.390ffe		a9 01		lda #$01	                LDA #$01		;Default Value - C256 Doesn't use this IO Pin
.391000		8f 23 11 af	sta $af1123	                STA GP10_REG
.391004		af 23 11 af	lda $af1123	                LDA GP10_REG
.391008		a9 01		lda #$01	                LDA #$01		;Default Value - C256 Doesn't use this IO Pin
.39100a		8f 24 11 af	sta $af1124	                STA GP11_REG
.39100e		a9 01		lda #$01	                LDA #$01		;Default Value - C256 Doesn't use this IO Pin
.391010		8f 25 11 af	sta $af1125	                STA GP12_REG
.391014		a9 01		lda #$01	        				LDA #$01		;Default Value - C256 Doesn't use this IO Pin
.391016		8f 26 11 af	sta $af1126	        				STA GP13_REG
.39101a		a9 05		lda #$05	        				LDA #$05		;(C256 - POT A Analog BX) Bit[0] = 1, Bit[2] = 1
.39101c		8f 27 11 af	sta $af1127	        				STA GP14_REG
.391020		a9 05		lda #$05	        				LDA #$05		;(C256 - POT A Analog BY) Bit[0] = 1, Bit[2] = 1
.391022		8f 28 11 af	sta $af1128	        				STA GP15_REG
.391026		a9 05		lda #$05	        				LDA #$05		;(C256 - POT B Analog BX) Bit[0] = 1, Bit[2] = 1
.391028		8f 29 11 af	sta $af1129	        				STA GP16_REG
.39102c		a9 05		lda #$05	        				LDA #$05		;(C256 - POT B Analog BY) Bit[0] = 1, Bit[2] = 1
.39102e		8f 2a 11 af	sta $af112a	        				STA GP17_REG
.391032		a9 00		lda #$00	        				LDA #$00		;(C256 - HEADPHONE MUTE) - Output GPIO - Push-Pull (1 - Headphone On, 0 - HeadPhone Off)
.391034		8f 2b 11 af	sta $af112b	        				STA GP20_REG
.391038		a9 01		lda #$01					        LDA #$01		;Default Value - C256 Doesn't use this IO Pin
.39103a		8f 2f 11 af	sta $af112f					        STA GP24_REG
.39103e		a9 05		lda #$05					        LDA #$05		;(C256 - MIDI IN) Bit[0] = 1, Bit[2] = 1 (Page 132 Manual)
.391040		8f 30 11 af	sta $af1130					        STA GP25_REG
.391044		a9 84		lda #$84				        	LDA #$84		;(C256 - MIDI OUT) Bit[2] = 1, Bit[7] = 1 (Open Drain - To be Checked)
.391046		8f 31 11 af	sta $af1131					        STA GP26_REG
.39104a		a9 01		lda #$01					        LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 1) Setup as GPIO Input for now
.39104c		8f 33 11 af	sta $af1133					        STA GP30_REG
.391050		a9 01		lda #$01					        LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 4) Setup as GPIO Input for now
.391052		8f 34 11 af	sta $af1134					        STA GP31_REG
.391056		a9 01		lda #$01					        LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 3) Setup as GPIO Input for now
.391058		8f 35 11 af	sta $af1135					        STA GP32_REG
.39105c		a9 01		lda #$01					        LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 6) Setup as GPIO Input for now
.39105e		8f 36 11 af	sta $af1136					        STA GP33_REG
.391062		a9 01		lda #$01					        LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 5) Setup as GPIO Input for now
.391064		8f 37 11 af	sta $af1137					        STA GP34_REG
.391068		a9 01		lda #$01					        LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 8) Setup as GPIO Input for now
.39106a		8f 38 11 af	sta $af1138					        STA GP35_REG
.39106e		a9 01		lda #$01					        LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 7) Setup as GPIO Input for now
.391070		8f 39 11 af	sta $af1139					        STA GP36_REG
.391074		a9 01		lda #$01					        LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 10) Setup as GPIO Input for now
.391076		8f 3a 11 af	sta $af113a					        STA GP37_REG
.39107a		a9 01		lda #$01					        LDA #$01		;Default Value - C256 Doesn't use this IO Pin
.39107c		8f 3d 11 af	sta $af113d					        STA GP42_REG
.391080		a9 01		lda #$01				          LDA #$01		;(C256 - INPUT PLL CLK INTERRUPT) Default Value - Will keep it as an input for now, no real usage for now
.391082		8f 3e 11 af	sta $af113e					        STA GP43_REG
.391086		a9 05		lda #$05					        LDA #$05		;(C256 - UART2 - RI2) - Input - Set Secondary Function
.391088		8f 3f 11 af	sta $af113f					        STA GP50_REG
.39108c		a9 05		lda #$05					        LDA #$05		;(C256 - UART2 - DCD2) - Input - Set Secondary Function
.39108e		8f 40 11 af	sta $af1140					        STA GP51_REG
.391092		a9 05		lda #$05					        LDA #$05		;(C256 - UART2 - RXD2) - Input - Set Secondary Function
.391094		8f 41 11 af	sta $af1141					        STA GP52_REG
.391098		a9 04		lda #$04					        LDA #$04		;(C256 - UART2 - TXD2) - Output - Set Secondary Function
.39109a		8f 42 11 af	sta $af1142					        STA GP53_REG
.39109e		a9 05		lda #$05					        LDA #$05		;(C256 - UART2 - DSR2) - Input - Set Secondary Function
.3910a0		8f 43 11 af	sta $af1143					        STA GP54_REG
.3910a4		a9 04		lda #$04					        LDA #$04		;(C256 - UART2 - RTS2) - Output - Set Secondary Function
.3910a6		8f 44 11 af	sta $af1144					        STA GP55_REG
.3910aa		a9 05		lda #$05					        LDA #$05		;(C256 - UART2 - CTS2) - Input - Set Secondary Function
.3910ac		8f 45 11 af	sta $af1145					        STA GP56_REG
.3910b0		a9 04		lda #$04					        LDA #$04		;(C256 - UART2 - DTR2) - Output - Set Secondary Function
.3910b2		8f 46 11 af	sta $af1146					        STA GP57_REG
.3910b6		a9 84		lda #$84					        LDA #$84		;(C256 - LED1) - Open Drain - Output
.3910b8		8f 47 11 af	sta $af1147					        STA GP60_REG
.3910bc		a9 84		lda #$84					        LDA #$84		;(C256 - LED2) - Open Drain - Output
.3910be		8f 48 11 af	sta $af1148					        STA GP61_REG
.3910c2		a9 00		lda #$00				        	LDA #$00		;GPIO Data Register (GP10..GP17) - Not Used
.3910c4		8f 4b 11 af	sta $af114b					        STA GP1_REG
.3910c8		a9 01		lda #$01					        LDA #$01		;GPIO Data Register (GP20..GP27) - Bit[0] - Headphone Mute (Enabling it)
.3910ca		8f 4c 11 af	sta $af114c					        STA GP2_REG
.3910ce		a9 00		lda #$00					        LDA #$00		;GPIO Data Register (GP30..GP37) - Since it is in Output mode, nothing to write here.
.3910d0		8f 4d 11 af	sta $af114d					        STA GP3_REG
.3910d4		a9 00		lda #$00					        LDA #$00		;GPIO Data Register (GP40..GP47)  - Not Used
.3910d6		8f 4e 11 af	sta $af114e					        STA GP4_REG
.3910da		a9 00		lda #$00					        LDA #$00		;GPIO Data Register (GP50..GP57)  - Not Used
.3910dc		8f 4f 11 af	sta $af114f					        STA GP5_REG
.3910e0		a9 00		lda #$00					        LDA #$00		;GPIO Data Register (GP60..GP61)  - Not Used
.3910e2		8f 50 11 af	sta $af1150					        STA GP6_REG
.3910e6		a9 01		lda #$01					        LDA #$01		;LED1 Output - Already setup by Vicky Init Phase, for now, I will leave it alone
.3910e8		8f 5d 11 af	sta $af115d					        STA LED1_REG
.3910ec		a9 02		lda #$02					        LDA #$02		;LED2 Output - However, I will setup this one, to make sure the Code works (Full On, when Code was ran)
.3910ee		8f 5e 11 af	sta $af115e					        STA LED2_REG
.3910f2		c2 20		rep #$20	                REP #$20        ; set A long
.3910f4		68		pla		                PLA
.3910f5		28		plp						        PLP
.3910f6		2b		pld					        	PLD
.3910f7		6b		rtl		                RTL
.3910f8		0b		phd		IINITKEYBOARD	  PHD
.3910f9		08		php						        PHP
.3910fa		48		pha						        PHA
.3910fb		da		phx						        PHX
.3910fc		e2 20		sep #$20	                SEP #$20        ; set A short
.3910fe		c2 10		rep #$10	                REP #$10        ; set X long
.391100		18		clc		                CLC
.391101		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf ;
.391104		a9 aa		lda #$aa					        LDA #$AA			;Send self test command
.391106		8f 64 10 af	sta $af1064					        STA KBD_CMD_BUF
.39110a		20 bc 11	jsr $3911bc	                JSR Poll_Outbuf ;
.39110d		af 60 10 af	lda $af1060					        LDA KBD_OUT_BUF		;Check self test result
.391111		c9 55		cmp #$55					        CMP #$55
.391113		f0 03		beq $391118					        BEQ	passAAtest
.391115		82 89 00	brl $3911a1	                BRL initkb_loop_out
.391118						passAAtest
.391118		a9 ab		lda #$ab					        LDA #$AB			;Send test Interface command
.39111a		8f 64 10 af	sta $af1064					        STA KBD_CMD_BUF
.39111e		20 bc 11	jsr $3911bc	                JSR Poll_Outbuf ;
.391121		af 60 10 af	lda $af1060					        LDA KBD_OUT_BUF		;Display Interface test results
.391125		c9 00		cmp #$00					        CMP #$00			;Should be 00
.391127		f0 03		beq $39112c					        BEQ	passABtest
.391129		82 75 00	brl $3911a1	                BRL initkb_loop_out
.39112c						passABtest
.39112c		a9 60		lda #$60	                LDA #$60            ; Send Command 0x60 so to Enable Interrupt
.39112e		8f 64 10 af	sta $af1064	                STA KBD_CMD_BUF
.391132		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf ;
.391135		a9 69		lda #$69	                LDA #%01101001      ; Enable Interrupt
.391137		8f 60 10 af	sta $af1060	                STA KBD_DATA_BUF
.39113b		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf ;
.39113e		a9 ff		lda #$ff	                LDA #$FF      ; Send Keyboard Reset command
.391140		8f 60 10 af	sta $af1060	                STA KBD_DATA_BUF
.391144		a2 ff ff	ldx #$ffff	                LDX #$FFFF
.391147		ca		dex		DLY_LOOP1       DEX
.391148		ea		nop		                NOP
.391149		ea		nop		                NOP
.39114a		ea		nop		                NOP
.39114b		ea		nop		                NOP
.39114c		ea		nop		                NOP
.39114d		ea		nop		                NOP
.39114e		ea		nop		                NOP
.39114f		ea		nop		                NOP
.391150		e0 00 00	cpx #$0000	                CPX #$0000
.391153		d0 f2		bne $391147	                BNE DLY_LOOP1
.391155		20 bc 11	jsr $3911bc	                JSR Poll_Outbuf ;
.391158		af 60 10 af	lda $af1060	                LDA KBD_OUT_BUF   ; Read Output Buffer
.39115c						DO_CMD_F4_AGAIN
.39115c		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf ;
.39115f		a9 f4		lda #$f4					        LDA #$F4			; Enable the Keyboard
.391161		8f 60 10 af	sta $af1060					        STA KBD_DATA_BUF
.391165		20 bc 11	jsr $3911bc	                JSR Poll_Outbuf ;
.391168		af 60 10 af	lda $af1060					        LDA KBD_OUT_BUF		; Clear the Output buffer
.39116c		c9 fa		cmp #$fa	                CMP #$FA
.39116e		d0 ec		bne $39115c	                BNE DO_CMD_F4_AGAIN
.391170		20 c7 11	jsr $3911c7	                JSR INIT_MOUSE
.391173		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0  ; Read the Pending Register &
.391177		29 80		and #$80	                AND #FNX0_INT07_MOUSE
.391179		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0  ; Writing it back will clear the Active Bit
.39117d		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1  ; Read the Pending Register &
.391181		29 01		and #$01	                AND #FNX1_INT00_KBD
.391183		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1  ; Writing it back will clear the Active Bit
.391187		af 4d 01 00	lda $00014d	                LDA @lINT_MASK_REG1
.39118b		29 fe		and #$fe	                AND #~FNX1_INT00_KBD
.39118d		8f 4d 01 00	sta $00014d	                STA @lINT_MASK_REG1
.391191		af 4c 01 00	lda $00014c	                LDA @lINT_MASK_REG0
.391195		29 7f		and #$7f	                AND #~FNX0_INT07_MOUSE
.391197		8f 4c 01 00	sta $00014c	                STA @lINT_MASK_REG0
.39119b		a2 26 71	ldx #$7126	                LDX #<>Success_kb_init
.39119e		38		sec		                SEC
.39119f		b0 03		bcs $3911a4	                BCS InitSuccess
.3911a1		a2 38 71	ldx #$7138	initkb_loop_out LDX #<>Failed_kb_init
.3911a4		22 7e 07 39	jsl $39077e	InitSuccess     JSL IPRINT       ; print Message
.3911a8		c2 20		rep #$20	                REP #$20        ; set A long
.3911aa		c2 10		rep #$10	                REP #$10        ; set X long
.3911ac		fa		plx		                PLX
.3911ad		68		pla		                PLA
.3911ae		28		plp						        PLP
.3911af		2b		pld						        PLD
.3911b0		6b		rtl		                RTL
.3911b1						Poll_Inbuf
.3911b1		af 64 10 af	lda $af1064	                LDA STATUS_PORT		; Load Status Byte
.3911b5		29 02		and #$02					        AND	#<INPT_BUF_FULL	; Test bit $02 (if 0, Empty)
.3911b7		c9 02		cmp #$02					        CMP #<INPT_BUF_FULL
.3911b9		f0 f6		beq $3911b1					        BEQ Poll_Inbuf
.3911bb		60		rts		                RTS
.3911bc						Poll_Outbuf
.3911bc		af 64 10 af	lda $af1064	                LDA STATUS_PORT
.3911c0		29 01		and #$01	                AND #OUT_BUF_FULL ; Test bit $01 (if 1, Full)
.3911c2		c9 01		cmp #$01	                CMP #OUT_BUF_FULL
.3911c4		d0 f6		bne $3911bc	                BNE Poll_Outbuf
.3911c6		60		rts		                RTS
.3911c7						INIT_MOUSE
.3911c7		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf
.3911ca		a9 a8		lda #$a8	                LDA #$A8          ; Enable the second PS2 Channel
.3911cc		8f 64 10 af	sta $af1064	                STA KBD_CMD_BUF
.3911d0						DO_CMD_A9_AGAIN
.3911d0		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf
.3911d3		a9 a9		lda #$a9	                LDA #$A9          ; Tests second PS2 Channel
.3911d5		8f 64 10 af	sta $af1064	                STA KBD_CMD_BUF
.3911d9		20 bc 11	jsr $3911bc	                JSR Poll_Outbuf ;
.3911dc		af 60 10 af	lda $af1060					        LDA KBD_OUT_BUF		; Clear the Output buffer
.3911e0		c9 00		cmp #$00	                CMP #$00
.3911e2		d0 ec		bne $3911d0	                BNE DO_CMD_A9_AGAIN
.3911e4		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf
.3911e7		a9 20		lda #$20	                LDA #$20
.3911e9		8f 64 10 af	sta $af1064	                STA KBD_CMD_BUF
.3911ed		20 bc 11	jsr $3911bc	                JSR Poll_Outbuf ;
.3911f0		af 60 10 af	lda $af1060	                LDA KBD_OUT_BUF
.3911f4		09 02		ora #$02	                ORA #$02
.3911f6		48		pha		                PHA
.3911f7		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf
.3911fa		a9 60		lda #$60	                LDA #$60
.3911fc		8f 64 10 af	sta $af1064	                STA KBD_CMD_BUF
.391200		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf ;
.391203		68		pla		                PLA
.391204		8f 60 10 af	sta $af1060	                STA KBD_DATA_BUF
.391208		a9 f6		lda #$f6	                LDA #$F6        ;Tell the mouse to use default settings
.39120a		20 2d 12	jsr $39122d	                JSR MOUSE_WRITE
.39120d		20 40 12	jsr $391240	                JSR MOUSE_READ
.391210		a9 e8		lda #$e8	                LDA #$E8
.391212		20 2d 12	jsr $39122d	                JSR MOUSE_WRITE
.391215		20 40 12	jsr $391240	                JSR MOUSE_READ
.391218		a9 00		lda #$00	                LDA #$00
.39121a		20 2d 12	jsr $39122d	                JSR MOUSE_WRITE
.39121d		20 40 12	jsr $391240	                JSR MOUSE_READ
.391220		a9 f4		lda #$f4	                LDA #$F4        ; Enable the Mouse
.391222		20 2d 12	jsr $39122d	                JSR MOUSE_WRITE
.391225		20 40 12	jsr $391240	                JSR MOUSE_READ
.391228		a9 00		lda #$00	                LDA #$00
.39122a		85 e0		sta $e0		                STA MOUSE_PTR
.39122c		60		rts		                RTS
.39122d						MOUSE_WRITE
.39122d		48		pha		                PHA
.39122e		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf
.391231		a9 d4		lda #$d4	                LDA #$D4
.391233		8f 64 10 af	sta $af1064	                STA KBD_CMD_BUF
.391237		20 b1 11	jsr $3911b1	                JSR Poll_Inbuf
.39123a		68		pla		                PLA
.39123b		8f 60 10 af	sta $af1060	                STA KBD_DATA_BUF
.39123f		60		rts		                RTS
.391240						MOUSE_READ
.391240		20 bc 11	jsr $3911bc	                JSR Poll_Outbuf ;
.391243		af 60 10 af	lda $af1060	                LDA KBD_INPT_BUF
.391247		60		rts		                RTS
.391248		48		pha		INITRTC         PHA
.391249		08		php		                PHP
.39124a		e2 20		sep #$20	                SEP #$20        ; set A short
.39124c		a9 00		lda #$00	                LDA #0
.39124e		8f 0b 08 af	sta $af080b	                STA @l RTC_RATES    ; Set watch dog timer and periodic interrupt rates to 0
.391252		8f 0c 08 af	sta $af080c	                STA @l RTC_ENABLE   ; Disable all the alarms and interrupts
.391256		af 0e 08 af	lda $af080e	                LDA @lRTC_CTRL      ; Make sure the RTC will continue to tick in battery mode
.39125a		09 04		ora #$04	                ORA #%00000100
.39125c		8f 0e 08 af	sta $af080e	                STA @lRTC_CTRL
.391260		28		plp		                PLP
.391261		68		pla		                PLA
.391262		6b		rtl		                RTL
.391263						ITESTSID
.391263		a9 0f		lda #$0f	                LDA #$0F
.391265		8f 18 e4 af	sta $afe418	                STA SID0_MODE_VOL
.391269		a9 be		lda #$be	                LDA #$BE
.39126b		8f 05 e4 af	sta $afe405	                STA SID0_V1_ATCK_DECY
.39126f		a9 f8		lda #$f8	                LDA #$F8
.391271		8f 06 e4 af	sta $afe406	                STA SID0_V1_SSTN_RLSE
.391275		a9 11		lda #$11	                LDA #$11
.391277		8f 01 e4 af	sta $afe401	                STA SID0_V1_FREQ_HI
.39127b		a9 25		lda #$25	                LDA #$25
.39127d		8f 00 e4 af	sta $afe400	                STA SID0_V1_FREQ_LO
.391281		a9 11		lda #$11	                LDA #$11
.391283		8f 04 e4 af	sta $afe404	                STA SID0_V1_CTRL
.391287		a9 08		lda #$08	                LDA #$08
.391289		8f 03 e4 af	sta $afe403	                STA SID0_V1_PW_HI   ;G1
.39128d		a9 00		lda #$00	                LDA #$00
.39128f		8f 01 e4 af	sta $afe401	                STA SID0_V1_FREQ_HI
.391293		a9 c6		lda #$c6	                LDA #$C6
.391295		8f 06 e4 af	sta $afe406	                STA SID0_V1_SSTN_RLSE
.391299		a9 08		lda #$08	                LDA #$08
.39129b		8f 0a e4 af	sta $afe40a	                STA SID0_V2_PW_HI   ;G1
.39129f		a9 00		lda #$00	                LDA #$00
.3912a1		8f 08 e4 af	sta $afe408	                STA SID0_V2_FREQ_HI
.3912a5		a9 08		lda #$08	                LDA #$08
.3912a7		8f 0c e4 af	sta $afe40c	                STA SID0_V2_ATCK_DECY
.3912ab		a9 c6		lda #$c6	                LDA #$C6
.3912ad		8f 0d e4 af	sta $afe40d	                STA SID0_V2_SSTN_RLSE
.3912b1		a9 08		lda #$08	                LDA #$08
.3912b3		8f 11 e4 af	sta $afe411	                STA SID0_V3_PW_HI   ;G1
.3912b7		a9 00		lda #$00	                LDA #$00
.3912b9		8f 0f e4 af	sta $afe40f	                STA SID0_V3_FREQ_HI
.3912bd		a9 08		lda #$08	                LDA #$08
.3912bf		8f 13 e4 af	sta $afe413	                STA SID0_V3_ATCK_DECY
.3912c3		a9 c6		lda #$c6	                LDA #$C6
.3912c5		8f 14 e4 af	sta $afe414	                STA SID0_V3_SSTN_RLSE
.3912c9		a9 36		lda #$36	                LDA #$36              ;Left Side (Rev A of Board)
.3912cb		8f 00 e4 af	sta $afe400	                STA SID0_V1_FREQ_LO
.3912cf		a9 01		lda #$01	                LDA #$01
.3912d1		8f 01 e4 af	sta $afe401	                STA SID0_V1_FREQ_HI   ;G1
.3912d5		a9 00		lda #$00	                LDA #$00              ;Left Side (Rev A of Board)
.3912d7		8f 02 e4 af	sta $afe402	                STA SID0_V1_PW_LO
.3912db		a9 08		lda #$08	                LDA #$08
.3912dd		8f 03 e4 af	sta $afe403	                STA SID0_V1_PW_HI   ;G1
.3912e1		a9 08		lda #$08	                LDA #$08
.3912e3		8f 04 e4 af	sta $afe404	                STA SID0_V1_CTRL    ; Reset
.3912e7		a9 0c		lda #$0c	                LDA #$0C
.3912e9		8f 07 e4 af	sta $afe407	                STA SID0_V2_FREQ_LO
.3912ed		a9 04		lda #$04	                LDA #$04
.3912ef		8f 08 e4 af	sta $afe408	                STA SID0_V2_FREQ_HI   ;B1
.3912f3		a9 00		lda #$00	                LDA #$00              ;Left Side (Rev A of Board)
.3912f5		8f 09 e4 af	sta $afe409	                STA SID0_V2_PW_LO
.3912f9		a9 08		lda #$08	                LDA #$08
.3912fb		8f 0a e4 af	sta $afe40a	                STA SID0_V2_PW_HI   ;G1
.3912ff		a9 08		lda #$08	                LDA #$08
.391301		8f 0b e4 af	sta $afe40b	                STA SID0_V2_CTRL    ; Reset
.391305		a9 00		lda #$00	                LDA #$00
.391307		8f 0e e4 af	sta $afe40e	                STA SID0_V3_FREQ_LO
.39130b		a9 08		lda #$08	                LDA #$08
.39130d		8f 0f e4 af	sta $afe40f	                STA SID0_V3_FREQ_HI   ;D
.391311		a9 00		lda #$00	                LDA #$00              ;Left Side (Rev A of Board)
.391313		8f 10 e4 af	sta $afe410	                STA SID0_V3_PW_LO
.391317		a9 08		lda #$08	                LDA #$08
.391319		8f 11 e4 af	sta $afe411	                STA SID0_V3_PW_HI   ;G1
.39131d		a9 08		lda #$08	                LDA #$08
.39131f		8f 12 e4 af	sta $afe412	                STA SID0_V3_CTRL    ; Reset
.391323		a9 10		lda #$10	                LDA #$10
.391325		8f 04 e4 af	sta $afe404	                STA SID0_V1_CTRL    ; Triangle
.391329		8f 0b e4 af	sta $afe40b	                STA SID0_V2_CTRL    ; Triangle
.39132d		8f 12 e4 af	sta $afe412	                STA SID0_V3_CTRL    ; Triangle
.391331		6b		rtl		                RTL
.391332		48		pha		IINITCODEC      PHA
.391333		c2 20		rep #$20	                REP #$20        ; set A long
.391335		a9 00 1a	lda #$1a00	                LDA #%0001101000000000     ;R13 - Turn On Headphones
.391338		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
.39133c		a9 01 00	lda #$0001	                LDA #$0001
.39133f		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
.391343		20 c2 13	jsr $3913c2	                JSR CODEC_TRF_FINISHED
.391346		a9 0f 2a	lda #$2a0f	                LDA #%0010101000001111       ;R21 - Enable All the Analog In
.391349		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
.39134d		a9 01 00	lda #$0001	                LDA #$0001
.391350		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
.391354		20 c2 13	jsr $3913c2	                JSR CODEC_TRF_FINISHED
.391357		a9 01 23	lda #$2301	                LDA #%0010001100000001      ;R17 - Enable All the Analog In
.39135a		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
.39135e		a9 01 00	lda #$0001	                LDA #$0001
.391361		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
.391365		20 c2 13	jsr $3913c2	                JSR CODEC_TRF_FINISHED
.391368		a9 07 2c	lda #$2c07	                LDA #%0010110000000111      ;R22 - Enable all Analog Out
.39136b		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
.39136f		a9 01 00	lda #$0001	                LDA #$0001
.391372		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
.391376		20 c2 13	jsr $3913c2	                JSR CODEC_TRF_FINISHED
.391379		a9 02 14	lda #$1402	                LDA #%0001010000000010      ;R10 - DAC Interface Control
.39137c		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
.391380		a9 01 00	lda #$0001	                LDA #$0001
.391383		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
.391387		20 c2 13	jsr $3913c2	                JSR CODEC_TRF_FINISHED
.39138a		a9 02 16	lda #$1602	                LDA #%0001011000000010      ;R11 - ADC Interface Control
.39138d		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
.391391		a9 01 00	lda #$0001	                LDA #$0001
.391394		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
.391398		20 c2 13	jsr $3913c2	                JSR CODEC_TRF_FINISHED
.39139b		a9 d5 19	lda #$19d5	                LDA #%0001100111010101      ;R12 - Master Mode Control
.39139e		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
.3913a2		a9 01 00	lda #$0001	                LDA #$0001
.3913a5		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
.3913a9		20 c2 13	jsr $3913c2	                JSR CODEC_TRF_FINISHED
.3913ac		68		pla		                PLA
.3913ad		6b		rtl		                RTL
.3913ae						IRESETCODEC
.3913ae		c2 20		rep #$20	                REP #$20        ; set A long
.3913b0		a9 00 2e	lda #$2e00	                LDA #$2E00      ;R22 - Enable all Analog Out
.3913b3		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
.3913b7		a9 01 00	lda #$0001	                LDA #$0001
.3913ba		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
.3913be		20 c2 13	jsr $3913c2	                JSR CODEC_TRF_FINISHED
.3913c1		6b		rtl		                RTL
.3913c2						CODEC_TRF_FINISHED
.3913c2		e2 20		sep #$20	                SEP #$20        ; set A short
.3913c4		af 02 e9 af	lda $afe902	CODEC_LOOP      LDA CODEC_WR_CTRL
.3913c8		29 01		and #$01	                AND #$01
.3913ca		c9 01		cmp #$01	                CMP #$01
.3913cc		f0 f6		beq $3913c4	                BEQ CODEC_LOOP
.3913ce		c2 20		rep #$20	                REP #$20        ; set A long
.3913d0		60		rts		                RTS
.3913d1						IBM_FILL_SCREEN
.3913d1		c2 30		rep #$30	                REP #$30        ; set A&X long
.3913d3		a9 00 00	lda #$0000	                LDA #$0000
.3913d6		a2 00 00	ldx #$0000	                LDX #$0000
.3913d9						BM_FILL_SCREEN_LOOPY
.3913d9		a0 00 00	ldy #$0000	                LDY #$0000
.3913dc		e2 20		sep #$20	                SEP #$20        ; set A short
.3913de						BM_FILL_SCREEN_LOOPX
.3913de		97 48		sta [$48],y	                STA [BMP_PRSE_DST_PTR],Y    ; This is where the Pixel Go, Video Memory
.3913e0		c8		iny		                INY
.3913e1		c4 40		cpy $40		                CPY BM_CLEAR_SCRN_X              ; Transfer the First line
.3913e3		d0 f9		bne $3913de	                BNE BM_FILL_SCREEN_LOOPX
.3913e5		20 f0 13	jsr $3913f0	                JSR BM_FILL_COMPUTE_Y_DST
.3913e8		e8		inx		                INX
.3913e9		e4 42		cpx $42		                CPX BM_CLEAR_SCRN_Y
.3913eb		d0 ec		bne $3913d9	                BNE BM_FILL_SCREEN_LOOPY
.3913ed		c2 30		rep #$30	                REP #$30        ; set A&X long
.3913ef		6b		rtl		                RTL
.3913f0						BM_FILL_COMPUTE_Y_DST
.3913f0		c2 20		rep #$20	                REP #$20        ; set A long
.3913f2		a5 48		lda $48		                LDA BMP_PRSE_DST_PTR        ; Right now it is set @ $020000 (128K) + File Size
.3913f4		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL
.3913f8		a5 4a		lda $4a		                LDA BMP_PRSE_DST_PTR+2      ; Right now it is set @ $020000 (128K)
.3913fa		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL
.3913fe		a9 80 02	lda #$0280	                LDA #$280        ; Right now it is set @ $020000 (128K) + File Size
.391401		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL
.391405		a9 00 00	lda #$0000	                LDA #$0000
.391408		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL
.39140c		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
.391410		85 48		sta $48		                STA BMP_PRSE_DST_PTR
.391412		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
.391416		85 4a		sta $4a		                STA BMP_PRSE_DST_PTR+2
.391418		a9 00 00	lda #$0000	                LDA #$0000
.39141b		60		rts		                RTS
.39141c						IBMP_PARSER
.39141c		c2 30		rep #$30	                REP #$30        ; set A&X long
.39141e		a0 00 00	ldy #$0000	                LDY #$0000
.391421		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y
.391423		c9 42 4d	cmp #$4d42	                CMP #$4D42
.391426		f0 03		beq $39142b	                BEQ IBMP_PARSER_CONT
.391428		82 04 01	brl $39152f	                BRL BMP_PARSER_END_WITH_ERROR
.39142b						IBMP_PARSER_CONT
.39142b		a0 02 00	ldy #$0002	                LDY #$0002
.39142e		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; File Size Low Short
.391430		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL          ; Store in 32Bit Adder (A)
.391434		a0 04 00	ldy #$0004	                LDY #$0004
.391437		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; File Size High Short
.391439		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL          ; Store in 32Bit Adder (A)
.39143d		a9 ff ff	lda #$ffff	                LDA #$FFFF                  ; Store -1 in Adder (B)
.391440		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL
.391444		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL
.391448		18		clc		                CLC
.391449		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
.39144d		85 50		sta $50		                STA BMP_FILE_SIZE
.39144f		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
.391453		85 52		sta $52		                STA BMP_FILE_SIZE+2
.391455		a0 12 00	ldy #$0012	                LDY #$0012
.391458		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; The X SIze is 32bits in BMP, but 16bits will suffice
.39145a		85 40		sta $40		                STA BMP_X_SIZE
.39145c		a0 16 00	ldy #$0016	                LDY #$0016
.39145f		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; The X SIze is 32bits in BMP, but 16bits will suffice
.391461		85 42		sta $42		                STA BMP_Y_SIZE
.391463		a0 2e 00	ldy #$002e	                LDY #$002E
.391466		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; The X SIze is 32bits in BMP, but 16bits will suffice
.391468		0a		asl a		                ASL A; Multiply by 2
.391469		0a		asl a		                ASL A; Multiply by 2
.39146a		85 4c		sta $4c		                STA BMP_COLOR_PALET         ;
.39146c		e0 00 00	cpx #$0000	                CPX #$0000
.39146f		d0 05		bne $391476	                BNE BMP_LUT1_PICK
.391471		20 37 15	jsr $391537	                JSR BMP_PARSER_UPDATE_LUT0   ; Go Upload the LUT0
.391474		80 08		bra $39147e	                BRA DONE_TRANSFER_LUT;
.391476						  BMP_LUT1_PICK
.391476		e0 01 00	cpx #$0001	                CPX #$0001
.391479		d0 03		bne $39147e	                BNE BMP_LUT2_PICK
.39147b		20 67 15	jsr $391567	                JSR BMP_PARSER_UPDATE_LUT1   ; Go Upload the LUT1
.39147e						  BMP_LUT2_PICK
.39147e						  DONE_TRANSFER_LUT
.39147e		a5 56		lda $56		                LDA BMP_POSITION_Y
.391480		8f 00 01 00	sta $000100	                STA @lUNSIGNED_MULT_A_LO
.391484		a5 4e		lda $4e		                LDA SCRN_X_STRIDE
.391486		8f 02 01 00	sta $000102	                STA @lUNSIGNED_MULT_B_LO
.39148a		af 04 01 00	lda $000104	                LDA @lUNSIGNED_MULT_AL_LO
.39148e		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL          ; Store in 32Bit Adder (A)
.391492		af 06 01 00	lda $000106	                LDA @lUNSIGNED_MULT_AL_LO+2
.391496		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL          ; Store in 32Bit Adder (A)
.39149a		a5 54		lda $54		                LDA BMP_POSITION_X
.39149c		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL          ; Put the X Position Adder (B)
.3914a0		a9 00 00	lda #$0000	                LDA #$0000
.3914a3		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL
.3914a7		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL          ; Put the Results in TEMP
.3914ab		85 f0		sta $f0		                STA USER_TEMP
.3914ad		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL          ; Put the Results in TEMP
.3914b1		85 f2		sta $f2		                STA USER_TEMP+2
.3914b3		a5 48		lda $48		                LDA BMP_PRSE_DST_PTR
.3914b5		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL          ; Store in 32Bit Adder (A)
.3914b9		a5 4a		lda $4a		                LDA BMP_PRSE_DST_PTR+2
.3914bb		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL          ; Store in 32Bit Adder (A)
.3914bf		a5 f0		lda $f0		                LDA USER_TEMP
.3914c1		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL          ; Store in 32Bit Adder (B)
.3914c5		a5 f2		lda $f2		                LDA USER_TEMP+2
.3914c7		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL          ; Store in 32Bit Adder (B)
.3914cb		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL          ; Put the Results in BMP_PRSE_DST_PTR
.3914cf		85 48		sta $48		                STA BMP_PRSE_DST_PTR
.3914d1		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL          ; Put the Results in BMP_PRSE_DST_PTR
.3914d5		85 4a		sta $4a		                STA BMP_PRSE_DST_PTR+2
.3914d7		a5 44		lda $44		                LDA BMP_PRSE_SRC_PTR        ; Right now it is set @ $020000 (128K)
.3914d9		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL
.3914dd		a5 46		lda $46		                LDA BMP_PRSE_SRC_PTR+2        ; Right now it is set @ $020000 (128K)
.3914df		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL
.3914e3		a5 50		lda $50		                LDA BMP_FILE_SIZE
.3914e5		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL
.3914e9		a5 52		lda $52		                LDA BMP_FILE_SIZE+2
.3914eb		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL
.3914ef		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
.3914f3		85 44		sta $44		                STA BMP_PRSE_SRC_PTR
.3914f5		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
.3914f9		85 46		sta $46		                STA BMP_PRSE_SRC_PTR+2
.3914fb		a5 44		lda $44		                LDA BMP_PRSE_SRC_PTR        ; Right now it is set @ $020000 (128K) + File Size
.3914fd		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL
.391501		a5 46		lda $46		                LDA BMP_PRSE_SRC_PTR+2      ; Right now it is set @ $020000 (128K)
.391503		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL
.391507		18		clc		                CLC
.391508		a5 40		lda $40		                LDA BMP_X_SIZE              ; Load The Size in X of the image and Make it negative
.39150a		49 ff ff	eor #$ffff	                EOR #$FFFF                  ; Inverse all bit
.39150d		69 01 00	adc #$0001	                ADC #$0001                  ; Add 0 ()
.391510		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL          ; Store the Results in reg B of ADDER32
.391514		a9 ff ff	lda #$ffff	                LDA #$FFFF
.391517		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL          ; Store in the Reminder of the 32Bits B Register
.39151b		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
.39151f		85 44		sta $44		                STA BMP_PRSE_SRC_PTR
.391521		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
.391525		85 46		sta $46		                STA BMP_PRSE_SRC_PTR+2
.391527		20 97 15	jsr $391597	                JSR BMP_PARSER_DMA_SHIT_OUT  ; We are going to start with the slow method
.39152a		a2 74 71	ldx #$7174	                LDX #<>bmp_parser_msg0
.39152d		80 03		bra $391532	                BRA BMP_PARSER_END_NO_ERROR
.39152f						BMP_PARSER_END_WITH_ERROR
.39152f		a2 60 71	ldx #$7160	                LDX #<>bmp_parser_err0
.391532						BMP_PARSER_END_NO_ERROR
.391532		22 7e 07 39	jsl $39077e	                JSL IPRINT       ; print the first line
.391536		6b		rtl		                RTL
.391537						BMP_PARSER_UPDATE_LUT0
.391537		38		sec		                SEC
.391538		a0 7a 00	ldy #$007a	                LDY #$007A
.39153b		a2 00 00	ldx #$0000	                LDX #$0000
.39153e		e2 20		sep #$20	                SEP #$20        ; set A short
.391540						BMP_PARSER_UPDATE_LOOP
.391540		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; First Pixel is Red
.391542		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR+0, X      ; The look-up Table point to a pixel Blue
.391546		c8		iny		                INY
.391547		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Second Pixel is Green
.391549		9f 01 20 af	sta $af2001,x	                STA @lGRPH_LUT0_PTR+1, X      ; The look-up Table point to a pixel Blue
.39154d		c8		iny		                INY
.39154e		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Third Pixel is Blue
.391550		9f 02 20 af	sta $af2002,x	                STA @lGRPH_LUT0_PTR+2, X      ; The look-up Table point to a pixel Blue
.391554		c8		iny		                INY
.391555		a9 80		lda #$80	                LDA #$80
.391557		9f 03 20 af	sta $af2003,x	                STA @lGRPH_LUT0_PTR+3, X      ; The look-up Table point to a pixel Blue
.39155b		c8		iny		                INY ; For the Alpha Value, nobody cares
.39155c		e8		inx		                INX
.39155d		e8		inx		                INX
.39155e		e8		inx		                INX
.39155f		e8		inx		                INX
.391560		e4 4c		cpx $4c		                CPX BMP_COLOR_PALET         ; Apparently sometime there is less than 256 Values in the lookup
.391562		d0 dc		bne $391540	                BNE BMP_PARSER_UPDATE_LOOP
.391564		c2 20		rep #$20	                REP #$20        ; set A long
.391566		60		rts		                RTS
.391567						BMP_PARSER_UPDATE_LUT1
.391567		38		sec		                SEC
.391568		a0 36 00	ldy #$0036	                LDY #$0036
.39156b		a2 00 00	ldx #$0000	                LDX #$0000
.39156e		e2 20		sep #$20	                SEP #$20        ; set A short
.391570						PALETTE_LUT1_LOOP
.391570		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; First Pixel is Red
.391572		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR+0, X      ; The look-up Table point to a pixel Blue
.391576		c8		iny		                INY
.391577		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Second Pixel is Green
.391579		9f 01 24 af	sta $af2401,x	                STA @lGRPH_LUT1_PTR+1, X      ; The look-up Table point to a pixel Blue
.39157d		c8		iny		                INY
.39157e		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Third Pixel is Blue
.391580		9f 02 24 af	sta $af2402,x	                STA @lGRPH_LUT1_PTR+2, X      ; The look-up Table point to a pixel Blue
.391584		c8		iny		                INY
.391585		a9 80		lda #$80	                LDA #$80
.391587		9f 03 24 af	sta $af2403,x	                STA @lGRPH_LUT1_PTR+3, X      ; The look-up Table point to a pixel Blue
.39158b		c8		iny		                INY ; For the Alpha Value, nobody cares
.39158c		e8		inx		                INX
.39158d		e8		inx		                INX
.39158e		e8		inx		                INX
.39158f		e8		inx		                INX
.391590		e4 4c		cpx $4c		                CPX BMP_COLOR_PALET         ; Apparently sometime there is less than 256 Values in the lookup
.391592		d0 dc		bne $391570	                BNE PALETTE_LUT1_LOOP
.391594		c2 20		rep #$20	                REP #$20        ; set A long
.391596		60		rts		                RTS
.391597						BMP_PARSER_DMA_SHIT_OUT
.391597		a2 00 00	ldx #$0000	                LDX #$0000
.39159a						BMP_PARSER_LOOPY
.39159a		a0 00 00	ldy #$0000	                LDY #$0000
.39159d		e2 20		sep #$20	                SEP #$20        ; set A short
.39159f						BMP_PARSER_LOOPX
.39159f		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Load First Pixel Y (will be linear)
.3915a1		97 48		sta [$48],y	                STA [BMP_PRSE_DST_PTR],Y    ; This is where the Pixel Go, Video Memory
.3915a3		c8		iny		                INY
.3915a4		c4 40		cpy $40		                CPY BMP_X_SIZE              ; Transfer the First line
.3915a6		d0 f7		bne $39159f	                BNE BMP_PARSER_LOOPX
.3915a8		20 b4 15	jsr $3915b4	                JSR BMP_PARSER_COMPUTE_Y_SRC
.3915ab		20 cf 15	jsr $3915cf	                JSR BMP_PARSER_COMPUTE_Y_DST
.3915ae		e8		inx		                INX
.3915af		e4 42		cpx $42		                CPX BMP_Y_SIZE
.3915b1		d0 e7		bne $39159a	                BNE BMP_PARSER_LOOPY
.3915b3		60		rts		                RTS
.3915b4						BMP_PARSER_COMPUTE_Y_SRC
.3915b4		c2 20		rep #$20	                REP #$20        ; set A long
.3915b6		a5 44		lda $44		                LDA BMP_PRSE_SRC_PTR        ; Right now it is set @ $020000 (128K) + File Size
.3915b8		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL
.3915bc		a5 46		lda $46		                LDA BMP_PRSE_SRC_PTR+2      ; Right now it is set @ $020000 (128K)
.3915be		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL
.3915c2		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
.3915c6		85 44		sta $44		                STA BMP_PRSE_SRC_PTR
.3915c8		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
.3915cc		85 46		sta $46		                STA BMP_PRSE_SRC_PTR+2
.3915ce		60		rts		                RTS
.3915cf						BMP_PARSER_COMPUTE_Y_DST
.3915cf		c2 20		rep #$20	                REP #$20        ; set A long
.3915d1		18		clc		                CLC
.3915d2		a5 48		lda $48		                LDA BMP_PRSE_DST_PTR
.3915d4		65 4e		adc $4e		                ADC SCRN_X_STRIDE        ; In Normal Circumstances, it is 640
.3915d6		85 48		sta $48		                STA BMP_PRSE_DST_PTR
.3915d8		a5 4a		lda $4a		                LDA BMP_PRSE_DST_PTR+2
.3915da		69 00 00	adc #$0000	                ADC #$0000
.3915dd		85 4a		sta $4a		                STA BMP_PRSE_DST_PTR+2
.3915df		60		rts		                RTS
.3915e0		ea		nop		ILOOP           NOP
.3915e1		ea		nop		                NOP
.3915e2		ea		nop		                NOP
.3915e3		ea		nop		                NOP
.3915e4		ea		nop		                NOP
.3915e5		ea		nop		                NOP
.3915e6		ea		nop		                NOP
.3915e7		ea		nop		                NOP
.3915e8		ea		nop		                NOP
.3915e9		ea		nop		                NOP
.3915ea		6b		rtl		                RTL
.3915eb		22 e0 15 39	jsl $3915e0	ILOOP_1         JSL ILOOP
.3915ef		22 e0 15 39	jsl $3915e0	                JSL ILOOP
.3915f3		22 e0 15 39	jsl $3915e0	                JSL ILOOP
.3915f7		22 e0 15 39	jsl $3915e0	                JSL ILOOP
.3915fb		22 e0 15 39	jsl $3915e0	                JSL ILOOP
.3915ff		22 e0 15 39	jsl $3915e0	                JSL ILOOP
.391603		22 e0 15 39	jsl $3915e0	                JSL ILOOP
.391607		22 e0 15 39	jsl $3915e0	                JSL ILOOP
.39160b		22 e0 15 39	jsl $3915e0	                JSL ILOOP
.39160f		22 e0 15 39	jsl $3915e0	                JSL ILOOP
.391613		6b		rtl		                RTL
.391614		22 eb 15 39	jsl $3915eb	ILOOP_1MS       JSL ILOOP_1
.391618		6b		rtl		                RTL
.391619		e0 00 00	cpx #$0000	ILOOP_MS        CPX #0
.39161c		f0 07		beq $391625	                BEQ LOOP_MS_END
.39161e		22 14 16 39	jsl $391614	                JSL ILOOP_1MS
.391622		ca		dex		                DEX
.391623		80 f4		bra $391619	                BRA ILOOP_MS
.391625		6b		rtl		LOOP_MS_END     RTL
.391626						IDELAY
.391626		8b		phb		                PHB
.391627		08		php		                PHP
.391628		48		pha		                PHA             ; begin setdbr macro
.391629		08		php		                PHP
.39162a		e2 20		sep #$20	                SEP #$20        ; set A short
.39162c		a9 00		lda #$00	                LDA #0
.39162e		48		pha		                PHA
.39162f		ab		plb		                PLB
.391630		28		plp		                PLP
.391631		68		pla		                PLA             ; end setdbr macro
.391632		e2 20		sep #$20	                SEP #$20        ; set A short
.391634		a9 00		lda #$00	                LDA #0                      ; Stop the timer if it's running
.391636		8f 60 01 00	sta $000160	                STA @l TIMER0_CTRL_REG
.39163a		af 4c 01 00	lda $00014c	                LDA @l INT_MASK_REG0        ; Enable Timer 0 Interrupts
.39163e		29 fb		and #$fb	                AND #~FNX0_INT02_TMR0
.391640		8f 4c 01 00	sta $00014c	                STA @l INT_MASK_REG0
.391644		a9 7f		lda #$7f	                LDA #~TIMER0TRIGGER         ; Clear the timer 0 trigger flag
.391646		8d 05 07	sta $0705	                STA @w TIMERFLAGS
.391649		a9 00		lda #$00	                LDA #0
.39164b		8f 61 01 00	sta $000161	                STA @l TIMER0_CHARGE_L      ; Clear the comparator for count-down
.39164f		8f 62 01 00	sta $000162	                STA @l TIMER0_CHARGE_M
.391653		8f 63 01 00	sta $000163	                STA @l TIMER0_CHARGE_H
.391657		c2 30		rep #$30	                REP #$30        ; set A&X long
.391659		8a		txa		                TXA
.39165a		8f 65 01 00	sta $000165	                STA @l TIMER0_CMP_L         ; Set the number of ticks
.39165e		98		tya		                TYA
.39165f		e2 20		sep #$20	                SEP #$20        ; set A short
.391661		8f 67 01 00	sta $000167	                STA @l TIMER0_CMP_H
.391665		a9 09		lda #$09	                LDA #TMR0_EN | TMR0_UPDWN   ; Enable the timer to count up
.391667		8f 60 01 00	sta $000160	                STA @l TIMER0_CTRL_REG
.39166b		a9 80		lda #$80	                LDA #TIMER0TRIGGER          ; Timer zero's trigger flag
.39166d		cb		wai		loop            WAI                         ; Wait for an interrupt
.39166e		1c 05 07	trb $0705	                TRB @w TIMERFLAGS           ; Check for the flag
.391671		f0 fa		beq $39166d	                BEQ loop                    ; Keep checking until it's set
.391673		a9 00		lda #$00	                LDA #0                      ; Stop the timer
.391675		8f 60 01 00	sta $000160	                STA @l TIMER0_CTRL_REG
.391679		a9 7f		lda #$7f	                LDA #~TIMER0TRIGGER         ; Clear the timer 0 trigger flag
.39167b		8d 05 07	sta $0705	                STA @w TIMERFLAGS
.39167e		af 4c 01 00	lda $00014c	                LDA @l INT_MASK_REG0        ; Disable Timer 0 Interrupts
.391682		09 04		ora #$04	                ORA #FNX0_INT02_TMR0
.391684		8f 4c 01 00	sta $00014c	                STA @l INT_MASK_REG0
.391688		28		plp		                PLP
.391689		ab		plb		                PLB
.39168a		6b		rtl		                RTL
.39168b						SHOW_CREDITS
.39168b		48		pha		                PHA
.39168c		da		phx		                PHX
.39168d		5a		phy		                PHY
.39168e		08		php		                PHP
.39168f		e2 20		sep #$20	                SEP #$20        ; set A short
.391691		c2 10		rep #$10	                REP #$10        ; set X long
.391693		af 10 00 af	lda $af0010	                LDA @lVKY_TXT_CURSOR_CTRL_REG   ; Disable the cursor
.391697		29 fe		and #$fe	                AND #~Vky_Cursor_Enable
.391699		8f 10 00 af	sta $af0010	                STA @lVKY_TXT_CURSOR_CTRL_REG
.39169d		a2 00 00	ldx #$0000	                LDX #0
.3916a0		bf 00 00 3b	lda $3b0000,x	credit_loop     LDA @lCREDITS_TEXT,X            ; Copy a byte of text
.3916a4		9f 00 a0 af	sta $afa000,x	                STA @lCS_TEXT_MEM_PTR,X
.3916a8		bf 00 20 3b	lda $3b2000,x	                LDA @lCREDITS_COLOR,X           ; Copy a byte of color
.3916ac		9f 00 c0 af	sta $afc000,x	                STA @lCS_COLOR_MEM_PTR,X
.3916b0		e8		inx		                INX
.3916b1		e0 00 20	cpx #$2000	                CPX #128 * 64
.3916b4		d0 ea		bne $3916a0	                BNE credit_loop
.3916b6		22 21 07 39	jsl $390721	                JSL IGETCHW                     ; Wait for a keypress
.3916ba		22 42 0b 39	jsl $390b42	                JSL ICLRSCREEN                  ; Then clear the screen and return
.3916be		22 66 09 39	jsl $390966	                JSL ICSRHOME                    ; Move cursor to the home position
.3916c2		af 10 00 af	lda $af0010	                LDA @lVKY_TXT_CURSOR_CTRL_REG   ; Enable the cursor
.3916c6		09 01		ora #$01	                ORA #Vky_Cursor_Enable
.3916c8		8f 10 00 af	sta $af0010	                STA @lVKY_TXT_CURSOR_CTRL_REG
.3916cc		28		plp		                PLP
.3916cd		7a		ply		                PLY
.3916ce		fa		plx		                PLX
.3916cf		68		pla		                PLA
.3916d0		6b		rtl		                RTL
.3916d1		00		brk #		ISCINIT         BRK ;
.3916d2		00		brk #		IIOINIT         BRK ;
.3916d3		00		brk #		ISETLFS         BRK ; Obsolete (done in OPEN)
.3916d4		00		brk #		ISETNAM         BRK ; Obsolete (done in OPEN)
.3916d5		00		brk #		IOPEN           BRK ; Open a channel for reading and/or writing. Use SETLFS and SETNAM to set the channels and filename first.
.3916d6		00		brk #		ICLOSE          BRK ; Close a channel
.3916d7		00		brk #		IGETB           BRK ; Get a byte from input channel. Return 0 if no input. Carry is set if no input.
.3916d8		00		brk #		IGETS           BRK ; Get a string from the input channel. NULL terminates
.3916d9		00		brk #		IGETLINE        BRK ; Get a line of text from input channel. CR or NULL terminates.
.3916da		00		brk #		IGETFIELD       BRK ; Get a field from the input channel. Value in A, CR, or NULL terminates
.3916db		00		brk #		ITRIM           BRK ; Removes spaces at beginning and end of string.
.3916dc		00		brk #		IPRINTC         BRK ; Print character to screen. Handles terminal commands
.3916dd		00		brk #		IPRINTS         BRK ; Print string to screen. Handles terminal commands
.3916de		00		brk #		IPRINTF         BRK ; Print a float value
.3916df		00		brk #		IPRINTI         BRK ; Prints integer value in TEMP
.3916e0		00		brk #		IPRINTAI        BRK ; Prints integer value in A
.3916e1		00		brk #		IPUSHKEY        BRK ;
.3916e2		00		brk #		IPUSHKEYS       BRK ;
.3916e3		00		brk #		ISCRREADLINE    BRK ; Loads the MCMDADDR/BCMDADDR variable with the address of the current line on the screen. This is called when the RETURN key is pressed and is the first step in processing an immediate mode command.
.3916e4		00		brk #		ISCRGETWORD     BRK ; Read a current word on the screen. A word ends with a space, punctuation (except _), or any control character (value < 32). Loads the address into CMPTEXT_VAL and length into CMPTEXT_LEN variables.
.3916e5		6b		rtl		IRQHANDLESTUB   RTL

;******  Processing file: src\OPL2_Library.asm


;******  Processing file: src\OPL3_def.asm

=$afe600					OPL3_R_BASE               = $AFE600
=$e600						OPL3_R_BASE_LL            = $E600
=$00af						OPL3_R_BASE_HL            = $00AF
=$afe601					OPL3_R_TEST               = $AFE601 ; TEST
=$afe602					OPL3_R_TIMER1             = $AFE602 ; TIMER-1
=$afe603					OPL3_R_TIMER2             = $AFE603 ; TIMER-2
=$afe604					OPL3_R_IRQ                = $AFE604 ;
=$afe605					OPL3_R_OPL3_MODE          = $AFE605 ; Set bit 0 to 1 if you want to use in OPL3 Mode
=$afe608					OPL3_R_CSM                = $AFE608 ;
=$afe620					OPL3_R_AM_VID_EG_KSR_MULT = $AFE620 ; $40..$35 (21 Registers)
=$afe640					OPL3_R_KSL_TL             = $AFE640;  $40..$55 (21 Registers)
=$afe660					OPL3_R_AR_DR              = $AFE660;  $60..$75 (21 Registers)
=$afe680					OPL3_R_SL_RR              = $AFE680;  $80..$95 (21 Registers)
=$afe6a0					OPL3_R_FNumber            = $AFE6A0;  $A0..$A8
=$afe6b0					OPL3_R_KON_BLOCK_FNumber  = $AFE6B0;  $B0..$B9
=$afe6bd					OPL3_R_DPTH_RHYTM         = $AFE6BD;  $BD
=$afe6c0					OPL3_R_FEEDBACK           = $AFE6C0;  $C0..$C9
=$afe6e0					OPL3_R_WAVE_SELECT        = $AFE6E0;  $E0..$F5
=$afe700					OPL3_L_BASE               = $AFE700
=$e700						OPL3_L_BASE_LL            = $E700
=$00af						OPL3_L_BASE_HL            = $00AF
=$afe701					OPL3_L_TEST               = $AFE701 ; TEST
=$afe702					OPL3_L_TIMER1             = $AFE702 ; TIMER-1
=$afe703					OPL3_L_TIMER2             = $AFE703 ; TIMER-2
=$afe704					OPL3_L_IRQ                = $AFE704 ;
=$afe708					OPL3_L_CSM                = $AFE708 ;
=$afe720					OPL3_L_AM_VID_EG_KSR_MULT = $AFE720 ; $40..$35 (21 Registers)
=$afe740					OPL3_L_KSL_TL             = $AFE740;  $40..$55 (21 Registers)
=$afe760					OPL3_L_AR_DR              = $AFE760;  $60..$75 (21 Registers)
=$afe780					OPL3_L_SL_RR              = $AFE780;  $80..$95 (21 Registers)
=$afe7a0					OPL3_L_FNumber            = $AFE7A0;  $A0..$A8
=$afe7b0					OPL3_L_KON_BLOCK_FNumber  = $AFE7B0;  $B0..$B9
=$afe7bd					OPL3_L_DPTH_RHYTM         = $AFE7BD;  $BD
=$afe7c0					OPL3_L_FEEDBACK           = $AFE7C0;  $C0..$C9
=$afe7e0					OPL3_L_WAVE_SELECT        = $AFE7E0;  $E0..$F5
=$80						TREMOLO    = $80
=$40						VIBRATO    = $40
=$20						SUSTAINING = $20
=$10						KSR        = $10
=$0f						MULTIPLIER = $0F
=$c0						KEY_SCALE  = $C0
=$3f						OP_LEVEL   = $3F
=$f0						ATTACK_RT  = $F0
=$0f						DECAY_RT   = $0F
=$f0						SUSTAIN_RT = $F0
=$0f						RELEASE_RT = $0F
=$0e						FEEDBACK   = $0E
=$01						ALGORITHM  = $01
=9						OPL2_NUM_CHANNELS = 9
=0						OPERATOR1 = 0
=1						OPERATOR2 = 1
=0						MODULATOR = 0
=1						CARRIER = 1
=0						FREQ_MODULATION = 0
=1						ADDITIVE_SYNTH  = 1
=$10						DRUM_BASS   = $10
=$08						DRUM_SNARE  = $08
=$04						DRUM_TOM    = $04
=$02						DRUM_CYMBAL = $02
=$01						DRUM_HI_HAT = $01
=1						NOTE_CS =   1
=2						NOTE_D =    2
=3						NOTE_DS =   3
=4						NOTE_E =    4
=5						NOTE_F =    5
=6						NOTE_FS =   6
=7						NOTE_G =    7
=8						NOTE_GS =   8
=9						NOTE_A =    9
=10						NOTE_AS =  10
=11						NOTE_B =   11
=12						NOTE_C =   12
>3916e6		6b 01 81 01 98 01 b0 01		noteFNumbers    .word  $016B, $0181, $0198, $01B0, $01CA, $01E5, $0202, $0220, $0241, $0263, $0287, $02AE
>3916ee		ca 01 e5 01 02 02 20 02 41 02 63 02 87 02 ae 02
>3916fe		00 01 02 08 09 0a 10 11		registerOffsets_operator0 .byte $00, $01, $02, $08, $09, $0A, $10, $11, $12 ;initializers for operator 1 */
>391706		12
>391707		03 04 05 0b 0c 0d 13 14		registerOffsets_operator1 .byte $03, $04, $05, $0B, $0C, $0D, $13, $14, $15 ;initializers for operator 2 */
>39170f		15
>391710		10 13 14 12 15 11		drumOffsets               .byte $10, $13, $14, $12, $15, $11
>391716		10 08 04 02 01			drumBits                  .byte $10, $08, $04, $02, $01
>39171b		20 40 60 80 e0 c0		instrumentBaseRegs        .byte $20, $40, $60, $80, $E0, $C0

;******  Return to file: src\OPL2_Library.asm


;******  Processing file: src\OPL2_Instruments.asm

>391721		00 24 4f f2 0b 00 0e 31		INSTRUMENT_ACCORDN    .text $00, $24, $4F, $F2, $0B, $00, $0E, $31, $00, $52, $0B, $00, 'ACCORDN   '
>391729		00 52 0b 00 41 43 43 4f 52 44 4e 20 20 20
>391737		00 31 43 6e 17 01 02 22		INSTRUMENT_BAGPIPE1   .text $00, $31, $43, $6E, $17, $01, $02, $22, $05, $8B, $0C, $02, 'BAGPIPE1  '
>39173f		05 8b 0c 02 42 41 47 50 49 50 45 31 20 20
>39174d		00 30 00 ff a0 03 00 a3		INSTRUMENT_BAGPIPE2   .text $00, $30, $00, $FF, $A0, $03, $00, $A3, $00, $65, $0B, $02, 'BAGPIPE2  '
>391755		00 65 0b 02 42 41 47 50 49 50 45 32 20 20
>391763		00 31 87 a1 11 00 08 16		INSTRUMENT_BANJO1     .text $00, $31, $87, $A1, $11, $00, $08, $16, $80, $7D, $43, $00, 'BANJO1    '
>39176b		80 7d 43 00 42 41 4e 4a 4f 31 20 20 20 20
>391779		00 01 15 25 2f 00 0a 21		INSTRUMENT_BASS1      .text $00, $01, $15, $25, $2F, $00, $0A, $21, $80, $65, $6C, $00, 'BASS1     '
>391781		80 65 6c 00 42 41 53 53 31 20 20 20 20 20
>39178f		00 01 1d f2 ef 00 0a 01		INSTRUMENT_BASS2      .text $00, $01, $1D, $F2, $EF, $00, $0A, $01, $00, $F5, $78, $00, 'BASS2     '
>391797		00 f5 78 00 42 41 53 53 32 20 20 20 20 20
>3917a5		00 c0 6d f9 01 01 0e 41		INSTRUMENT_BASSHARP   .text $00, $C0, $6D, $F9, $01, $01, $0E, $41, $00, $F2, $73, $00, 'BASSHARP  '
>3917ad		00 f2 73 00 42 41 53 53 48 41 52 50 20 20
>3917bb		00 30 c8 d5 19 00 0c 71		INSTRUMENT_BASSOON1   .text $00, $30, $C8, $D5, $19, $00, $0C, $71, $80, $61, $1B, $00, 'BASSOON1  '
>3917c3		80 61 1b 00 42 41 53 53 4f 4f 4e 31 20 20
>3917d1		00 c1 4f b1 53 03 06 e0		INSTRUMENT_BASSTRLG   .text $00, $C1, $4F, $B1, $53, $03, $06, $E0, $00, $12, $74, $03, 'BASSTRLG  '
>3917d9		00 12 74 03 42 41 53 53 54 52 4c 47 20 20
>3917e7		06 00 0b a8 4c 00 00 00		INSTRUMENT_BDRUM1     .text $06, $00, $0B, $A8, $4C, $00, $00, $00, $00, $00, $00, $00, 'BDRUM1    '
>3917ef		00 00 00 00 42 44 52 55 4d 31 20 20 20 20
>3917fd		00 64 db ff 01 00 04 3e		INSTRUMENT_BELLONG    .text $00, $64, $DB, $FF, $01, $00, $04, $3E, $C0, $F3, $62, $00, 'BELLONG   '
>391805		c0 f3 62 00 42 45 4c 4c 4f 4e 47 20 20 20
>391813		00 07 4f f2 60 00 08 12		INSTRUMENT_BELLS      .text $00, $07, $4F, $F2, $60, $00, $08, $12, $00, $F2, $72, $00, 'BELLS     '
>39181b		00 f2 72 00 42 45 4c 4c 53 20 20 20 20 20
>391829		00 64 db ff 01 00 04 3e		INSTRUMENT_BELSHORT   .text $00, $64, $DB, $FF, $01, $00, $04, $3E, $C0, $F5, $F3, $00, 'BELSHORT  '
>391831		c0 f5 f3 00 42 45 4c 53 48 4f 52 54 20 20
>39183f		00 20 4b 7b 04 01 0e 21		INSTRUMENT_BNCEBASS   .text $00, $20, $4B, $7B, $04, $01, $0E, $21, $00, $F5, $72, $00, 'BNCEBASS  '
>391847		00 f5 72 00 42 4e 43 45 42 41 53 53 20 20
>391855		00 21 16 71 ae 00 0e 21		INSTRUMENT_BRASS1     .text $00, $21, $16, $71, $AE, $00, $0E, $21, $00, $81, $9E, $00, 'BRASS1    '
>39185d		00 81 9e 00 42 52 41 53 53 31 20 20 20 20
>39186b		00 30 c5 52 11 00 00 31		INSTRUMENT_CBASSOON   .text $00, $30, $C5, $52, $11, $00, $00, $31, $80, $31, $2E, $00, 'CBASSOON  '
>391873		80 31 2e 00 43 42 41 53 53 4f 4f 4e 20 20
>391881		00 33 87 01 10 00 08 14		INSTRUMENT_CELESTA    .text $00, $33, $87, $01, $10, $00, $08, $14, $80, $7D, $33, $00, 'CELESTA   '
>391889		80 7d 33 00 43 45 4c 45 53 54 41 20 20 20
>391897		00 32 16 73 24 00 0e 21		INSTRUMENT_CLAR1      .text $00, $32, $16, $73, $24, $00, $0E, $21, $80, $75, $57, $00, 'CLAR1     '
>39189f		80 75 57 00 43 4c 41 52 31 20 20 20 20 20
>3918ad		00 31 1c 41 1b 00 0c 60		INSTRUMENT_CLAR2      .text $00, $31, $1C, $41, $1B, $00, $0C, $60, $80, $42, $3B, $00, 'CLAR2     '
>3918b5		80 42 3b 00 43 4c 41 52 32 20 20 20 20 20
>3918c3		00 32 9a 51 1b 00 0c 61		INSTRUMENT_CLARINET   .text $00, $32, $9A, $51, $1B, $00, $0C, $61, $82, $A2, $3B, $00, 'CLARINET  '
>3918cb		82 a2 3b 00 43 4c 41 52 49 4e 45 54 20 20
>3918d9		00 11 0d f2 01 00 0a 15		INSTRUMENT_CLAVECIN   .text $00, $11, $0D, $F2, $01, $00, $0A, $15, $0D, $F2, $B1, $00, 'CLAVECIN  '
>3918e1		0d f2 b1 00 43 4c 41 56 45 43 49 4e 20 20
>3918ef		00 00 02 f0 ff 00 06 11		INSTRUMENT_CROMORNE   .text $00, $00, $02, $F0, $FF, $00, $06, $11, $80, $F0, $FF, $00, 'CROMORNE  '
>3918f7		80 f0 ff 00 43 52 4f 4d 4f 52 4e 45 20 20
>391905		09 01 00 f5 b5 00 00 00		INSTRUMENT_CYMBAL1    .text $09, $01, $00, $F5, $B5, $00, $00, $00, $00, $00, $00, $00, 'CYMBAL1   '
>39190d		00 00 00 00 43 59 4d 42 41 4c 31 20 20 20
>39191b		00 05 8a f0 7b 00 08 01		INSTRUMENT_ELCLAV1    .text $00, $05, $8A, $F0, $7B, $00, $08, $01, $80, $F4, $7B, $00, 'ELCLAV1   '
>391923		80 f4 7b 00 45 4c 43 4c 41 56 31 20 20 20
>391931		00 01 49 f1 53 01 06 11		INSTRUMENT_ELCLAV2    .text $00, $01, $49, $F1, $53, $01, $06, $11, $00, $F1, $74, $02, 'ELCLAV2   '
>391939		00 f1 74 02 45 4c 43 4c 41 56 32 20 20 20
>391947		00 e0 6d 57 04 01 0e 61		INSTRUMENT_ELECFL     .text $00, $E0, $6D, $57, $04, $01, $0E, $61, $00, $67, $7D, $00, 'ELECFL    '
>39194f		00 67 7d 00 45 4c 45 43 46 4c 20 20 20 20
>39195d		00 13 97 9a 12 02 0e 91		INSTRUMENT_ELECVIBE   .text $00, $13, $97, $9A, $12, $02, $0E, $91, $80, $9B, $11, $00, 'ELECVIBE  '
>391965		80 9b 11 00 45 4c 45 43 56 49 42 45 20 20
>391973		00 f1 01 97 17 00 08 21		INSTRUMENT_ELGUIT1    .text $00, $F1, $01, $97, $17, $00, $08, $21, $0D, $F1, $18, $00, 'ELGUIT1   '
>39197b		0d f1 18 00 45 4c 47 55 49 54 31 20 20 20
>391989		00 13 96 ff 21 00 0a 11		INSTRUMENT_ELGUIT2    .text $00, $13, $96, $FF, $21, $00, $0A, $11, $80, $FF, $03, $00, 'ELGUIT2   '
>391991		80 ff 03 00 45 4c 47 55 49 54 32 20 20 20
>39199f		00 07 8f 82 7d 00 0c 14		INSTRUMENT_ELGUIT3    .text $00, $07, $8F, $82, $7D, $00, $0C, $14, $80, $82, $7D, $00, 'ELGUIT3   '
>3919a7		80 82 7d 00 45 4c 47 55 49 54 33 20 20 20
>3919b5		00 05 8f da 15 00 0a 01		INSTRUMENT_ELGUIT4    .text $00, $05, $8F, $DA, $15, $00, $0A, $01, $80, $F9, $14, $02, 'ELGUIT4   '
>3919bd		80 f9 14 02 45 4c 47 55 49 54 34 20 20 20
>3919cb		00 b2 cd 91 2a 02 09 b1		INSTRUMENT_ELORGAN1   .text $00, $B2, $CD, $91, $2A, $02, $09, $B1, $80, $91, $2A, $01, 'ELORGAN1  '
>3919d3		80 91 2a 01 45 4c 4f 52 47 41 4e 31 20 20
>3919e1		00 01 4f f1 50 00 06 01		INSTRUMENT_ELPIANO1   .text $00, $01, $4F, $F1, $50, $00, $06, $01, $04, $D2, $7C, $00, 'ELPIANO1  '
>3919e9		04 d2 7c 00 45 4c 50 49 41 4e 4f 31 20 20
>3919f7		00 02 22 f2 13 00 0e 02		INSTRUMENT_ELPIANO2   .text $00, $02, $22, $F2, $13, $00, $0E, $02, $00, $F5, $43, $00, 'ELPIANO2  '
>3919ff		00 f5 43 00 45 4c 50 49 41 4e 4f 32 20 20
>391a0d		00 81 63 f3 58 00 00 01		INSTRUMENT_EPIANO1A   .text $00, $81, $63, $F3, $58, $00, $00, $01, $80, $F2, $58, $00, 'EPIANO1A  '
>391a15		80 f2 58 00 45 50 49 41 4e 4f 31 41 20 20
>391a23		00 07 1f f5 fa 00 0e 01		INSTRUMENT_EPIANO1B   .text $00, $07, $1F, $F5, $FA, $00, $0E, $01, $57, $F5, $FA, $00, 'EPIANO1B  '
>391a2b		57 f5 fa 00 45 50 49 41 4e 4f 31 42 20 20
>391a39		00 21 83 74 17 00 07 a2		INSTRUMENT_FLUTE      .text $00, $21, $83, $74, $17, $00, $07, $A2, $8D, $65, $17, $00, 'FLUTE     '
>391a41		8d 65 17 00 46 4c 55 54 45 20 20 20 20 20
>391a4f		00 a1 27 74 8f 00 02 a1		INSTRUMENT_FLUTE1     .text $00, $A1, $27, $74, $8F, $00, $02, $A1, $80, $65, $2A, $00, 'FLUTE1    '
>391a57		80 65 2a 00 46 4c 55 54 45 31 20 20 20 20
>391a65		00 e0 ec 6e 8f 00 0e 61		INSTRUMENT_FLUTE2     .text $00, $E0, $EC, $6E, $8F, $00, $0E, $61, $00, $65, $2A, $00, 'FLUTE2    '
>391a6d		00 65 2a 00 46 4c 55 54 45 32 20 20 20 20
>391a7b		00 21 9f 53 5a 00 0c 21		INSTRUMENT_FRHORN1    .text $00, $21, $9F, $53, $5A, $00, $0C, $21, $80, $AA, $1A, $00, 'FRHORN1   '
>391a83		80 aa 1a 00 46 52 48 4f 52 4e 31 20 20 20
>391a91		00 20 8e a5 8f 02 06 21		INSTRUMENT_FRHORN2    .text $00, $20, $8E, $A5, $8F, $02, $06, $21, $00, $36, $3D, $00, 'FRHORN2   '
>391a99		00 36 3d 00 46 52 48 4f 52 4e 32 20 20 20
>391aa7		00 f0 18 55 ef 02 00 e0		INSTRUMENT_FSTRP1     .text $00, $F0, $18, $55, $EF, $02, $00, $E0, $80, $87, $1E, $03, 'FSTRP1    '
>391aaf		80 87 1e 03 46 53 54 52 50 31 20 20 20 20
>391abd		00 70 16 55 2f 02 0c e0		INSTRUMENT_FSTRP2     .text $00, $70, $16, $55, $2F, $02, $0C, $E0, $80, $87, $1E, $03, 'FSTRP2    '
>391ac5		80 87 1e 03 46 53 54 52 50 32 20 20 20 20
>391ad3		00 f1 00 97 13 00 0a 25		INSTRUMENT_FUZGUIT1   .text $00, $F1, $00, $97, $13, $00, $0A, $25, $0D, $F1, $18, $01, 'FUZGUIT1  '
>391adb		0d f1 18 01 46 55 5a 47 55 49 54 31 20 20
>391ae9		00 31 48 f1 53 00 06 32		INSTRUMENT_FUZGUIT2   .text $00, $31, $48, $F1, $53, $00, $06, $32, $00, $F2, $27, $02, 'FUZGUIT2  '
>391af1		00 f2 27 02 46 55 5a 47 55 49 54 32 20 20
>391aff		00 01 11 f2 1f 00 0a 01		INSTRUMENT_GUITAR1    .text $00, $01, $11, $F2, $1F, $00, $0A, $01, $00, $F5, $88, $00, 'GUITAR1   '
>391b07		00 f5 88 00 47 55 49 54 41 52 31 20 20 20
>391b15		00 02 29 f5 75 00 00 01		INSTRUMENT_HARP1      .text $00, $02, $29, $F5, $75, $00, $00, $01, $83, $F2, $F3, $00, 'HARP1     '
>391b1d		83 f2 f3 00 48 41 52 50 31 20 20 20 20 20
>391b2b		00 02 99 f5 55 00 00 01		INSTRUMENT_HARP2      .text $00, $02, $99, $F5, $55, $00, $00, $01, $80, $F6, $53, $00, 'HARP2     '
>391b33		80 f6 53 00 48 41 52 50 32 20 20 20 20 20
>391b41		00 02 57 f5 56 00 00 01		INSTRUMENT_HARP3      .text $00, $02, $57, $F5, $56, $00, $00, $01, $80, $F6, $54, $00, 'HARP3     '
>391b49		80 f6 54 00 48 41 52 50 33 20 20 20 20 20
>391b57		00 02 29 f5 75 00 00 01		INSTRUMENT_HARPE1     .text $00, $02, $29, $F5, $75, $00, $00, $01, $03, $F2, $F3, $00, 'HARPE1    '
>391b5f		03 f2 f3 00 48 41 52 50 45 31 20 20 20 20
>391b6d		00 32 87 a1 10 00 08 16		INSTRUMENT_HARPSI1    .text $00, $32, $87, $A1, $10, $00, $08, $16, $80, $7D, $33, $00, 'HARPSI1   '
>391b75		80 7d 33 00 48 41 52 50 53 49 31 20 20 20
>391b83		00 33 87 a1 10 00 06 15		INSTRUMENT_HARPSI2    .text $00, $33, $87, $A1, $10, $00, $06, $15, $80, $7D, $43, $00, 'HARPSI2   '
>391b8b		80 7d 43 00 48 41 52 50 53 49 32 20 20 20
>391b99		00 35 84 a8 10 00 08 18		INSTRUMENT_HARPSI3    .text $00, $35, $84, $A8, $10, $00, $08, $18, $80, $7D, $33, $00, 'HARPSI3   '
>391ba1		80 7d 33 00 48 41 52 50 53 49 33 20 20 20
>391baf		00 11 0d f2 01 00 0a 15		INSTRUMENT_HARPSI4    .text $00, $11, $0D, $F2, $01, $00, $0A, $15, $0D, $F2, $B1, $00, 'HARPSI4   '
>391bb7		0d f2 b1 00 48 41 52 50 53 49 34 20 20 20
>391bc5		00 36 87 8a 00 00 08 1a		INSTRUMENT_HARPSI5    .text $00, $36, $87, $8A, $00, $00, $08, $1A, $80, $7F, $33, $00, 'HARPSI5   '
>391bcd		80 7f 33 00 48 41 52 50 53 49 35 20 20 20
>391bdb		00 f0 00 1e 11 01 08 e2		INSTRUMENT_HELICPTR   .text $00, $F0, $00, $1E, $11, $01, $08, $E2, $C0, $11, $11, $01, 'HELICPTR  '
>391be3		c0 11 11 01 48 45 4c 49 43 50 54 52 20 20
>391bf1		0a 01 00 f7 b5 00 00 00		INSTRUMENT_HIHAT1     .text $0A, $01, $00, $F7, $B5, $00, $00, $00, $00, $00, $00, $00, 'HIHAT1    '
>391bf9		00 00 00 00 48 49 48 41 54 31 20 20 20 20
>391c07		0a 01 03 da 18 00 00 00		INSTRUMENT_HIHAT2     .text $0A, $01, $03, $DA, $18, $00, $00, $00, $00, $00, $00, $00, 'HIHAT2    '
>391c0f		00 00 00 00 48 49 48 41 54 32 20 20 20 20
>391c1d		00 87 4d 78 42 00 0a 94		INSTRUMENT_JAVAICAN   .text $00, $87, $4D, $78, $42, $00, $0A, $94, $00, $85, $54, $00, 'JAVAICAN  '
>391c25		00 85 54 00 4a 41 56 41 49 43 41 4e 20 20
>391c33		00 03 5e 85 51 01 0e 11		INSTRUMENT_JAZZGUIT   .text $00, $03, $5E, $85, $51, $01, $0E, $11, $00, $D2, $71, $00, 'JAZZGUIT  '
>391c3b		00 d2 71 00 4a 41 5a 5a 47 55 49 54 20 20
>391c49		00 00 50 f2 70 00 0e 13		INSTRUMENT_JEWSHARP   .text $00, $00, $50, $F2, $70, $00, $0E, $13, $00, $F2, $72, $00, 'JEWSHARP  '
>391c51		00 f2 72 00 4a 45 57 53 48 41 52 50 20 20
>391c5f		00 00 02 f0 fa 01 06 11		INSTRUMENT_KEYBRD1    .text $00, $00, $02, $F0, $FA, $01, $06, $11, $80, $F2, $FA, $01, 'KEYBRD1   '
>391c67		80 f2 fa 01 4b 45 59 42 52 44 31 20 20 20
>391c75		00 01 8f f2 bd 00 08 14		INSTRUMENT_KEYBRD2    .text $00, $01, $8F, $F2, $BD, $00, $08, $14, $80, $82, $BD, $00, 'KEYBRD2   '
>391c7d		80 82 bd 00 4b 45 59 42 52 44 32 20 20 20
>391c8b		00 01 00 f0 f0 00 00 e4		INSTRUMENT_KEYBRD3    .text $00, $01, $00, $F0, $F0, $00, $00, $E4, $03, $F3, $36, $00, 'KEYBRD3   '
>391c93		03 f3 36 00 4b 45 59 42 52 44 33 20 20 20
>391ca1		09 e6 00 25 b5 00 00 00		INSTRUMENT_LASER      .text $09, $E6, $00, $25, $B5, $00, $00, $00, $00, $00, $00, $00, 'LASER     '
>391ca9		00 00 00 00 4c 41 53 45 52 20 20 20 20 20
>391cb7		00 32 44 f8 ff 00 0e 11		INSTRUMENT_LOGDRUM1   .text $00, $32, $44, $F8, $FF, $00, $0E, $11, $00, $F5, $7F, $00, 'LOGDRUM1  '
>391cbf		00 f5 7f 00 4c 4f 47 44 52 55 4d 31 20 20
>391ccd		00 05 4e da 25 00 0a 01		INSTRUMENT_MARIMBA1   .text $00, $05, $4E, $DA, $25, $00, $0A, $01, $00, $F9, $15, $00, 'MARIMBA1  '
>391cd5		00 f9 15 00 4d 41 52 49 4d 42 41 31 20 20
>391ce3		00 85 4e da 15 00 0a 81		INSTRUMENT_MARIMBA2   .text $00, $85, $4E, $DA, $15, $00, $0A, $81, $80, $F9, $13, $00, 'MARIMBA2  '
>391ceb		80 f9 13 00 4d 41 52 49 4d 42 41 32 20 20
>391cf9		00 30 00 fe 11 01 08 ae		INSTRUMENT_MDRNPHON   .text $00, $30, $00, $FE, $11, $01, $08, $AE, $C0, $F1, $19, $01, 'MDRNPHON  '
>391d01		c0 f1 19 01 4d 44 52 4e 50 48 4f 4e 20 20
>391d0f		07 0c 00 c8 b6 01 00 00		INSTRUMENT_MLTRDRUM   .text $07, $0C, $00, $C8, $B6, $01, $00, $00, $00, $00, $00, $00, 'MLTRDRUM  '
>391d17		00 00 00 00 4d 4c 54 52 44 52 55 4d 20 20
>391d25		00 20 90 f5 9e 02 0c 11		INSTRUMENT_MOOGSYNT   .text $00, $20, $90, $F5, $9E, $02, $0C, $11, $00, $F4, $5B, $03, 'MOOGSYNT  '
>391d2d		00 f4 5b 03 4d 4f 4f 47 53 59 4e 54 20 20
>391d3b		00 0e 40 d1 53 00 0e 0e		INSTRUMENT_NOISE1     .text $00, $0E, $40, $D1, $53, $00, $0E, $0E, $00, $F2, $7F, $03, 'NOISE1    '
>391d43		00 f2 7f 03 4e 4f 49 53 45 31 20 20 20 20
>391d51		00 b1 c5 6e 17 00 02 22		INSTRUMENT_OBOE1      .text $00, $B1, $C5, $6E, $17, $00, $02, $22, $05, $8B, $0E, $00, 'OBOE1     '
>391d59		05 8b 0e 00 4f 42 4f 45 31 20 20 20 20 20
>391d67		00 65 d2 81 03 00 02 71		INSTRUMENT_ORGAN1     .text $00, $65, $D2, $81, $03, $00, $02, $71, $80, $F1, $05, $00, 'ORGAN1    '
>391d6f		80 f1 05 00 4f 52 47 41 4e 31 20 20 20 20
>391d7d		00 24 80 ff 0f 00 01 21		INSTRUMENT_ORGAN2     .text $00, $24, $80, $FF, $0F, $00, $01, $21, $80, $FF, $0F, $00, 'ORGAN2    '
>391d85		80 ff 0f 00 4f 52 47 41 4e 32 20 20 20 20
>391d93		00 03 5b f0 1f 00 0a 01		INSTRUMENT_ORGAN3     .text $00, $03, $5B, $F0, $1F, $00, $0A, $01, $80, $F0, $1F, $00, 'ORGAN3    '
>391d9b		80 f0 1f 00 4f 52 47 41 4e 33 20 20 20 20
>391da9		00 03 5b f0 1f 00 0a 01		INSTRUMENT_ORGAN3A    .text $00, $03, $5B, $F0, $1F, $00, $0A, $01, $8D, $F0, $13, $00, 'ORGAN3A   '
>391db1		8d f0 13 00 4f 52 47 41 4e 33 41 20 20 20
>391dbf		00 03 5b f0 1f 00 0a 01		INSTRUMENT_ORGAN3B    .text $00, $03, $5B, $F0, $1F, $00, $0A, $01, $92, $F0, $12, $00, 'ORGAN3B   '
>391dc7		92 f0 12 00 4f 52 47 41 4e 33 42 20 20 20
>391dd5		00 0c 00 f8 b5 00 01 00		INSTRUMENT_ORGNPERC   .text $00, $0C, $00, $F8, $B5, $00, $01, $00, $00, $D6, $4F, $00, 'ORGNPERC  '
>391ddd		00 d6 4f 00 4f 52 47 4e 50 45 52 43 20 20
>391deb		00 17 4f f2 61 00 08 12		INSTRUMENT_PHONE1     .text $00, $17, $4F, $F2, $61, $00, $08, $12, $08, $F1, $B2, $00, 'PHONE1    '
>391df3		08 f1 b2 00 50 48 4f 4e 45 31 20 20 20 20
>391e01		00 17 4f f2 61 00 08 12		INSTRUMENT_PHONE2     .text $00, $17, $4F, $F2, $61, $00, $08, $12, $0A, $F1, $B4, $00, 'PHONE2    '
>391e09		0a f1 b4 00 50 48 4f 4e 45 32 20 20 20 20
>391e17		00 81 63 f3 58 00 00 01		INSTRUMENT_PIAN1A     .text $00, $81, $63, $F3, $58, $00, $00, $01, $80, $F2, $58, $00, 'PIAN1A    '
>391e1f		80 f2 58 00 50 49 41 4e 31 41 20 20 20 20
>391e2d		00 07 1f f5 fa 00 0e 01		INSTRUMENT_PIAN1B     .text $00, $07, $1F, $F5, $FA, $00, $0E, $01, $26, $F5, $FA, $00, 'PIAN1B    '
>391e35		26 f5 fa 00 50 49 41 4e 31 42 20 20 20 20
>391e43		00 07 1f f5 fa 00 0e 01		INSTRUMENT_PIAN1C     .text $00, $07, $1F, $F5, $FA, $00, $0E, $01, $57, $F5, $FA, $00, 'PIAN1C    '
>391e4b		57 f5 fa 00 50 49 41 4e 31 43 20 20 20 20
>391e59		00 03 4f f1 53 00 06 17		INSTRUMENT_PIANO      .text $00, $03, $4F, $F1, $53, $00, $06, $17, $00, $F2, $74, $00, 'PIANO     '
>391e61		00 f2 74 00 50 49 41 4e 4f 20 20 20 20 20
>391e6f		00 01 4f f1 53 00 06 11		INSTRUMENT_PIANO1     .text $00, $01, $4F, $F1, $53, $00, $06, $11, $00, $D2, $74, $00, 'PIANO1    '
>391e77		00 d2 74 00 50 49 41 4e 4f 31 20 20 20 20
>391e85		00 41 9d f2 51 00 06 13		INSTRUMENT_PIANO2     .text $00, $41, $9D, $F2, $51, $00, $06, $13, $00, $F2, $F1, $00, 'PIANO2    '
>391e8d		00 f2 f1 00 50 49 41 4e 4f 32 20 20 20 20
>391e9b		00 01 4f f1 50 00 06 01		INSTRUMENT_PIANO3     .text $00, $01, $4F, $F1, $50, $00, $06, $01, $04, $D2, $7C, $00, 'PIANO3    '
>391ea3		04 d2 7c 00 50 49 41 4e 4f 33 20 20 20 20
>391eb1		00 01 4d f1 60 00 08 11		INSTRUMENT_PIANO4     .text $00, $01, $4D, $F1, $60, $00, $08, $11, $00, $D2, $7B, $00, 'PIANO4    '
>391eb9		00 d2 7b 00 50 49 41 4e 4f 34 20 20 20 20
>391ec7		00 03 4f f1 53 00 06 17		INSTRUMENT_PIANOBEL   .text $00, $03, $4F, $F1, $53, $00, $06, $17, $03, $F2, $74, $00, 'PIANOBEL  '
>391ecf		03 f2 74 00 50 49 41 4e 4f 42 45 4c 20 20
>391edd		00 01 cf f1 53 00 02 12		INSTRUMENT_PIANOF     .text $00, $01, $CF, $F1, $53, $00, $02, $12, $00, $F2, $83, $00, 'PIANOF    '
>391ee5		00 f2 83 00 50 49 41 4e 4f 46 20 20 20 20
>391ef3		00 10 00 75 93 01 00 01		INSTRUMENT_POPBASS1   .text $00, $10, $00, $75, $93, $01, $00, $01, $00, $F5, $82, $01, 'POPBASS1  '
>391efb		00 f5 82 01 50 4f 50 42 41 53 53 31 20 20
>391f09		07 0c 00 c7 b4 00 00 00		INSTRUMENT_RKSNARE1   .text $07, $0C, $00, $C7, $B4, $00, $00, $00, $00, $00, $00, $00, 'RKSNARE1  '
>391f11		00 00 00 00 52 4b 53 4e 41 52 45 31 20 20
>391f1f		00 01 4f 71 53 00 0a 12		INSTRUMENT_SAX1       .text $00, $01, $4F, $71, $53, $00, $0A, $12, $00, $52, $7C, $00, 'SAX1      '
>391f27		00 52 7c 00 53 41 58 31 20 20 20 20 20 20
>391f35		00 07 00 f0 f0 00 0e 00		INSTRUMENT_SCRATCH    .text $00, $07, $00, $F0, $F0, $00, $0E, $00, $00, $5C, $DC, $00, 'SCRATCH   '
>391f3d		00 5c dc 00 53 43 52 41 54 43 48 20 20 20
>391f4b		00 07 00 f0 f0 00 0e 00		INSTRUMENT_SCRATCH4   .text $00, $07, $00, $F0, $F0, $00, $0E, $00, $00, $5C, $DC, $00, 'SCRATCH4  '
>391f53		00 5c dc 00 53 43 52 41 54 43 48 34 20 20
>391f61		00 06 00 f0 f0 00 0e 00		INSTRUMENT_SDRUM2     .text $00, $06, $00, $F0, $F0, $00, $0E, $00, $00, $F6, $B4, $00, 'SDRUM2    '
>391f69		00 f6 b4 00 53 44 52 55 4d 32 20 20 20 20
>391f77		00 e4 0e ff 3f 01 00 c0		INSTRUMENT_SHRTVIBE   .text $00, $E4, $0E, $FF, $3F, $01, $00, $C0, $00, $F3, $07, $00, 'SHRTVIBE  '
>391f7f		00 f3 07 00 53 48 52 54 56 49 42 45 20 20
>391f8d		00 01 40 f1 53 00 00 08		INSTRUMENT_SITAR1     .text $00, $01, $40, $F1, $53, $00, $00, $08, $40, $F1, $53, $00, 'SITAR1    '
>391f95		40 f1 53 00 53 49 54 41 52 31 20 20 20 20
>391fa3		00 01 40 f1 53 00 00 08		INSTRUMENT_SITAR2     .text $00, $01, $40, $F1, $53, $00, $00, $08, $40, $F1, $53, $01, 'SITAR2    '
>391fab		40 f1 53 01 53 49 54 41 52 32 20 20 20 20
>391fb9		00 61 0c 81 03 00 08 71		INSTRUMENT_SNAKEFL    .text $00, $61, $0C, $81, $03, $00, $08, $71, $80, $61, $0C, $00, 'SNAKEFL   '
>391fc1		80 61 0c 00 53 4e 41 4b 45 46 4c 20 20 20
>391fcf		07 0c 00 f8 b5 00 00 00		INSTRUMENT_SNARE1     .text $07, $0C, $00, $F8, $B5, $00, $00, $00, $00, $00, $00, $00, 'SNARE1    '
>391fd7		00 00 00 00 53 4e 41 52 45 31 20 20 20 20
>391fe5		00 06 00 f0 f0 00 0e c4		INSTRUMENT_SNRSUST    .text $00, $06, $00, $F0, $F0, $00, $0E, $C4, $03, $C4, $34, $00, 'SNRSUST   '
>391fed		03 c4 34 00 53 4e 52 53 55 53 54 20 20 20
>391ffb		00 70 1c 51 03 02 0e 20		INSTRUMENT_SOLOVLN    .text $00, $70, $1C, $51, $03, $02, $0E, $20, $00, $54, $67, $02, 'SOLOVLN   '
>392003		00 54 67 02 53 4f 4c 4f 56 4c 4e 20 20 20
>392011		00 01 46 f1 83 00 06 61		INSTRUMENT_STEELGT1   .text $00, $01, $46, $F1, $83, $00, $06, $61, $03, $31, $86, $00, 'STEELGT1  '
>392019		03 31 86 00 53 54 45 45 4c 47 54 31 20 20
>392027		00 01 47 f1 83 00 06 61		INSTRUMENT_STEELGT2   .text $00, $01, $47, $F1, $83, $00, $06, $61, $03, $91, $86, $00, 'STEELGT2  '
>39202f		03 91 86 00 53 54 45 45 4c 47 54 32 20 20
>39203d		00 b1 8b 71 11 00 06 61		INSTRUMENT_STRINGS1   .text $00, $B1, $8B, $71, $11, $00, $06, $61, $40, $42, $15, $01, 'STRINGS1  '
>392045		40 42 15 01 53 54 52 49 4e 47 53 31 20 20
>392053		00 e1 4f b1 d3 03 06 21		INSTRUMENT_STRNLONG   .text $00, $E1, $4F, $B1, $D3, $03, $06, $21, $00, $12, $74, $01, 'STRNLONG  '
>39205b		00 12 74 01 53 54 52 4e 4c 4f 4e 47 20 20
>392069		00 55 97 2a 02 00 00 12		INSTRUMENT_SYN1       .text $00, $55, $97, $2A, $02, $00, $00, $12, $80, $42, $F3, $00, 'SYN1      '
>392071		80 42 f3 00 53 59 4e 31 20 20 20 20 20 20
>39207f		00 13 97 9a 12 00 0e 11		INSTRUMENT_SYN2       .text $00, $13, $97, $9A, $12, $00, $0E, $11, $80, $9B, $14, $00, 'SYN2      '
>392087		80 9b 14 00 53 59 4e 32 20 20 20 20 20 20
>392095		00 11 8a f1 11 00 06 01		INSTRUMENT_SYN3       .text $00, $11, $8A, $F1, $11, $00, $06, $01, $40, $F1, $B3, $00, 'SYN3      '
>39209d		40 f1 b3 00 53 59 4e 33 20 20 20 20 20 20
>3920ab		00 21 0d e9 3a 00 0a 22		INSTRUMENT_SYN4       .text $00, $21, $0D, $E9, $3A, $00, $0A, $22, $80, $65, $6C, $00, 'SYN4      '
>3920b3		80 65 6c 00 53 59 4e 34 20 20 20 20 20 20
>3920c1		00 01 4f 71 53 00 06 19		INSTRUMENT_SYN5       .text $00, $01, $4F, $71, $53, $00, $06, $19, $00, $52, $7C, $00, 'SYN5      '
>3920c9		00 52 7c 00 53 59 4e 35 20 20 20 20 20 20
>3920d7		00 24 0f 41 7e 00 0a 21		INSTRUMENT_SYN6       .text $00, $24, $0F, $41, $7E, $00, $0A, $21, $00, $F1, $5E, $00, 'SYN6      '
>3920df		00 f1 5e 00 53 59 4e 36 20 20 20 20 20 20
>3920ed		00 07 87 f0 05 00 04 01		INSTRUMENT_SYN9       .text $00, $07, $87, $F0, $05, $00, $04, $01, $80, $F0, $05, $00, 'SYN9      '
>3920f5		80 f0 05 00 53 59 4e 39 20 20 20 20 20 20
>392103		00 26 03 e0 f0 00 08 1e		INSTRUMENT_SYNBAL1    .text $00, $26, $03, $E0, $F0, $00, $08, $1E, $00, $FF, $31, $00, 'SYNBAL1   '
>39210b		00 ff 31 00 53 59 4e 42 41 4c 31 20 20 20
>392119		00 28 03 e0 f0 00 04 13		INSTRUMENT_SYNBAL2    .text $00, $28, $03, $E0, $F0, $00, $04, $13, $00, $E8, $11, $00, 'SYNBAL2   '
>392121		00 e8 11 00 53 59 4e 42 41 4c 32 20 20 20
>39212f		00 30 88 d5 19 00 0c 71		INSTRUMENT_SYNBASS1   .text $00, $30, $88, $D5, $19, $00, $0C, $71, $80, $61, $1B, $00, 'SYNBASS1  '
>392137		80 61 1b 00 53 59 4e 42 41 53 53 31 20 20
>392145		00 81 86 65 01 00 0c 11		INSTRUMENT_SYNBASS2   .text $00, $81, $86, $65, $01, $00, $0C, $11, $00, $32, $74, $00, 'SYNBASS2  '
>39214d		00 32 74 00 53 59 4e 42 41 53 53 32 20 20
>39215b		00 81 83 65 05 00 0a 51		INSTRUMENT_SYNBASS4   .text $00, $81, $83, $65, $05, $00, $0A, $51, $00, $32, $74, $00, 'SYNBASS4  '
>392163		00 32 74 00 53 59 4e 42 41 53 53 34 20 20
>392171		00 06 00 f0 f0 00 0e 00		INSTRUMENT_SYNSNR1    .text $00, $06, $00, $F0, $F0, $00, $0E, $00, $00, $F8, $B6, $00, 'SYNSNR1   '
>392179		00 f8 b6 00 53 59 4e 53 4e 52 31 20 20 20
>392187		00 06 00 f0 f0 00 0e 00		INSTRUMENT_SYNSNR2    .text $00, $06, $00, $F0, $F0, $00, $0E, $00, $00, $F6, $B4, $00, 'SYNSNR2   '
>39218f		00 f6 b4 00 53 59 4e 53 4e 52 32 20 20 20
>39219d		00 8f 81 ef 01 00 04 01		INSTRUMENT_TINCAN1    .text $00, $8F, $81, $EF, $01, $00, $04, $01, $00, $98, $F1, $00, 'TINCAN1   '
>3921a5		00 98 f1 00 54 49 4e 43 41 4e 31 20 20 20
>3921b3		08 04 00 f7 b5 00 00 00		INSTRUMENT_TOM1       .text $08, $04, $00, $F7, $B5, $00, $00, $00, $00, $00, $00, $00, 'TOM1      '
>3921bb		00 00 00 00 54 4f 4d 31 20 20 20 20 20 20
>3921c9		08 02 00 c8 97 00 00 00		INSTRUMENT_TOM2       .text $08, $02, $00, $C8, $97, $00, $00, $00, $00, $00, $00, $00, 'TOM2      '
>3921d1		00 00 00 00 54 4f 4d 32 20 20 20 20 20 20
>3921df		00 17 4f f2 61 00 08 12		INSTRUMENT_TRAINBEL   .text $00, $17, $4F, $F2, $61, $00, $08, $12, $08, $F2, $74, $00, 'TRAINBEL  '
>3921e7		08 f2 74 00 54 52 41 49 4e 42 45 4c 20 20
>3921f5		00 26 03 e0 f0 00 08 1e		INSTRUMENT_TRIANGLE   .text $00, $26, $03, $E0, $F0, $00, $08, $1E, $00, $FF, $31, $00, 'TRIANGLE  '
>3921fd		00 ff 31 00 54 52 49 41 4e 47 4c 45 20 20
>39220b		00 b1 1c 41 1f 00 0e 61		INSTRUMENT_TROMB1     .text $00, $B1, $1C, $41, $1F, $00, $0E, $61, $80, $92, $3B, $00, 'TROMB1    '
>392213		80 92 3b 00 54 52 4f 4d 42 31 20 20 20 20
>392221		00 21 1c 53 1d 00 0c 61		INSTRUMENT_TROMB2     .text $00, $21, $1C, $53, $1D, $00, $0C, $61, $80, $52, $3B, $00, 'TROMB2    '
>392229		80 52 3b 00 54 52 4f 4d 42 32 20 20 20 20
>392237		00 31 1c 41 0b 00 0e 61		INSTRUMENT_TRUMPET1   .text $00, $31, $1C, $41, $0B, $00, $0E, $61, $80, $92, $3B, $00, 'TRUMPET1  '
>39223f		80 92 3b 00 54 52 55 4d 50 45 54 31 20 20
>39224d		00 31 1c 23 1d 00 0c 61		INSTRUMENT_TRUMPET2   .text $00, $31, $1C, $23, $1D, $00, $0C, $61, $80, $52, $3B, $00, 'TRUMPET2  '
>392255		80 52 3b 00 54 52 55 4d 50 45 54 32 20 20
>392263		00 31 1c 41 01 00 0e 61		INSTRUMENT_TRUMPET3   .text $00, $31, $1C, $41, $01, $00, $0E, $61, $80, $92, $3B, $00, 'TRUMPET3  '
>39226b		80 92 3b 00 54 52 55 4d 50 45 54 33 20 20
>392279		00 31 1c 41 0b 00 0c 61		INSTRUMENT_TRUMPET4   .text $00, $31, $1C, $41, $0B, $00, $0C, $61, $80, $92, $3B, $00, 'TRUMPET4  '
>392281		80 92 3b 00 54 52 55 4d 50 45 54 34 20 20
>39228f		00 21 19 43 8c 00 0c 21		INSTRUMENT_TUBA1      .text $00, $21, $19, $43, $8C, $00, $0C, $21, $80, $85, $2F, $00, 'TUBA1     '
>392297		80 85 2f 00 54 55 42 41 31 20 20 20 20 20
>3922a5		00 84 53 f5 33 00 06 a0		INSTRUMENT_VIBRA1     .text $00, $84, $53, $F5, $33, $00, $06, $A0, $80, $FD, $25, $00, 'VIBRA1    '
>3922ad		80 fd 25 00 56 49 42 52 41 31 20 20 20 20
>3922bb		00 06 73 f6 54 00 00 81		INSTRUMENT_VIBRA2     .text $00, $06, $73, $F6, $54, $00, $00, $81, $03, $F2, $B3, $00, 'VIBRA2    '
>3922c3		03 f2 b3 00 56 49 42 52 41 32 20 20 20 20
>3922d1		00 93 97 aa 12 02 0e 91		INSTRUMENT_VIBRA3     .text $00, $93, $97, $AA, $12, $02, $0E, $91, $80, $AC, $21, $00, 'VIBRA3    '
>3922d9		80 ac 21 00 56 49 42 52 41 33 20 20 20 20
>3922e7		00 31 1c 51 03 00 0e 61		INSTRUMENT_VIOLIN1    .text $00, $31, $1C, $51, $03, $00, $0E, $61, $80, $54, $67, $00, 'VIOLIN1   '
>3922ef		80 54 67 00 56 49 4f 4c 49 4e 31 20 20 20
>3922fd		00 e1 88 62 29 00 0c 22		INSTRUMENT_VIOLIN2    .text $00, $E1, $88, $62, $29, $00, $0C, $22, $80, $53, $2C, $00, 'VIOLIN2   '
>392305		80 53 2c 00 56 49 4f 4c 49 4e 32 20 20 20
>392313		00 e1 88 64 29 00 06 22		INSTRUMENT_VIOLIN3    .text $00, $E1, $88, $64, $29, $00, $06, $22, $83, $53, $2C, $00, 'VIOLIN3   '
>39231b		83 53 2c 00 56 49 4f 4c 49 4e 33 20 20 20
>392329		00 31 9c f1 f9 00 0e 31		INSTRUMENT_VLNPIZZ1   .text $00, $31, $9C, $F1, $F9, $00, $0E, $31, $80, $F7, $E6, $00, 'VLNPIZZ1  '
>392331		80 f7 e6 00 56 4c 4e 50 49 5a 5a 31 20 20
>39233f		00 00 02 00 f0 00 0e 14		INSTRUMENT_WAVE       .text $00, $00, $02, $00, $F0, $00, $0E, $14, $80, $1B, $A2, $00, 'WAVE      '
>392347		80 1b a2 00 57 41 56 45 20 20 20 20 20 20
>392355		00 11 2d c8 2f 00 0c 31		INSTRUMENT_XYLO1      .text $00, $11, $2D, $C8, $2F, $00, $0C, $31, $00, $F5, $F5, $00, 'XYLO1     '
>39235d		00 f5 f5 00 58 59 4c 4f 31 20 20 20 20 20
>39236b		06 2e 00 ff 0f 00 00 00		INSTRUMENT_XYLO2      .text $06, $2E, $00, $FF, $0F, $00, $00, $00, $00, $00, $00, $00, 'XYLO2     '
>392373		00 00 00 00 58 59 4c 4f 32 20 20 20 20 20
>392381		00 06 00 ff f0 00 0e c4		INSTRUMENT_XYLO3      .text $00, $06, $00, $FF, $F0, $00, $0E, $C4, $00, $F8, $B5, $00, 'XYLO3     '
>392389		00 f8 b5 00 58 59 4c 4f 33 20 20 20 20 20

;******  Return to file: src\OPL2_Library.asm


;******  Processing file: src\OPL2_Midi_Drums.asm

>392397		00 3e 00 9f 0f 0f 00 30		DRUMINS_CLAP2         .text $00, $3E, $00, $9F, $0F, $0F, $00, $30, $00, $87, $FA, $00
>39239f		00 87 fa 00
>3923a3		00 01 00 78 97 09 00 02		DRUMINS_SCRATCH1      .text $00, $01, $00, $78, $97, $09, $00, $02, $00, $88, $98, $03
>3923ab		00 88 98 03
>3923af		00 01 00 78 97 09 00 02		DRUMINS_SCRATCH2      .text $00, $01, $00, $78, $97, $09, $00, $02, $00, $88, $98, $03
>3923b7		00 88 98 03
>3923bb		00 16 08 f1 fb 01 00 11		DRUMINS_RIMSHOT2      .text $00, $16, $08, $F1, $FB, $01, $00, $11, $00, $F9, $69, $00
>3923c3		00 f9 69 00
>3923c7		00 00 00 f8 6c 01 00 0e		DRUMINS_HIQ           .text $00, $00, $00, $F8, $6C, $01, $00, $0E, $80, $E8, $4A, $00
>3923cf		80 e8 4a 00
>3923d3		00 25 1b fa f2 01 00 12		DRUMINS_WOODBLOK      .text $00, $25, $1B, $FA, $F2, $01, $00, $12, $00, $F6, $9A, $00
>3923db		00 f6 9a 00
>3923df		00 06 03 f4 44 00 01 01		DRUMINS_GLOCK         .text $00, $06, $03, $F4, $44, $00, $01, $01, $1B, $F2, $34, $00
>3923e7		1b f2 34 00
>3923eb		00 00 00 f9 f3 05 00 01		DRUMINS_BASS_DR2      .text $00, $00, $00, $F9, $F3, $05, $00, $01, $00, $F7, $8A, $00
>3923f3		00 f7 8a 00
>3923f7		00 01 07 fa fd 05 00 01		DRUMINS_BASS_DR1      .text $00, $01, $07, $FA, $FD, $05, $00, $01, $00, $F6, $47, $00
>3923ff		00 f6 47 00
>392403		00 16 08 f1 fb 01 00 11		DRUMINS_RIMSHOT       .text $00, $16, $08, $F1, $FB, $01, $00, $11, $00, $F9, $69, $00
>39240b		00 f9 69 00
>39240f		00 24 00 ff 00 0f 00 02		DRUMINS_SNARE_AC      .text $00, $24, $00, $FF, $00, $0F, $00, $02, $00, $F7, $A9, $00
>392417		00 f7 a9 00
>39241b		00 3e 00 9f 0f 0f 00 30		DRUMINS_CLAP          .text $00, $3E, $00, $9F, $0F, $0F, $00, $30, $00, $87, $FA, $00
>392423		00 87 fa 00
>392427		00 24 00 ff 00 0f 00 02		DRUMINS_SNARE_EL      .text $00, $24, $00, $FF, $00, $0F, $00, $02, $00, $F7, $A9, $00
>39242f		00 f7 a9 00
>392433		00 06 0a fa 1f 0c 00 11		DRUMINS_LO_TOMS       .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
>39243b		00 f5 f5 00
>39243f		00 2c 00 f2 fe 07 00 02		DRUMINS_HIHAT_CL      .text $00, $2C, $00, $F2, $FE, $07, $00, $02, $06, $B8, $D8, $03
>392447		06 b8 d8 03
>39244b		00 06 0a fa 1f 0c 00 11		DRUMINS_HI_TOMS       .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
>392453		00 f5 f5 00
>392457		00 2c 00 f2 fe 07 00 02		DRUMINS_HIHAT_PL      .text $00, $2C, $00, $F2, $FE, $07, $00, $02, $06, $B8, $D8, $03
>39245f		06 b8 d8 03
>392463		00 06 0a fa 1f 0c 00 11		DRUMINS_LOW_TOM       .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
>39246b		00 f5 f5 00
>39246f		00 2e 00 82 f6 05 00 04		DRUMINS_HIHAT_OP      .text $00, $2E, $00, $82, $F6, $05, $00, $04, $10, $74, $F8, $03
>392477		10 74 f8 03
>39247b		00 06 0a fa 1f 0c 00 11		DRUMINS_LTOM_MID      .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
>392483		00 f5 f5 00
>392487		00 06 0a fa 1f 0c 00 11		DRUMINS_HTOM_MID      .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
>39248f		00 f5 f5 00
>392493		00 2c 00 9f 00 0f 02 0e		DRUMINS_CRASH         .text $00, $2C, $00, $9F, $00, $0F, $02, $0E, $05, $C5, $D4, $03
>39249b		05 c5 d4 03
>39249f		00 06 0a fa 1f 0c 00 11		DRUMINS_TOM_HIGH      .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
>3924a7		00 f5 f5 00
>3924ab		00 29 10 94 00 0f 00 04		DRUMINS_RIDE_CY       .text $00, $29, $10, $94, $00, $0F, $00, $04, $04, $F9, $44, $03
>3924b3		04 f9 44 03
>3924b7		00 2c 00 9f 00 0f 02 0e		DRUMINS_TAMBOUR       .text $00, $2C, $00, $9F, $00, $0F, $02, $0E, $05, $C5, $D4, $03
>3924bf		05 c5 d4 03
>3924c3		00 29 10 94 00 0f 00 04		DRUMINS_CYMBAL        .text $00, $29, $10, $94, $00, $0F, $00, $04, $04, $F9, $44, $03
>3924cb		04 f9 44 03
>3924cf		00 2e 09 f5 f1 01 00 06		DRUMINS_TAMBOU2       .text $00, $2E, $09, $F5, $F1, $01, $00, $06, $03, $87, $F7, $03
>3924d7		03 87 f7 03
>3924db		00 2c 00 9f 00 0f 02 0e		DRUMINS_SPLASH        .text $00, $2C, $00, $9F, $00, $0F, $02, $0E, $05, $C5, $D4, $03
>3924e3		05 c5 d4 03
>3924e7		00 37 14 f7 a1 09 01 03		DRUMINS_COWBELL       .text $00, $37, $14, $F7, $A1, $09, $01, $03, $00, $F6, $28, $00
>3924ef		00 f6 28 00
>3924f3		00 2c 00 9f 00 0f 02 0e		DRUMINS_CRASH2        .text $00, $2C, $00, $9F, $00, $0F, $02, $0E, $05, $C5, $D4, $03
>3924fb		05 c5 d4 03
>3924ff		00 80 00 ff 00 0d 01 00		DRUMINS_VIBRASLA      .text $00, $80, $00, $FF, $00, $0D, $01, $00, $00, $F5, $F7, $01
>392507		00 f5 f7 01
>39250b		00 29 10 94 00 0f 00 04		DRUMINS_RIDE2         .text $00, $29, $10, $94, $00, $0F, $00, $04, $04, $F9, $44, $03
>392513		04 f9 44 03
>392517		00 25 c4 fa fa 01 00 03		DRUMINS_HI_BONGO      .text $00, $25, $C4, $FA, $FA, $01, $00, $03, $00, $99, $F9, $00
>39251f		00 99 f9 00
>392523		00 21 03 fb fa 01 01 02		DRUMINS_LO_BONGO      .text $00, $21, $03, $FB, $FA, $01, $01, $02, $00, $A8, $F7, $00
>39252b		00 a8 f7 00
>39252f		00 25 c4 fa fa 01 00 03		DRUMINS_MUTECONG      .text $00, $25, $C4, $FA, $FA, $01, $00, $03, $00, $99, $F9, $00
>392537		00 99 f9 00
>39253b		00 24 18 f9 fa 0f 02 03		DRUMINS_OPENCONG      .text $00, $24, $18, $F9, $FA, $0F, $02, $03, $00, $A6, $F6, $00
>392543		00 a6 f6 00
>392547		00 24 18 f9 fa 0f 02 03		DRUMINS_LOWCONGA      .text $00, $24, $18, $F9, $FA, $0F, $02, $03, $00, $A6, $F6, $00
>39254f		00 a6 f6 00
>392553		00 05 14 f5 f5 07 02 03		DRUMINS_HI_TIMBA      .text $00, $05, $14, $F5, $F5, $07, $02, $03, $00, $F6, $36, $02
>39255b		00 f6 36 02
>39255f		00 05 14 f5 f5 07 02 03		DRUMINS_LO_TIMBA      .text $00, $05, $14, $F5, $F5, $07, $02, $03, $00, $F6, $36, $02
>392567		00 f6 36 02
>39256b		00 1c 0c f9 31 0f 01 15		DRUMINS_HI_AGOGO      .text $00, $1C, $0C, $F9, $31, $0F, $01, $15, $00, $96, $E8, $01
>392573		00 96 e8 01
>392577		00 1c 0c f9 31 0f 01 15		DRUMINS_LO_AGOGO      .text $00, $1C, $0C, $F9, $31, $0F, $01, $15, $00, $96, $E8, $01
>39257f		00 96 e8 01
>392583		00 0e 00 ff 01 0f 00 0e		DRUMINS_CABASA        .text $00, $0E, $00, $FF, $01, $0F, $00, $0E, $02, $79, $77, $03
>39258b		02 79 77 03
>39258f		00 0e 00 ff 01 0f 00 0e		DRUMINS_MARACAS       .text $00, $0E, $00, $FF, $01, $0F, $00, $0E, $02, $79, $77, $03
>392597		02 79 77 03
>39259b		00 20 15 af 07 05 01 0e		DRUMINS_S_WHISTL      .text $00, $20, $15, $AF, $07, $05, $01, $0E, $00, $A5, $2B, $02
>3925a3		00 a5 2b 02
>3925a7		00 20 18 bf 07 01 01 0e		DRUMINS_L_WHISTL      .text $00, $20, $18, $BF, $07, $01, $01, $0E, $00, $93, $3B, $02
>3925af		00 93 3b 02
>3925b3		00 20 00 f0 f7 0b 00 08		DRUMINS_S_GUIRO       .text $00, $20, $00, $F0, $F7, $0B, $00, $08, $01, $89, $3B, $03
>3925bb		01 89 3b 03
>3925bf		00 20 00 f3 fa 09 00 08		DRUMINS_L_GUIRO       .text $00, $20, $00, $F3, $FA, $09, $00, $08, $0A, $53, $2B, $02
>3925c7		0a 53 2b 02
>3925cb		00 15 21 f8 9a 09 01 13		DRUMINS_CLAVES        .text $00, $15, $21, $F8, $9A, $09, $01, $13, $00, $F6, $89, $00
>3925d3		00 f6 89 00
>3925d7		00 25 1b fa f2 01 00 12		DRUMINS_HI_WDBLK      .text $00, $25, $1B, $FA, $F2, $01, $00, $12, $00, $F6, $9A, $00
>3925df		00 f6 9a 00
>3925e3		00 25 1b fa f2 01 00 12		DRUMINS_LO_WDBLK      .text $00, $25, $1B, $FA, $F2, $01, $00, $12, $00, $F6, $9A, $00
>3925eb		00 f6 9a 00
>3925ef		00 20 01 5f 07 01 00 08		DRUMINS_MU_CUICA      .text $00, $20, $01, $5F, $07, $01, $00, $08, $00, $87, $4B, $01
>3925f7		00 87 4b 01
>3925fb		00 25 12 57 f7 01 01 03		DRUMINS_OP_CUICA      .text $00, $25, $12, $57, $F7, $01, $01, $03, $00, $78, $67, $01
>392603		00 78 67 01
>392607		00 22 2f f1 f0 07 00 27		DRUMINS_MU_TRNGL      .text $00, $22, $2F, $F1, $F0, $07, $00, $27, $02, $F8, $FC, $00
>39260f		02 f8 fc 00
>392613		00 26 44 f1 f0 07 00 27		DRUMINS_OP_TRNGL      .text $00, $26, $44, $F1, $F0, $07, $00, $27, $40, $F5, $F5, $00
>39261b		40 f5 f5 00
>39261f		00 0e 00 ff 01 0f 00 0e		DRUMINS_SHAKER        .text $00, $0E, $00, $FF, $01, $0F, $00, $0E, $02, $79, $77, $03
>392627		02 79 77 03
>39262b		00 26 44 f1 f0 07 00 27		DRUMINS_TRIANGL1      .text $00, $26, $44, $F1, $F0, $07, $00, $27, $40, $F5, $F5, $00
>392633		40 f5 f5 00
>392637		00 26 44 f1 f0 07 00 27		DRUMINS_TRIANGL2      .text $00, $26, $44, $F1, $F0, $07, $00, $27, $40, $F5, $F5, $00
>39263f		40 f5 f5 00
>392643		00 16 08 f1 fb 01 00 11		DRUMINS_RIMSHOT3      .text $00, $16, $08, $F1, $FB, $01, $00, $11, $00, $F9, $69, $00
>39264b		00 f9 69 00
>39264f		00 16 08 f1 fb 01 00 11		DRUMINS_RIMSHOT4      .text $00, $16, $08, $F1, $FB, $01, $00, $11, $00, $F9, $69, $00
>392657		00 f9 69 00
>39265b		00 02 1d f5 93 01 00 00		DRUMINS_TAIKO         .text $00, $02, $1D, $F5, $93, $01, $00, $00, $00, $C6, $45, $00
>392663		00 c6 45 00
=27						DRUM_NOTE_BASE = 27;
=60						NUM_MIDI_DRUMS = 60;
>392667		97 23 39 00 a3 23 39 00		midiDrums     .dword DRUMINS_CLAP2, DRUMINS_SCRATCH1, DRUMINS_SCRATCH2, DRUMINS_RIMSHOT2
>39266f		af 23 39 00 bb 23 39 00
>392677		c7 23 39 00 d3 23 39 00		              .dword DRUMINS_HIQ, DRUMINS_WOODBLOK, DRUMINS_GLOCK, DRUMINS_BASS_DR2
>39267f		df 23 39 00 eb 23 39 00
>392687		f7 23 39 00 03 24 39 00		              .dword DRUMINS_BASS_DR1, DRUMINS_RIMSHOT,  DRUMINS_SNARE_AC, DRUMINS_CLAP
>39268f		0f 24 39 00 1b 24 39 00
>392697		27 24 39 00 33 24 39 00		              .dword DRUMINS_SNARE_EL, DRUMINS_LO_TOMS,  DRUMINS_HIHAT_CL, DRUMINS_HI_TOMS
>39269f		3f 24 39 00 4b 24 39 00
>3926a7		57 24 39 00 63 24 39 00		              .dword DRUMINS_HIHAT_PL, DRUMINS_LOW_TOM,	DRUMINS_HIHAT_OP, DRUMINS_LTOM_MID
>3926af		6f 24 39 00 7b 24 39 00
>3926b7		87 24 39 00 93 24 39 00		              .dword DRUMINS_HTOM_MID, DRUMINS_CRASH,    DRUMINS_TOM_HIGH, DRUMINS_RIDE_CY
>3926bf		9f 24 39 00 ab 24 39 00
>3926c7		b7 24 39 00 c3 24 39 00		              .dword DRUMINS_TAMBOUR,  DRUMINS_CYMBAL,   DRUMINS_TAMBOU2,  DRUMINS_SPLASH
>3926cf		cf 24 39 00 db 24 39 00
>3926d7		e7 24 39 00 f3 24 39 00		              .dword DRUMINS_COWBELL,  DRUMINS_CRASH2, 	DRUMINS_VIBRASLA, DRUMINS_RIDE2
>3926df		ff 24 39 00 0b 25 39 00
>3926e7		17 25 39 00 23 25 39 00		              .dword DRUMINS_HI_BONGO, DRUMINS_LO_BONGO, DRUMINS_MUTECONG, DRUMINS_OPENCONG
>3926ef		2f 25 39 00 3b 25 39 00
>3926f7		47 25 39 00 53 25 39 00		              .dword DRUMINS_LOWCONGA, DRUMINS_HI_TIMBA, DRUMINS_LO_TIMBA, DRUMINS_HI_AGOGO
>3926ff		5f 25 39 00 6b 25 39 00
>392707		77 25 39 00 83 25 39 00		              .dword DRUMINS_LO_AGOGO, DRUMINS_CABASA, DRUMINS_MARACAS,  DRUMINS_S_WHISTL
>39270f		8f 25 39 00 9b 25 39 00
>392717		a7 25 39 00 b3 25 39 00		              .dword DRUMINS_L_WHISTL, DRUMINS_S_GUIRO,  DRUMINS_L_GUIRO,  DRUMINS_CLAVES
>39271f		bf 25 39 00 cb 25 39 00
>392727		d7 25 39 00 e3 25 39 00		              .dword DRUMINS_HI_WDBLK, DRUMINS_LO_WDBLK, DRUMINS_MU_CUICA, DRUMINS_OP_CUICA
>39272f		ef 25 39 00 fb 25 39 00
>392737		07 26 39 00 13 26 39 00		              .dword DRUMINS_MU_TRNGL, DRUMINS_OP_TRNGL, DRUMINS_SHAKER, DRUMINS_TRIANGL1
>39273f		1f 26 39 00 2b 26 39 00
>392747		37 26 39 00 43 26 39 00		              .dword DRUMINS_TRIANGL2, DRUMINS_RIMSHOT3, DRUMINS_RIMSHOT4, DRUMINS_TAIKO
>39274f		4f 26 39 00 5b 26 39 00

;******  Return to file: src\OPL2_Library.asm


;******  Processing file: src\OPL2_Midi_Instruments.asm

>392757		00 33 5a b2 50 01 00 31		MIDI_INSTRUMENT_PIANO1     .text $00, $33, $5A, $B2, $50, $01, $00, $31, $00, $B1, $F5, $01
>39275f		00 b1 f5 01
>392763		00 31 49 f2 53 07 01 11		MIDI_INSTRUMENT_PIANO2     .text $00, $31, $49, $F2, $53, $07, $01, $11, $03, $F1, $F5, $00
>39276b		03 f1 f5 00
>39276f		00 31 95 d1 83 0d 01 32		MIDI_INSTRUMENT_PIANO3     .text $00, $31, $95, $D1, $83, $0D, $01, $32, $03, $C1, $F5, $00
>392777		03 c1 f5 00
>39277b		00 34 9b f3 63 01 01 11		MIDI_INSTRUMENT_HONKTONK   .text $00, $34, $9B, $F3, $63, $01, $01, $11, $00, $92, $F5, $01
>392783		00 92 f5 01
>392787		00 27 28 f8 b7 01 02 91		MIDI_INSTRUMENT_EP1        .text $00, $27, $28, $F8, $B7, $01, $02, $91, $00, $F1, $F9, $00
>39278f		00 f1 f9 00
>392793		00 1a 2d f3 ee 01 01 11		MIDI_INSTRUMENT_EP2        .text $00, $1A, $2D, $F3, $EE, $01, $01, $11, $00, $F1, $F5, $00
>39279b		00 f1 f5 00
>39279f		00 35 95 f2 58 0f 01 32		MIDI_INSTRUMENT_HARPSIC    .text $00, $35, $95, $F2, $58, $0F, $01, $32, $02, $81, $F6, $01
>3927a7		02 81 f6 01
>3927ab		00 31 85 c9 40 01 00 35		MIDI_INSTRUMENT_CLAVIC     .text $00, $31, $85, $C9, $40, $01, $00, $35, $00, $C2, $B9, $01
>3927b3		00 c2 b9 01
>3927b7		00 09 15 c7 64 08 00 01		MIDI_INSTRUMENT_CELESTA    .text $00, $09, $15, $C7, $64, $08, $00, $01, $05, $B2, $35, $00
>3927bf		05 b2 35 00
>3927c3		00 06 03 f4 44 00 01 01		MIDI_INSTRUMENT_GLOCK      .text $00, $06, $03, $F4, $44, $00, $01, $01, $1B, $F2, $34, $00
>3927cb		1b f2 34 00
>3927cf		00 04 06 a9 24 0a 01 01		MIDI_INSTRUMENT_MUSICBOX   .text $00, $04, $06, $A9, $24, $0A, $01, $01, $01, $F5, $74, $00
>3927d7		01 f5 74 00
>3927db		00 d4 00 f6 33 00 00 f1		MIDI_INSTRUMENT_VIBES      .text $00, $D4, $00, $F6, $33, $00, $00, $F1, $00, $61, $E3, $00
>3927e3		00 61 e3 00
>3927e7		00 d4 00 f7 e8 04 00 d1		MIDI_INSTRUMENT_MARIMBA    .text $00, $D4, $00, $F7, $E8, $04, $00, $D1, $00, $A4, $64, $00
>3927ef		00 a4 64 00
>3927f3		00 36 16 f7 f7 01 00 31		MIDI_INSTRUMENT_XYLO       .text $00, $36, $16, $F7, $F7, $01, $00, $31, $07, $B5, $F5, $00
>3927fb		07 b5 f5 00
>3927ff		00 03 1b a2 43 0b 00 00		MIDI_INSTRUMENT_TUBEBELL   .text $00, $03, $1B, $A2, $43, $0B, $00, $00, $00, $F3, $74, $00
>392807		00 f3 74 00
>39280b		00 c3 8e f8 35 01 01 11		MIDI_INSTRUMENT_SANTUR     .text $00, $C3, $8E, $F8, $35, $01, $01, $11, $00, $C3, $94, $01
>392813		00 c3 94 01
>392817		00 e2 07 f4 1b 06 01 e0		MIDI_INSTRUMENT_ORGAN1     .text $00, $E2, $07, $F4, $1B, $06, $01, $E0, $00, $F4, $0D, $01
>39281f		00 f4 0d 01
>392823		00 f2 00 f6 2c 04 00 f0		MIDI_INSTRUMENT_ORGAN2     .text $00, $F2, $00, $F6, $2C, $04, $00, $F0, $00, $F5, $0B, $01
>39282b		00 f5 0b 01
>39282f		00 f1 06 b6 15 0a 00 f0		MIDI_INSTRUMENT_ORGAN3     .text $00, $F1, $06, $B6, $15, $0A, $00, $F0, $00, $BF, $07, $00
>392837		00 bf 07 00
>39283b		00 22 03 79 16 08 01 e0		MIDI_INSTRUMENT_PIPEORG    .text $00, $22, $03, $79, $16, $08, $01, $E0, $00, $6D, $08, $01
>392843		00 6d 08 01
>392847		00 31 27 63 06 01 00 72		MIDI_INSTRUMENT_REEDORG    .text $00, $31, $27, $63, $06, $01, $00, $72, $00, $51, $17, $01
>39284f		00 51 17 01
>392853		00 b4 1d 53 16 0f 01 71		MIDI_INSTRUMENT_ACORDIAN   .text $00, $B4, $1D, $53, $16, $0F, $01, $71, $00, $51, $17, $01
>39285b		00 51 17 01
>39285f		00 25 29 97 15 01 00 32		MIDI_INSTRUMENT_HARMONIC   .text $00, $25, $29, $97, $15, $01, $00, $32, $00, $53, $08, $01
>392867		00 53 08 01
>39286b		00 24 9e 67 15 0f 00 31		MIDI_INSTRUMENT_BANDNEON   .text $00, $24, $9E, $67, $15, $0F, $00, $31, $00, $53, $06, $01
>392873		00 53 06 01
>392877		00 13 27 a3 b4 05 01 31		MIDI_INSTRUMENT_NYLONGT    .text $00, $13, $27, $A3, $B4, $05, $01, $31, $00, $D2, $F8, $00
>39287f		00 d2 f8 00
>392883		00 17 a3 f3 32 01 00 11		MIDI_INSTRUMENT_STEELGT    .text $00, $17, $A3, $F3, $32, $01, $00, $11, $00, $E2, $C7, $01
>39288b		00 e2 c7 01
>39288f		00 33 24 d2 c1 0f 01 31		MIDI_INSTRUMENT_JAZZGT     .text $00, $33, $24, $D2, $C1, $0F, $01, $31, $00, $F1, $9C, $00
>392897		00 f1 9c 00
>39289b		00 31 05 f8 44 01 00 32		MIDI_INSTRUMENT_CLEANGT    .text $00, $31, $05, $F8, $44, $01, $00, $32, $02, $F2, $C9, $01
>3928a3		02 f2 c9 01
>3928a7		00 21 09 9c 7b 07 00 02		MIDI_INSTRUMENT_MUTEGT     .text $00, $21, $09, $9C, $7B, $07, $00, $02, $03, $95, $FB, $00
>3928af		03 95 fb 00
>3928b3		00 21 84 81 98 07 01 21		MIDI_INSTRUMENT_OVERDGT    .text $00, $21, $84, $81, $98, $07, $01, $21, $04, $A1, $59, $00
>3928bb		04 a1 59 00
>3928bf		00 b1 0c 78 43 01 00 22		MIDI_INSTRUMENT_DISTGT     .text $00, $B1, $0C, $78, $43, $01, $00, $22, $03, $91, $FC, $03
>3928c7		03 91 fc 03
>3928cb		00 00 0a 82 8c 09 00 08		MIDI_INSTRUMENT_GTHARMS    .text $00, $00, $0A, $82, $8C, $09, $00, $08, $02, $B4, $EC, $00
>3928d3		02 b4 ec 00
>3928d7		00 21 13 ab 46 01 00 21		MIDI_INSTRUMENT_ACOUBASS   .text $00, $21, $13, $AB, $46, $01, $00, $21, $00, $93, $F7, $00
>3928df		00 93 f7 00
>3928e3		00 01 0a f9 32 01 00 22		MIDI_INSTRUMENT_FINGBASS   .text $00, $01, $0A, $F9, $32, $01, $00, $22, $04, $C1, $58, $00
>3928eb		04 c1 58 00
>3928ef		00 21 07 fa 77 0b 00 22		MIDI_INSTRUMENT_PICKBASS   .text $00, $21, $07, $FA, $77, $0B, $00, $22, $02, $C3, $6A, $00
>3928f7		02 c3 6a 00
>3928fb		00 21 17 71 57 0b 00 21		MIDI_INSTRUMENT_FRETLESS   .text $00, $21, $17, $71, $57, $0B, $00, $21, $00, $62, $87, $00
>392903		00 62 87 00
>392907		00 25 01 fa 78 07 01 12		MIDI_INSTRUMENT_SLAPBAS1   .text $00, $25, $01, $FA, $78, $07, $01, $12, $00, $F3, $97, $00
>39290f		00 f3 97 00
>392913		00 21 03 fa 88 0d 00 13		MIDI_INSTRUMENT_SLAPBAS2   .text $00, $21, $03, $FA, $88, $0D, $00, $13, $00, $B3, $97, $00
>39291b		00 b3 97 00
>39291f		00 21 09 f5 7f 09 01 23		MIDI_INSTRUMENT_SYNBASS1   .text $00, $21, $09, $F5, $7F, $09, $01, $23, $04, $F3, $CC, $00
>392927		04 f3 cc 00
>39292b		00 01 10 a3 9b 09 00 01		MIDI_INSTRUMENT_SYNBASS2   .text $00, $01, $10, $A3, $9B, $09, $00, $01, $00, $93, $AA, $00
>392933		00 93 aa 00
>392937		00 e2 19 f6 29 0d 01 e1		MIDI_INSTRUMENT_VIOLIN     .text $00, $E2, $19, $F6, $29, $0D, $01, $E1, $00, $78, $08, $01
>39293f		00 78 08 01
>392943		00 e2 1c f6 29 0d 01 e1		MIDI_INSTRUMENT_VIOLA      .text $00, $E2, $1C, $F6, $29, $0D, $01, $E1, $00, $78, $08, $01
>39294b		00 78 08 01
>39294f		00 61 19 69 16 0b 01 61		MIDI_INSTRUMENT_CELLO      .text $00, $61, $19, $69, $16, $0B, $01, $61, $00, $54, $27, $01
>392957		00 54 27 01
>39295b		00 71 18 82 31 0d 01 32		MIDI_INSTRUMENT_CONTRAB    .text $00, $71, $18, $82, $31, $0D, $01, $32, $00, $61, $56, $00
>392963		00 61 56 00
>392967		00 e2 23 70 06 0d 01 e1		MIDI_INSTRUMENT_TREMSTR    .text $00, $E2, $23, $70, $06, $0D, $01, $E1, $00, $75, $16, $01
>39296f		00 75 16 01
>392973		00 02 00 88 e6 08 00 61		MIDI_INSTRUMENT_PIZZ       .text $00, $02, $00, $88, $E6, $08, $00, $61, $00, $F5, $F6, $01
>39297b		00 f5 f6 01
>39297f		00 12 20 f6 d5 0f 01 11		MIDI_INSTRUMENT_HARP       .text $00, $12, $20, $F6, $D5, $0F, $01, $11, $80, $F3, $E3, $00
>392987		80 f3 e3 00
>39298b		00 61 0e f4 f4 01 01 00		MIDI_INSTRUMENT_TIMPANI    .text $00, $61, $0E, $F4, $F4, $01, $01, $00, $00, $B5, $F5, $00
>392993		00 b5 f5 00
>392997		00 61 1e 9c 04 0f 01 21		MIDI_INSTRUMENT_STRINGS    .text $00, $61, $1E, $9C, $04, $0F, $01, $21, $80, $71, $16, $00
>39299f		80 71 16 00
>3929a3		00 a2 2a c0 d6 0f 02 21		MIDI_INSTRUMENT_SLOWSTR    .text $00, $A2, $2A, $C0, $D6, $0F, $02, $21, $00, $30, $55, $01
>3929ab		00 30 55 01
>3929af		00 61 21 72 35 0f 01 61		MIDI_INSTRUMENT_SYNSTR1    .text $00, $61, $21, $72, $35, $0F, $01, $61, $00, $62, $36, $01
>3929b7		00 62 36 01
>3929bb		00 21 1a 72 23 0f 01 21		MIDI_INSTRUMENT_SYNSTR2    .text $00, $21, $1A, $72, $23, $0F, $01, $21, $02, $51, $07, $00
>3929c3		02 51 07 00
>3929c7		00 e1 16 97 31 09 00 61		MIDI_INSTRUMENT_CHOIR      .text $00, $E1, $16, $97, $31, $09, $00, $61, $00, $62, $39, $00
>3929cf		00 62 39 00
>3929d3		00 22 c3 79 45 01 00 21		MIDI_INSTRUMENT_OOHS       .text $00, $22, $C3, $79, $45, $01, $00, $21, $00, $66, $27, $00
>3929db		00 66 27 00
>3929df		00 21 de 63 55 01 01 21		MIDI_INSTRUMENT_SYNVOX     .text $00, $21, $DE, $63, $55, $01, $01, $21, $00, $73, $46, $00
>3929e7		00 73 46 00
>3929eb		00 42 05 86 f7 0a 00 50		MIDI_INSTRUMENT_ORCHIT     .text $00, $42, $05, $86, $F7, $0A, $00, $50, $00, $74, $76, $01
>3929f3		00 74 76 01
>3929f7		00 31 1c 61 02 0f 00 61		MIDI_INSTRUMENT_TRUMPET    .text $00, $31, $1C, $61, $02, $0F, $00, $61, $81, $92, $38, $00
>3929ff		81 92 38 00
>392a03		00 71 1e 52 23 0f 00 61		MIDI_INSTRUMENT_TROMBONE   .text $00, $71, $1E, $52, $23, $0F, $00, $61, $02, $71, $19, $00
>392a0b		02 71 19 00
>392a0f		00 21 1a 76 16 0f 00 21		MIDI_INSTRUMENT_TUBA       .text $00, $21, $1A, $76, $16, $0F, $00, $21, $01, $81, $09, $00
>392a17		01 81 09 00
>392a1b		00 25 28 89 2c 07 02 20		MIDI_INSTRUMENT_MUTETRP    .text $00, $25, $28, $89, $2C, $07, $02, $20, $00, $83, $4B, $02
>392a23		00 83 4b 02
>392a27		00 21 1f 79 16 09 00 a2		MIDI_INSTRUMENT_FRHORN     .text $00, $21, $1F, $79, $16, $09, $00, $A2, $05, $71, $59, $00
>392a2f		05 71 59 00
>392a33		00 21 19 87 16 0f 00 21		MIDI_INSTRUMENT_BRASS1     .text $00, $21, $19, $87, $16, $0F, $00, $21, $03, $82, $39, $00
>392a3b		03 82 39 00
>392a3f		00 21 17 75 35 0f 00 22		MIDI_INSTRUMENT_SYNBRAS1   .text $00, $21, $17, $75, $35, $0F, $00, $22, $82, $84, $17, $00
>392a47		82 84 17 00
>392a4b		00 21 22 62 58 0f 00 21		MIDI_INSTRUMENT_SYNBRAS2   .text $00, $21, $22, $62, $58, $0F, $00, $21, $02, $72, $16, $00
>392a53		02 72 16 00
>392a57		00 b1 1b 59 07 01 01 a1		MIDI_INSTRUMENT_SOPSAX     .text $00, $B1, $1B, $59, $07, $01, $01, $A1, $00, $7B, $0A, $00
>392a5f		00 7b 0a 00
>392a63		00 21 16 9f 04 0b 00 21		MIDI_INSTRUMENT_ALTOSAX    .text $00, $21, $16, $9F, $04, $0B, $00, $21, $00, $85, $0C, $01
>392a6b		00 85 0c 01
>392a6f		00 21 0f a8 20 0d 00 23		MIDI_INSTRUMENT_TENSAX     .text $00, $21, $0F, $A8, $20, $0D, $00, $23, $00, $7B, $0A, $01
>392a77		00 7b 0a 01
>392a7b		00 21 0f 88 04 09 00 26		MIDI_INSTRUMENT_BARISAX    .text $00, $21, $0F, $88, $04, $09, $00, $26, $00, $79, $18, $01
>392a83		00 79 18 01
>392a87		00 31 18 8f 05 01 00 32		MIDI_INSTRUMENT_OBOE       .text $00, $31, $18, $8F, $05, $01, $00, $32, $01, $73, $08, $00
>392a8f		01 73 08 00
>392a93		00 a1 0a 8c 37 01 01 24		MIDI_INSTRUMENT_ENGLHORN   .text $00, $A1, $0A, $8C, $37, $01, $01, $24, $04, $77, $0A, $00
>392a9b		04 77 0a 00
>392a9f		00 31 04 a8 67 0b 00 75		MIDI_INSTRUMENT_BASSOON    .text $00, $31, $04, $A8, $67, $0B, $00, $75, $00, $51, $19, $00
>392aa7		00 51 19 00
>392aab		00 a2 1f 77 26 01 01 21		MIDI_INSTRUMENT_CLARINET   .text $00, $A2, $1F, $77, $26, $01, $01, $21, $01, $74, $09, $00
>392ab3		01 74 09 00
>392ab7		00 e1 07 b8 94 01 01 21		MIDI_INSTRUMENT_PICCOLO    .text $00, $E1, $07, $B8, $94, $01, $01, $21, $01, $63, $28, $00
>392abf		01 63 28 00
>392ac3		00 a1 93 87 59 01 00 e1		MIDI_INSTRUMENT_FLUTE1     .text $00, $A1, $93, $87, $59, $01, $00, $E1, $00, $65, $0A, $00
>392acb		00 65 0a 00
>392acf		00 22 10 9f 38 01 00 61		MIDI_INSTRUMENT_RECORDER   .text $00, $22, $10, $9F, $38, $01, $00, $61, $00, $67, $29, $00
>392ad7		00 67 29 00
>392adb		00 e2 0d 88 9a 01 01 21		MIDI_INSTRUMENT_PANFLUTE   .text $00, $E2, $0D, $88, $9A, $01, $01, $21, $00, $67, $09, $00
>392ae3		00 67 09 00
>392ae7		00 a2 10 98 94 0f 00 21		MIDI_INSTRUMENT_BOTTLEB    .text $00, $A2, $10, $98, $94, $0F, $00, $21, $01, $6A, $28, $00
>392aef		01 6a 28 00
>392af3		00 f1 1c 86 26 0f 00 f1		MIDI_INSTRUMENT_SHAKU      .text $00, $F1, $1C, $86, $26, $0F, $00, $F1, $00, $55, $27, $00
>392afb		00 55 27 00
>392aff		00 e1 3f 9f 09 00 00 e1		MIDI_INSTRUMENT_WHISTLE    .text $00, $E1, $3F, $9F, $09, $00, $00, $E1, $00, $6F, $08, $00
>392b07		00 6f 08 00
>392b0b		00 e2 3b f7 19 01 00 21		MIDI_INSTRUMENT_OCARINA    .text $00, $E2, $3B, $F7, $19, $01, $00, $21, $00, $7A, $07, $00
>392b13		00 7a 07 00
>392b17		00 22 1e 92 0c 0f 00 61		MIDI_INSTRUMENT_SQUARWAV   .text $00, $22, $1E, $92, $0C, $0F, $00, $61, $06, $A2, $0D, $00
>392b1f		06 a2 0d 00
>392b23		00 21 15 f4 22 0f 01 21		MIDI_INSTRUMENT_SAWWAV     .text $00, $21, $15, $F4, $22, $0F, $01, $21, $00, $A3, $5F, $00
>392b2b		00 a3 5f 00
>392b2f		00 f2 20 47 66 03 01 f1		MIDI_INSTRUMENT_SYNCALLI   .text $00, $F2, $20, $47, $66, $03, $01, $F1, $00, $42, $27, $00
>392b37		00 42 27 00
>392b3b		00 61 19 88 28 0f 00 61		MIDI_INSTRUMENT_CHIFLEAD   .text $00, $61, $19, $88, $28, $0F, $00, $61, $05, $B2, $49, $00
>392b43		05 b2 49 00
>392b47		00 21 16 82 1b 01 00 23		MIDI_INSTRUMENT_CHARANG    .text $00, $21, $16, $82, $1B, $01, $00, $23, $00, $B2, $79, $01
>392b4f		00 b2 79 01
>392b53		00 21 00 ca 93 01 00 22		MIDI_INSTRUMENT_SOLOVOX    .text $00, $21, $00, $CA, $93, $01, $00, $22, $00, $7A, $1A, $00
>392b5b		00 7a 1a 00
>392b5f		00 23 00 92 c9 08 01 22		MIDI_INSTRUMENT_FIFTHSAW   .text $00, $23, $00, $92, $C9, $08, $01, $22, $00, $82, $28, $01
>392b67		00 82 28 01
>392b6b		00 21 1d f3 7b 0f 00 22		MIDI_INSTRUMENT_BASSLEAD   .text $00, $21, $1D, $F3, $7B, $0F, $00, $22, $02, $C3, $5F, $00
>392b73		02 c3 5f 00
>392b77		00 e1 00 81 25 00 01 a6		MIDI_INSTRUMENT_FANTASIA   .text $00, $E1, $00, $81, $25, $00, $01, $A6, $86, $C4, $95, $01
>392b7f		86 c4 95 01
>392b83		00 21 27 31 01 0f 00 21		MIDI_INSTRUMENT_WARMPAD    .text $00, $21, $27, $31, $01, $0F, $00, $21, $00, $44, $15, $00
>392b8b		00 44 15 00
>392b8f		00 60 14 83 35 0d 02 61		MIDI_INSTRUMENT_POLYSYN    .text $00, $60, $14, $83, $35, $0D, $02, $61, $00, $D1, $06, $00
>392b97		00 d1 06 00
>392b9b		00 e1 5c d3 01 01 01 62		MIDI_INSTRUMENT_SPACEVOX   .text $00, $E1, $5C, $D3, $01, $01, $01, $62, $00, $82, $37, $00
>392ba3		00 82 37 00
>392ba7		00 28 38 34 86 01 02 21		MIDI_INSTRUMENT_BOWEDGLS   .text $00, $28, $38, $34, $86, $01, $02, $21, $00, $41, $35, $00
>392baf		00 41 35 00
>392bb3		00 24 12 52 f3 05 01 23		MIDI_INSTRUMENT_METALPAD   .text $00, $24, $12, $52, $F3, $05, $01, $23, $02, $32, $F5, $01
>392bbb		02 32 f5 01
>392bbf		00 61 1d 62 a6 0b 00 a1		MIDI_INSTRUMENT_HALOPAD    .text $00, $61, $1D, $62, $A6, $0B, $00, $A1, $00, $61, $26, $00
>392bc7		00 61 26 00
>392bcb		00 22 0f 22 d5 0b 01 21		MIDI_INSTRUMENT_SWEEPPAD   .text $00, $22, $0F, $22, $D5, $0B, $01, $21, $84, $3F, $05, $01
>392bd3		84 3f 05 01
>392bd7		00 e3 1f f9 24 01 00 31		MIDI_INSTRUMENT_ICERAIN    .text $00, $E3, $1F, $F9, $24, $01, $00, $31, $01, $D1, $F6, $00
>392bdf		01 d1 f6 00
>392be3		00 63 00 41 55 06 01 a2		MIDI_INSTRUMENT_SOUNDTRK   .text $00, $63, $00, $41, $55, $06, $01, $A2, $00, $41, $05, $01
>392beb		00 41 05 01
>392bef		00 c7 25 a7 65 01 01 c1		MIDI_INSTRUMENT_CRYSTAL    .text $00, $C7, $25, $A7, $65, $01, $01, $C1, $05, $F3, $E4, $00
>392bf7		05 f3 e4 00
>392bfb		00 e3 19 f7 b7 01 01 61		MIDI_INSTRUMENT_ATMOSPH    .text $00, $E3, $19, $F7, $B7, $01, $01, $61, $00, $92, $F5, $01
>392c03		00 92 f5 01
>392c07		00 66 9b a8 44 0f 00 41		MIDI_INSTRUMENT_BRIGHT     .text $00, $66, $9B, $A8, $44, $0F, $00, $41, $04, $F2, $E4, $01
>392c0f		04 f2 e4 01
>392c13		00 61 20 22 75 0d 00 61		MIDI_INSTRUMENT_GOBLIN     .text $00, $61, $20, $22, $75, $0D, $00, $61, $00, $45, $25, $00
>392c1b		00 45 25 00
>392c1f		00 e1 21 f6 84 0f 00 e1		MIDI_INSTRUMENT_ECHODROP   .text $00, $E1, $21, $F6, $84, $0F, $00, $E1, $01, $A3, $36, $00
>392c27		01 a3 36 00
>392c2b		00 e2 14 73 64 0b 01 e1		MIDI_INSTRUMENT_STARTHEM   .text $00, $E2, $14, $73, $64, $0B, $01, $E1, $01, $98, $05, $01
>392c33		01 98 05 01
>392c37		00 21 0b 72 34 09 00 24		MIDI_INSTRUMENT_SITAR      .text $00, $21, $0B, $72, $34, $09, $00, $24, $02, $A3, $F6, $01
>392c3f		02 a3 f6 01
>392c43		00 21 16 f4 53 0d 00 04		MIDI_INSTRUMENT_BANJO      .text $00, $21, $16, $F4, $53, $0D, $00, $04, $00, $F6, $F8, $00
>392c4b		00 f6 f8 00
>392c4f		00 21 18 da 02 0d 00 35		MIDI_INSTRUMENT_SHAMISEN   .text $00, $21, $18, $DA, $02, $0D, $00, $35, $00, $F3, $F5, $00
>392c57		00 f3 f5 00
>392c5b		00 25 0f fa 63 09 00 02		MIDI_INSTRUMENT_KOTO       .text $00, $25, $0F, $FA, $63, $09, $00, $02, $00, $94, $E5, $01
>392c63		00 94 e5 01
>392c67		00 32 07 f9 96 01 00 11		MIDI_INSTRUMENT_KALIMBA    .text $00, $32, $07, $F9, $96, $01, $00, $11, $00, $84, $44, $00
>392c6f		00 84 44 00
>392c73		00 20 0e 97 18 09 02 25		MIDI_INSTRUMENT_BAGPIPE    .text $00, $20, $0E, $97, $18, $09, $02, $25, $03, $83, $18, $01
>392c7b		03 83 18 01
>392c7f		00 61 18 f6 29 01 00 62		MIDI_INSTRUMENT_FIDDLE     .text $00, $61, $18, $F6, $29, $01, $00, $62, $01, $78, $08, $01
>392c87		01 78 08 01
>392c8b		00 e6 21 76 19 0b 00 61		MIDI_INSTRUMENT_SHANNAI    .text $00, $E6, $21, $76, $19, $0B, $00, $61, $03, $8E, $08, $01
>392c93		03 8e 08 01
>392c97		00 27 23 f0 d4 01 00 05		MIDI_INSTRUMENT_TINKLBEL   .text $00, $27, $23, $F0, $D4, $01, $00, $05, $09, $F2, $46, $00
>392c9f		09 f2 46 00
>392ca3		00 1c 0c f9 31 0f 01 15		MIDI_INSTRUMENT_AGOGO      .text $00, $1C, $0C, $F9, $31, $0F, $01, $15, $00, $96, $E8, $01
>392cab		00 96 e8 01
>392caf		00 02 00 75 16 06 02 01		MIDI_INSTRUMENT_STEELDRM   .text $00, $02, $00, $75, $16, $06, $02, $01, $00, $F6, $F6, $01
>392cb7		00 f6 f6 01
>392cbb		00 25 1b fa f2 01 00 12		MIDI_INSTRUMENT_WOODBLOK   .text $00, $25, $1B, $FA, $F2, $01, $00, $12, $00, $F6, $9A, $00
>392cc3		00 f6 9a 00
>392cc7		00 02 1d f5 93 01 00 00		MIDI_INSTRUMENT_TAIKO      .text $00, $02, $1D, $F5, $93, $01, $00, $00, $00, $C6, $45, $00
>392ccf		00 c6 45 00
>392cd3		00 11 15 f5 32 05 00 10		MIDI_INSTRUMENT_MELOTOM    .text $00, $11, $15, $F5, $32, $05, $00, $10, $00, $F4, $B4, $00
>392cdb		00 f4 b4 00
>392cdf		00 22 06 fa 99 09 00 01		MIDI_INSTRUMENT_SYNDRUM    .text $00, $22, $06, $FA, $99, $09, $00, $01, $00, $D5, $25, $00
>392ce7		00 d5 25 00
>392ceb		00 2e 00 ff 00 0f 02 0e		MIDI_INSTRUMENT_REVRSCYM   .text $00, $2E, $00, $FF, $00, $0F, $02, $0E, $0E, $21, $2D, $00
>392cf3		0e 21 2d 00
>392cf7		00 30 0b 56 e4 01 01 17		MIDI_INSTRUMENT_FRETNOIS   .text $00, $30, $0B, $56, $E4, $01, $01, $17, $00, $55, $87, $02
>392cff		00 55 87 02
>392d03		00 24 00 ff 03 0d 00 05		MIDI_INSTRUMENT_BRTHNOIS   .text $00, $24, $00, $FF, $03, $0D, $00, $05, $08, $98, $87, $01
>392d0b		08 98 87 01
>392d0f		00 0e 00 f0 00 0f 02 0a		MIDI_INSTRUMENT_SEASHORE   .text $00, $0E, $00, $F0, $00, $0F, $02, $0A, $04, $17, $04, $03
>392d17		04 17 04 03
>392d1b		00 20 08 f6 f7 01 00 0e		MIDI_INSTRUMENT_BIRDS      .text $00, $20, $08, $F6, $F7, $01, $00, $0E, $05, $77, $F9, $02
>392d23		05 77 f9 02
>392d27		00 20 14 f1 08 01 00 2e		MIDI_INSTRUMENT_TELEPHON   .text $00, $20, $14, $F1, $08, $01, $00, $2E, $02, $F4, $08, $00
>392d2f		02 f4 08 00
>392d33		00 20 04 f2 00 03 01 23		MIDI_INSTRUMENT_HELICOPT   .text $00, $20, $04, $F2, $00, $03, $01, $23, $00, $36, $05, $01
>392d3b		00 36 05 01
>392d3f		00 2e 00 ff 02 0f 00 2a		MIDI_INSTRUMENT_APPLAUSE   .text $00, $2E, $00, $FF, $02, $0F, $00, $2A, $05, $32, $55, $03
>392d47		05 32 55 03
>392d4b		00 20 00 a1 ef 0f 00 10		MIDI_INSTRUMENT_GUNSHOT    .text $00, $20, $00, $A1, $EF, $0F, $00, $10, $00, $F3, $DF, $00
>392d53		00 f3 df 00
>392d57		57 27 39 00 63 27 39 00		midiInstruments .dword MIDI_INSTRUMENT_PIANO1,   MIDI_INSTRUMENT_PIANO2,   MIDI_INSTRUMENT_PIANO3,   MIDI_INSTRUMENT_HONKTONK, MIDI_INSTRUMENT_EP1,      MIDI_INSTRUMENT_EP2
>392d5f		6f 27 39 00 7b 27 39 00 87 27 39 00 93 27 39 00
>392d6f		9f 27 39 00 ab 27 39 00		              	.dword MIDI_INSTRUMENT_HARPSIC,  MIDI_INSTRUMENT_CLAVIC,   MIDI_INSTRUMENT_CELESTA,  MIDI_INSTRUMENT_GLOCK,    MIDI_INSTRUMENT_MUSICBOX, MIDI_INSTRUMENT_VIBES
>392d77		b7 27 39 00 c3 27 39 00 cf 27 39 00 db 27 39 00
>392d87		e7 27 39 00 f3 27 39 00		              	.dword MIDI_INSTRUMENT_MARIMBA,  MIDI_INSTRUMENT_XYLO,     MIDI_INSTRUMENT_TUBEBELL, MIDI_INSTRUMENT_SANTUR,   MIDI_INSTRUMENT_ORGAN1,   MIDI_INSTRUMENT_ORGAN2
>392d8f		ff 27 39 00 0b 28 39 00 17 28 39 00 23 28 39 00
>392d9f		2f 28 39 00 3b 28 39 00		              	.dword MIDI_INSTRUMENT_ORGAN3,   MIDI_INSTRUMENT_PIPEORG,  MIDI_INSTRUMENT_REEDORG,  MIDI_INSTRUMENT_ACORDIAN, MIDI_INSTRUMENT_HARMONIC, MIDI_INSTRUMENT_BANDNEON
>392da7		47 28 39 00 53 28 39 00 5f 28 39 00 6b 28 39 00
>392db7		77 28 39 00 83 28 39 00		              	.dword MIDI_INSTRUMENT_NYLONGT,  MIDI_INSTRUMENT_STEELGT,  MIDI_INSTRUMENT_JAZZGT,   MIDI_INSTRUMENT_CLEANGT,  MIDI_INSTRUMENT_MUTEGT,   MIDI_INSTRUMENT_OVERDGT
>392dbf		8f 28 39 00 9b 28 39 00 a7 28 39 00 b3 28 39 00
>392dcf		bf 28 39 00 cb 28 39 00		              	.dword MIDI_INSTRUMENT_DISTGT,   MIDI_INSTRUMENT_GTHARMS,  MIDI_INSTRUMENT_ACOUBASS, MIDI_INSTRUMENT_FINGBASS, MIDI_INSTRUMENT_PICKBASS, MIDI_INSTRUMENT_FRETLESS
>392dd7		d7 28 39 00 e3 28 39 00 ef 28 39 00 fb 28 39 00
>392de7		07 29 39 00 13 29 39 00		              	.dword MIDI_INSTRUMENT_SLAPBAS1, MIDI_INSTRUMENT_SLAPBAS2, MIDI_INSTRUMENT_SYNBASS1, MIDI_INSTRUMENT_SYNBASS2, MIDI_INSTRUMENT_VIOLIN,   MIDI_INSTRUMENT_VIOLA
>392def		1f 29 39 00 2b 29 39 00 37 29 39 00 43 29 39 00
>392dff		4f 29 39 00 5b 29 39 00		              	.dword MIDI_INSTRUMENT_CELLO,    MIDI_INSTRUMENT_CONTRAB,  MIDI_INSTRUMENT_TREMSTR,  MIDI_INSTRUMENT_PIZZ,     MIDI_INSTRUMENT_HARP,     MIDI_INSTRUMENT_TIMPANI
>392e07		67 29 39 00 73 29 39 00 7f 29 39 00 8b 29 39 00
>392e17		97 29 39 00 a3 29 39 00		              	.dword MIDI_INSTRUMENT_STRINGS,  MIDI_INSTRUMENT_SLOWSTR,  MIDI_INSTRUMENT_SYNSTR1,  MIDI_INSTRUMENT_SYNSTR2,  MIDI_INSTRUMENT_CHOIR,    MIDI_INSTRUMENT_OOHS
>392e1f		af 29 39 00 bb 29 39 00 c7 29 39 00 d3 29 39 00
>392e2f		df 29 39 00 eb 29 39 00		              	.dword MIDI_INSTRUMENT_SYNVOX,   MIDI_INSTRUMENT_ORCHIT,   MIDI_INSTRUMENT_TRUMPET,  MIDI_INSTRUMENT_TROMBONE, MIDI_INSTRUMENT_TUBA,     MIDI_INSTRUMENT_MUTETRP
>392e37		f7 29 39 00 03 2a 39 00 0f 2a 39 00 1b 2a 39 00
>392e47		27 2a 39 00 33 2a 39 00		              	.dword MIDI_INSTRUMENT_FRHORN,   MIDI_INSTRUMENT_BRASS1,   MIDI_INSTRUMENT_SYNBRAS1, MIDI_INSTRUMENT_SYNBRAS2, MIDI_INSTRUMENT_SOPSAX,   MIDI_INSTRUMENT_ALTOSAX
>392e4f		3f 2a 39 00 4b 2a 39 00 57 2a 39 00 63 2a 39 00
>392e5f		6f 2a 39 00 7b 2a 39 00		              	.dword MIDI_INSTRUMENT_TENSAX,   MIDI_INSTRUMENT_BARISAX,  MIDI_INSTRUMENT_OBOE,     MIDI_INSTRUMENT_ENGLHORN, MIDI_INSTRUMENT_BASSOON,  MIDI_INSTRUMENT_CLARINET
>392e67		87 2a 39 00 93 2a 39 00 9f 2a 39 00 ab 2a 39 00
>392e77		b7 2a 39 00 c3 2a 39 00		              	.dword MIDI_INSTRUMENT_PICCOLO,  MIDI_INSTRUMENT_FLUTE1,   MIDI_INSTRUMENT_RECORDER, MIDI_INSTRUMENT_PANFLUTE, MIDI_INSTRUMENT_BOTTLEB,  MIDI_INSTRUMENT_SHAKU
>392e7f		cf 2a 39 00 db 2a 39 00 e7 2a 39 00 f3 2a 39 00
>392e8f		ff 2a 39 00 0b 2b 39 00		              	.dword MIDI_INSTRUMENT_WHISTLE,  MIDI_INSTRUMENT_OCARINA,  MIDI_INSTRUMENT_SQUARWAV, MIDI_INSTRUMENT_SAWWAV,   MIDI_INSTRUMENT_SYNCALLI, MIDI_INSTRUMENT_CHIFLEAD
>392e97		17 2b 39 00 23 2b 39 00 2f 2b 39 00 3b 2b 39 00
>392ea7		47 2b 39 00 53 2b 39 00		              	.dword MIDI_INSTRUMENT_CHARANG,  MIDI_INSTRUMENT_SOLOVOX,  MIDI_INSTRUMENT_FIFTHSAW, MIDI_INSTRUMENT_BASSLEAD, MIDI_INSTRUMENT_FANTASIA, MIDI_INSTRUMENT_WARMPAD
>392eaf		5f 2b 39 00 6b 2b 39 00 77 2b 39 00 83 2b 39 00
>392ebf		8f 2b 39 00 9b 2b 39 00		              	.dword MIDI_INSTRUMENT_POLYSYN,  MIDI_INSTRUMENT_SPACEVOX, MIDI_INSTRUMENT_BOWEDGLS, MIDI_INSTRUMENT_METALPAD, MIDI_INSTRUMENT_HALOPAD,  MIDI_INSTRUMENT_SWEEPPAD
>392ec7		a7 2b 39 00 b3 2b 39 00 bf 2b 39 00 cb 2b 39 00
>392ed7		d7 2b 39 00 e3 2b 39 00		              	.dword MIDI_INSTRUMENT_ICERAIN,  MIDI_INSTRUMENT_SOUNDTRK, MIDI_INSTRUMENT_CRYSTAL,  MIDI_INSTRUMENT_ATMOSPH,  MIDI_INSTRUMENT_BRIGHT,   MIDI_INSTRUMENT_GOBLIN
>392edf		ef 2b 39 00 fb 2b 39 00 07 2c 39 00 13 2c 39 00
>392eef		1f 2c 39 00 2b 2c 39 00		              	.dword MIDI_INSTRUMENT_ECHODROP, MIDI_INSTRUMENT_STARTHEM, MIDI_INSTRUMENT_SITAR,    MIDI_INSTRUMENT_BANJO,    MIDI_INSTRUMENT_SHAMISEN, MIDI_INSTRUMENT_KOTO
>392ef7		37 2c 39 00 43 2c 39 00 4f 2c 39 00 5b 2c 39 00
>392f07		67 2c 39 00 73 2c 39 00		              	.dword MIDI_INSTRUMENT_KALIMBA,  MIDI_INSTRUMENT_BAGPIPE,  MIDI_INSTRUMENT_FIDDLE,   MIDI_INSTRUMENT_SHANNAI,  MIDI_INSTRUMENT_TINKLBEL, MIDI_INSTRUMENT_AGOGO
>392f0f		7f 2c 39 00 8b 2c 39 00 97 2c 39 00 a3 2c 39 00
>392f1f		af 2c 39 00 bb 2c 39 00		              	.dword MIDI_INSTRUMENT_STEELDRM, MIDI_INSTRUMENT_WOODBLOK, MIDI_INSTRUMENT_TAIKO,    MIDI_INSTRUMENT_MELOTOM,  MIDI_INSTRUMENT_SYNDRUM,  MIDI_INSTRUMENT_REVRSCYM
>392f27		c7 2c 39 00 d3 2c 39 00 df 2c 39 00 eb 2c 39 00
>392f37		f7 2c 39 00 03 2d 39 00		              	.dword MIDI_INSTRUMENT_FRETNOIS, MIDI_INSTRUMENT_BRTHNOIS, MIDI_INSTRUMENT_SEASHORE, MIDI_INSTRUMENT_BIRDS,    MIDI_INSTRUMENT_TELEPHON, MIDI_INSTRUMENT_HELICOPT
>392f3f		0f 2d 39 00 1b 2d 39 00 27 2d 39 00 33 2d 39 00
>392f4f		3f 2d 39 00 4b 2d 39 00		              	.dword MIDI_INSTRUMENT_APPLAUSE, MIDI_INSTRUMENT_GUNSHOT

;******  Return to file: src\OPL2_Library.asm


;******  Processing file: src\OPL2_Midi_Instruments_Win31.asm

>392f57		00 01 8f f2 f4 38 00 01		MIDIW31_INSTRUMENT_PIANO1     .text $00, $01, $8F, $F2, $F4, $38, $00, $01, $0D, $F2, $F7, $00
>392f5f		0d f2 f7 00
>392f63		00 01 4b f2 f4 38 00 01		MIDIW31_INSTRUMENT_PIANO2     .text $00, $01, $4B, $F2, $F4, $38, $00, $01, $07, $F2, $F7, $00
>392f6b		07 f2 f7 00
>392f6f		00 01 49 f2 f4 38 00 01		MIDIW31_INSTRUMENT_PIANO3     .text $00, $01, $49, $F2, $F4, $38, $00, $01, $07, $F2, $F6, $00
>392f77		07 f2 f6 00
>392f7b		00 81 12 f2 f7 00 00 41		MIDIW31_INSTRUMENT_HONKTONK   .text $00, $81, $12, $F2, $F7, $00, $00, $41, $07, $F2, $F7, $00
>392f83		07 f2 f7 00
>392f87		00 01 57 f1 f7 00 00 01		MIDIW31_INSTRUMENT_EP1        .text $00, $01, $57, $F1, $F7, $00, $00, $01, $07, $F2, $F7, $00
>392f8f		07 f2 f7 00
>392f93		00 01 93 f1 f7 00 00 01		MIDIW31_INSTRUMENT_EP2        .text $00, $01, $93, $F1, $F7, $00, $00, $01, $07, $F2, $F7, $00
>392f9b		07 f2 f7 00
>392f9f		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_HARPSIC    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>392fa7		00 00 00 00
>392fab		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CLAVIC     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>392fb3		00 00 00 00
>392fb7		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CELESTA    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>392fbf		00 00 00 00
>392fc3		00 07 97 f3 f2 32 00 11		MIDIW31_INSTRUMENT_GLOCK      .text $00, $07, $97, $F3, $F2, $32, $00, $11, $87, $F2, $F1, $00
>392fcb		87 f2 f1 00
>392fcf		00 17 21 54 f4 32 00 01		MIDIW31_INSTRUMENT_MUSICBOX   .text $00, $17, $21, $54, $F4, $32, $00, $01, $07, $F4, $F4, $00
>392fd7		07 f4 f4 00
>392fdb		00 98 62 f3 f6 30 00 81		MIDIW31_INSTRUMENT_VIBES      .text $00, $98, $62, $F3, $F6, $30, $00, $81, $07, $F2, $F6, $00
>392fe3		07 f2 f6 00
>392fe7		00 18 23 f6 f6 00 00 01		MIDIW31_INSTRUMENT_MARIMBA    .text $00, $18, $23, $F6, $F6, $00, $00, $01, $07, $E7, $F7, $00
>392fef		07 e7 f7 00
>392ff3		00 15 91 f6 f6 00 00 01		MIDIW31_INSTRUMENT_XYLO       .text $00, $15, $91, $F6, $F6, $00, $00, $01, $07, $F6, $F6, $00
>392ffb		07 f6 f6 00
>392fff		00 45 59 d3 f3 00 00 81		MIDIW31_INSTRUMENT_TUBEBELL   .text $00, $45, $59, $D3, $F3, $00, $00, $81, $87, $A3, $F3, $00
>393007		87 a3 f3 00
>39300b		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SANTUR     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393013		00 00 00 00
>393017		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_ORGAN1     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39301f		00 00 00 00
>393023		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_ORGAN2     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39302b		00 00 00 00
>39302f		00 70 44 aa 18 34 00 b1		MIDIW31_INSTRUMENT_ORGAN3     .text $00, $70, $44, $AA, $18, $34, $00, $B1, $07, $8A, $08, $00
>393037		07 8a 08 00
>39303b		00 23 93 97 23 34 01 b1		MIDIW31_INSTRUMENT_PIPEORG    .text $00, $23, $93, $97, $23, $34, $01, $B1, $07, $55, $14, $00
>393043		07 55 14 00
>393047		00 61 13 97 04 30 01 b1		MIDIW31_INSTRUMENT_REEDORG    .text $00, $61, $13, $97, $04, $30, $01, $B1, $87, $55, $04, $00
>39304f		87 55 04 00
>393053		00 24 48 98 2a 30 01 b1		MIDIW31_INSTRUMENT_ACORDIAN   .text $00, $24, $48, $98, $2A, $30, $01, $B1, $07, $46, $1A, $00
>39305b		07 46 1a 00
>39305f		00 61 13 91 06 00 01 21		MIDIW31_INSTRUMENT_HARMONIC   .text $00, $61, $13, $91, $06, $00, $01, $21, $07, $61, $07, $00
>393067		07 61 07 00
>39306b		00 21 13 71 06 00 00 a1		MIDIW31_INSTRUMENT_BANDNEON   .text $00, $21, $13, $71, $06, $00, $00, $A1, $90, $61, $07, $00
>393073		90 61 07 00
>393077		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_NYLONGT    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39307f		00 00 00 00
>393083		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_STEELGT    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39308b		00 00 00 00
>39308f		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_JAZZGT     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393097		00 00 00 00
>39309b		00 03 87 f6 22 36 01 21		MIDIW31_INSTRUMENT_CLEANGT    .text $00, $03, $87, $F6, $22, $36, $01, $21, $87, $F3, $F8, $00
>3930a3		87 f3 f8 00
>3930a7		00 03 47 f9 54 30 00 21		MIDIW31_INSTRUMENT_MUTEGT     .text $00, $03, $47, $F9, $54, $30, $00, $21, $07, $F6, $3A, $00
>3930af		07 f6 3a 00
>3930b3		00 23 4a 91 41 38 01 21		MIDIW31_INSTRUMENT_OVERDGT    .text $00, $23, $4A, $91, $41, $38, $01, $21, $0C, $84, $19, $00
>3930bb		0c 84 19 00
>3930bf		00 23 4a 95 19 32 01 21		MIDIW31_INSTRUMENT_DISTGT     .text $00, $23, $4A, $95, $19, $32, $01, $21, $07, $94, $19, $00
>3930c7		07 94 19 00
>3930cb		00 09 a1 20 4f 00 00 84		MIDIW31_INSTRUMENT_GTHARMS    .text $00, $09, $A1, $20, $4F, $00, $00, $84, $87, $D1, $F8, $00
>3930d3		87 d1 f8 00
>3930d7		00 21 1e 94 06 00 00 a2		MIDIW31_INSTRUMENT_ACOUBASS   .text $00, $21, $1E, $94, $06, $00, $00, $A2, $07, $C3, $A6, $00
>3930df		07 c3 a6 00
>3930e3		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_FINGBASS   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3930eb		00 00 00 00
>3930ef		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_PICKBASS   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3930f7		00 00 00 00
>3930fb		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_FRETLESS   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393103		00 00 00 00
>393107		00 01 8b a1 9a 38 00 21		MIDIW31_INSTRUMENT_SLAPBAS1   .text $00, $01, $8B, $A1, $9A, $38, $00, $21, $47, $F2, $DF, $00
>39310f		47 f2 df 00
>393113		00 21 8b a2 16 38 00 21		MIDIW31_INSTRUMENT_SLAPBAS2   .text $00, $21, $8B, $A2, $16, $38, $00, $21, $0F, $A1, $DF, $00
>39311b		0f a1 df 00
>39311f		00 31 8b f4 e8 3a 00 31		MIDIW31_INSTRUMENT_SYNBASS1   .text $00, $31, $8B, $F4, $E8, $3A, $00, $31, $07, $F1, $78, $00
>393127		07 f1 78 00
>39312b		00 31 12 f1 28 30 00 31		MIDIW31_INSTRUMENT_SYNBASS2   .text $00, $31, $12, $F1, $28, $30, $00, $31, $07, $F1, $18, $00
>393133		07 f1 18 00
>393137		00 31 15 dd 13 00 01 21		MIDIW31_INSTRUMENT_VIOLIN     .text $00, $31, $15, $DD, $13, $00, $01, $21, $07, $56, $26, $00
>39313f		07 56 26 00
>393143		00 31 16 dd 13 00 01 21		MIDIW31_INSTRUMENT_VIOLA      .text $00, $31, $16, $DD, $13, $00, $01, $21, $07, $66, $06, $00
>39314b		07 66 06 00
>39314f		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CELLO      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393157		00 00 00 00
>39315b		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CONTRAB    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393163		00 00 00 00
>393167		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_TREMSTR    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39316f		00 00 00 00
>393173		00 02 1a f5 75 30 01 01		MIDIW31_INSTRUMENT_PIZZ       .text $00, $02, $1A, $F5, $75, $30, $01, $01, $87, $85, $35, $00
>39317b		87 85 35 00
>39317f		00 02 1d f5 75 30 01 01		MIDIW31_INSTRUMENT_HARP       .text $00, $02, $1D, $F5, $75, $30, $01, $01, $87, $F3, $F4, $00
>393187		87 f3 f4 00
>39318b		00 10 41 f5 05 32 01 11		MIDIW31_INSTRUMENT_TIMPANI    .text $00, $10, $41, $F5, $05, $32, $01, $11, $07, $F2, $C3, $00
>393193		07 f2 c3 00
>393197		00 21 9b b1 25 3c 01 a2		MIDIW31_INSTRUMENT_STRINGS    .text $00, $21, $9B, $B1, $25, $3C, $01, $A2, $08, $72, $08, $00
>39319f		08 72 08 00
>3931a3		00 a1 98 7f 03 00 01 21		MIDIW31_INSTRUMENT_SLOWSTR    .text $00, $A1, $98, $7F, $03, $00, $01, $21, $07, $3F, $07, $01
>3931ab		07 3f 07 01
>3931af		00 a1 93 c1 12 00 00 61		MIDIW31_INSTRUMENT_SYNSTR1    .text $00, $A1, $93, $C1, $12, $00, $00, $61, $07, $4F, $05, $00
>3931b7		07 4f 05 00
>3931bb		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SYNSTR2    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3931c3		00 00 00 00
>3931c7		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CHOIR      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3931cf		00 00 00 00
>3931d3		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_OOHS       .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3931db		00 00 00 00
>3931df		00 71 57 54 05 3c 00 72		MIDIW31_INSTRUMENT_SYNVOX     .text $00, $71, $57, $54, $05, $3C, $00, $72, $07, $7A, $05, $00
>3931e7		07 7a 05 00
>3931eb		00 90 00 54 63 38 00 41		MIDIW31_INSTRUMENT_ORCHIT     .text $00, $90, $00, $54, $63, $38, $00, $41, $07, $A5, $45, $00
>3931f3		07 a5 45 00
>3931f7		00 21 92 85 17 3c 00 21		MIDIW31_INSTRUMENT_TRUMPET    .text $00, $21, $92, $85, $17, $3C, $00, $21, $08, $8F, $09, $00
>3931ff		08 8f 09 00
>393203		00 21 94 75 17 32 00 21		MIDIW31_INSTRUMENT_TROMBONE   .text $00, $21, $94, $75, $17, $32, $00, $21, $0C, $8F, $09, $00
>39320b		0c 8f 09 00
>39320f		00 21 94 76 15 00 00 61		MIDIW31_INSTRUMENT_TUBA       .text $00, $21, $94, $76, $15, $00, $00, $61, $07, $82, $37, $00
>393217		07 82 37 00
>39321b		00 31 43 9e 17 00 01 21		MIDIW31_INSTRUMENT_MUTETRP    .text $00, $31, $43, $9E, $17, $00, $01, $21, $07, $62, $2C, $01
>393223		07 62 2c 01
>393227		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_FRHORN     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39322f		00 00 00 00
>393233		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BRASS1     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39323b		00 00 00 00
>39323f		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SYNBRAS1   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393247		00 00 00 00
>39324b		00 21 4d 54 3c 38 00 21		MIDIW31_INSTRUMENT_SYNBRAS2   .text $00, $21, $4D, $54, $3C, $38, $00, $21, $07, $A6, $1C, $00
>393253		07 a6 1c 00
>393257		00 31 8f 93 02 38 01 61		MIDIW31_INSTRUMENT_SOPSAX     .text $00, $31, $8F, $93, $02, $38, $01, $61, $07, $72, $0B, $00
>39325f		07 72 0b 00
>393263		00 31 8e 93 03 38 01 61		MIDIW31_INSTRUMENT_ALTOSAX    .text $00, $31, $8E, $93, $03, $38, $01, $61, $07, $72, $09, $00
>39326b		07 72 09 00
>39326f		00 31 91 93 03 30 01 61		MIDIW31_INSTRUMENT_TENSAX     .text $00, $31, $91, $93, $03, $30, $01, $61, $07, $82, $09, $00
>393277		07 82 09 00
>39327b		00 31 8e 93 0f 00 01 61		MIDIW31_INSTRUMENT_BARISAX    .text $00, $31, $8E, $93, $0F, $00, $01, $61, $07, $72, $0F, $00
>393283		07 72 0f 00
>393287		00 21 4b aa 16 00 01 21		MIDIW31_INSTRUMENT_OBOE       .text $00, $21, $4B, $AA, $16, $00, $01, $21, $07, $8F, $0A, $00
>39328f		07 8f 0a 00
>393293		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_ENGLHORN   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39329b		00 00 00 00
>39329f		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BASSOON    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3932a7		00 00 00 00
>3932ab		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CLARINET   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3932b3		00 00 00 00
>3932b7		00 e1 1f 85 5f 30 00 e1		MIDIW31_INSTRUMENT_PICCOLO    .text $00, $E1, $1F, $85, $5F, $30, $00, $E1, $07, $65, $1A, $00
>3932bf		07 65 1a 00
>3932c3		00 e1 46 88 5f 30 00 e1		MIDIW31_INSTRUMENT_FLUTE1     .text $00, $E1, $46, $88, $5F, $30, $00, $E1, $07, $65, $1A, $00
>3932cb		07 65 1a 00
>3932cf		00 a1 9c 75 1f 32 00 21		MIDIW31_INSTRUMENT_RECORDER   .text $00, $A1, $9C, $75, $1F, $32, $00, $21, $07, $75, $0A, $00
>3932d7		07 75 0a 00
>3932db		00 31 8b 84 58 30 00 21		MIDIW31_INSTRUMENT_PANFLUTE   .text $00, $31, $8B, $84, $58, $30, $00, $21, $07, $65, $1A, $00
>3932e3		07 65 1a 00
>3932e7		00 e1 4c 66 56 00 00 a1		MIDIW31_INSTRUMENT_BOTTLEB    .text $00, $E1, $4C, $66, $56, $00, $00, $A1, $07, $65, $26, $00
>3932ef		07 65 26 00
>3932f3		00 62 cb 76 46 00 00 a1		MIDIW31_INSTRUMENT_SHAKU      .text $00, $62, $CB, $76, $46, $00, $00, $A1, $07, $55, $36, $00
>3932fb		07 55 36 00
>3932ff		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_WHISTLE    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393307		00 00 00 00
>39330b		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_OCARINA    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393313		00 00 00 00
>393317		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SQUARWAV   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39331f		00 00 00 00
>393323		00 21 0e ff 0f 30 01 21		MIDIW31_INSTRUMENT_SAWWAV     .text $00, $21, $0E, $FF, $0F, $30, $01, $21, $07, $FF, $0F, $01
>39332b		07 ff 0f 01
>39332f		00 22 46 86 55 30 00 21		MIDIW31_INSTRUMENT_SYNCALLI   .text $00, $22, $46, $86, $55, $30, $00, $21, $87, $64, $18, $00
>393337		87 64 18 00
>39333b		00 21 45 66 12 30 00 a1		MIDIW31_INSTRUMENT_CHIFLEAD   .text $00, $21, $45, $66, $12, $30, $00, $A1, $07, $96, $0A, $00
>393343		07 96 0a 00
>393347		00 21 8b 92 2a 34 01 22		MIDIW31_INSTRUMENT_CHARANG    .text $00, $21, $8B, $92, $2A, $34, $01, $22, $07, $91, $2A, $00
>39334f		07 91 2a 00
>393353		00 a2 9e df 05 00 00 61		MIDIW31_INSTRUMENT_SOLOVOX    .text $00, $A2, $9E, $DF, $05, $00, $00, $61, $47, $6F, $07, $00
>39335b		47 6f 07 00
>39335f		00 20 1a ef 01 00 00 60		MIDIW31_INSTRUMENT_FIFTHSAW   .text $00, $20, $1A, $EF, $01, $00, $00, $60, $07, $8F, $06, $02
>393367		07 8f 06 02
>39336b		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BASSLEAD   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393373		00 00 00 00
>393377		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_FANTASIA   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39337f		00 00 00 00
>393383		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_WARMPAD    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39338b		00 00 00 00
>39338f		00 61 17 91 34 3c 00 61		MIDIW31_INSTRUMENT_POLYSYN    .text $00, $61, $17, $91, $34, $3C, $00, $61, $07, $55, $16, $00
>393397		07 55 16 00
>39339b		00 71 5d 54 01 30 00 72		MIDIW31_INSTRUMENT_SPACEVOX   .text $00, $71, $5D, $54, $01, $30, $00, $72, $07, $6A, $03, $00
>3933a3		07 6a 03 00
>3933a7		00 21 97 21 43 38 00 a2		MIDIW31_INSTRUMENT_BOWEDGLS   .text $00, $21, $97, $21, $43, $38, $00, $A2, $07, $42, $35, $00
>3933af		07 42 35 00
>3933b3		00 a1 1c a1 77 30 01 21		MIDIW31_INSTRUMENT_METALPAD   .text $00, $A1, $1C, $A1, $77, $30, $01, $21, $07, $31, $47, $01
>3933bb		07 31 47 01
>3933bf		00 21 89 11 33 00 00 61		MIDIW31_INSTRUMENT_HALOPAD    .text $00, $21, $89, $11, $33, $00, $00, $61, $0A, $42, $25, $00
>3933c7		0a 42 25 00
>3933cb		00 a1 15 11 47 00 01 21		MIDIW31_INSTRUMENT_SWEEPPAD   .text $00, $A1, $15, $11, $47, $00, $01, $21, $07, $CF, $07, $00
>3933d3		07 cf 07 00
>3933d7		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_ICERAIN    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3933df		00 00 00 00
>3933e3		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SOUNDTRK   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3933eb		00 00 00 00
>3933ef		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CRYSTAL    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3933f7		00 00 00 00
>3933fb		00 22 92 b1 81 3c 00 61		MIDIW31_INSTRUMENT_ATMOSPH    .text $00, $22, $92, $B1, $81, $3C, $00, $61, $8A, $F2, $26, $00
>393403		8a f2 26 00
>393407		00 41 4d f1 51 30 01 42		MIDIW31_INSTRUMENT_BRIGHT     .text $00, $41, $4D, $F1, $51, $30, $01, $42, $07, $F2, $F5, $00
>39340f		07 f2 f5 00
>393413		00 61 94 11 51 36 01 a3		MIDIW31_INSTRUMENT_GOBLIN     .text $00, $61, $94, $11, $51, $36, $01, $A3, $87, $11, $13, $00
>39341b		87 11 13 00
>39341f		00 61 8c 11 31 3a 00 a1		MIDIW31_INSTRUMENT_ECHODROP   .text $00, $61, $8C, $11, $31, $3A, $00, $A1, $87, $1D, $03, $00
>393427		87 1d 03 00
>39342b		00 a4 4c f3 73 00 01 61		MIDIW31_INSTRUMENT_STARTHEM   .text $00, $A4, $4C, $F3, $73, $00, $01, $61, $07, $81, $23, $00
>393433		07 81 23 00
>393437		00 02 85 d2 53 00 00 07		MIDIW31_INSTRUMENT_SITAR      .text $00, $02, $85, $D2, $53, $00, $00, $07, $0A, $F2, $F6, $01
>39343f		0a f2 f6 01
>393443		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BANJO      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39344b		00 00 00 00
>39344f		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SHAMISEN   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393457		00 00 00 00
>39345b		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_KOTO       .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393463		00 00 00 00
>393467		00 04 4f fa 56 3c 00 01		MIDIW31_INSTRUMENT_KALIMBA    .text $00, $04, $4F, $FA, $56, $3C, $00, $01, $07, $C2, $05, $00
>39346f		07 c2 05 00
>393473		00 21 49 7c 20 36 00 22		MIDIW31_INSTRUMENT_BAGPIPE    .text $00, $21, $49, $7C, $20, $36, $00, $22, $07, $6F, $0C, $01
>39347b		07 6f 0c 01
>39347f		00 31 85 dd 33 3a 01 21		MIDIW31_INSTRUMENT_FIDDLE     .text $00, $31, $85, $DD, $33, $3A, $01, $21, $07, $56, $16, $00
>393487		07 56 16 00
>39348b		00 20 04 da 05 30 02 21		MIDIW31_INSTRUMENT_SHANNAI    .text $00, $20, $04, $DA, $05, $30, $02, $21, $88, $8F, $0B, $00
>393493		88 8f 0b 00
>393497		00 05 6a f1 e5 00 00 03		MIDIW31_INSTRUMENT_TINKLBEL   .text $00, $05, $6A, $F1, $E5, $00, $00, $03, $87, $C3, $E5, $00
>39349f		87 c3 e5 00
>3934a3		00 07 15 ec 26 00 00 02		MIDIW31_INSTRUMENT_AGOGO      .text $00, $07, $15, $EC, $26, $00, $00, $02, $07, $F8, $16, $00
>3934ab		07 f8 16 00
>3934af		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_STEELDRM   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3934b7		00 00 00 00
>3934bb		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_WOODBLOK   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3934c3		00 00 00 00
>3934c7		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_TAIKO      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>3934cf		00 00 00 00
>3934d3		00 11 41 f8 47 34 02 10		MIDIW31_INSTRUMENT_MELOTOM    .text $00, $11, $41, $F8, $47, $34, $02, $10, $0A, $F3, $03, $00
>3934db		0a f3 03 00
>3934df		00 01 8e f1 06 3e 02 10		MIDIW31_INSTRUMENT_SYNDRUM    .text $00, $01, $8E, $F1, $06, $3E, $02, $10, $07, $F3, $02, $00
>3934e7		07 f3 02 00
>3934eb		00 0e 00 1f 00 3e 00 c0		MIDIW31_INSTRUMENT_REVRSCYM   .text $00, $0E, $00, $1F, $00, $3E, $00, $C0, $07, $1F, $FF, $03
>3934f3		07 1f ff 03
>3934f7		00 06 80 f8 24 38 00 03		MIDIW31_INSTRUMENT_FRETNOIS   .text $00, $06, $80, $F8, $24, $38, $00, $03, $8F, $56, $84, $02
>3934ff		8f 56 84 02
>393503		00 0e 00 f8 00 00 00 d0		MIDIW31_INSTRUMENT_BRTHNOIS   .text $00, $0E, $00, $F8, $00, $00, $00, $D0, $0C, $34, $04, $03
>39350b		0c 34 04 03
>39350f		00 0e 00 f6 00 00 00 c0		MIDIW31_INSTRUMENT_SEASHORE   .text $00, $0E, $00, $F6, $00, $00, $00, $C0, $07, $1F, $02, $03
>393517		07 1f 02 03
>39351b		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BIRDS      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>393523		00 00 00 00
>393527		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_TELEPHON   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39352f		00 00 00 00
>393533		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_HELICOPT   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>39353b		00 00 00 00
>39353f		00 26 00 ff 01 3e 00 e4		MIDIW31_INSTRUMENT_APPLAUSE   .text $00, $26, $00, $FF, $01, $3E, $00, $E4, $07, $12, $16, $01
>393547		07 12 16 01
>39354b		00 00 00 f3 f0 3e 00 00		MIDIW31_INSTRUMENT_GUNSHOT    .text $00, $00, $00, $F3, $F0, $3E, $00, $00, $07, $F6, $C9, $02
>393553		07 f6 c9 02
>393557		57 2f 39 00 63 2f 39 00		midiInstrumentsw31 .dword MIDIW31_INSTRUMENT_PIANO1,   MIDIW31_INSTRUMENT_PIANO2,   MIDIW31_INSTRUMENT_PIANO3,   MIDIW31_INSTRUMENT_HONKTONK, MIDIW31_INSTRUMENT_EP1, MIDIW31_INSTRUMENT_EP2
>39355f		6f 2f 39 00 7b 2f 39 00 87 2f 39 00 93 2f 39 00
>39356f		9f 2f 39 00 ab 2f 39 00		                   .dword MIDIW31_INSTRUMENT_HARPSIC,  MIDIW31_INSTRUMENT_CLAVIC,   MIDIW31_INSTRUMENT_CELESTA,  MIDIW31_INSTRUMENT_GLOCK,    MIDIW31_INSTRUMENT_MUSICBOX, MIDIW31_INSTRUMENT_VIBES
>393577		b7 2f 39 00 c3 2f 39 00 cf 2f 39 00 db 2f 39 00
>393587		e7 2f 39 00 f3 2f 39 00			                 .dword MIDIW31_INSTRUMENT_MARIMBA,  MIDIW31_INSTRUMENT_XYLO,     MIDIW31_INSTRUMENT_TUBEBELL, MIDIW31_INSTRUMENT_SANTUR,   MIDIW31_INSTRUMENT_ORGAN1,   MIDIW31_INSTRUMENT_ORGAN2
>39358f		ff 2f 39 00 0b 30 39 00 17 30 39 00 23 30 39 00
>39359f		2f 30 39 00 3b 30 39 00			                 .dword MIDIW31_INSTRUMENT_ORGAN3,   MIDIW31_INSTRUMENT_PIPEORG,  MIDIW31_INSTRUMENT_REEDORG,  MIDIW31_INSTRUMENT_ACORDIAN, MIDIW31_INSTRUMENT_HARMONIC, MIDIW31_INSTRUMENT_BANDNEON
>3935a7		47 30 39 00 53 30 39 00 5f 30 39 00 6b 30 39 00
>3935b7		77 30 39 00 83 30 39 00		                     .dword MIDIW31_INSTRUMENT_NYLONGT,  MIDIW31_INSTRUMENT_STEELGT,  MIDIW31_INSTRUMENT_JAZZGT,   MIDIW31_INSTRUMENT_CLEANGT,  MIDIW31_INSTRUMENT_MUTEGT,   MIDIW31_INSTRUMENT_OVERDGT
>3935bf		8f 30 39 00 9b 30 39 00 a7 30 39 00 b3 30 39 00
>3935cf		bf 30 39 00 cb 30 39 00			                 .dword MIDIW31_INSTRUMENT_DISTGT,   MIDIW31_INSTRUMENT_GTHARMS,  MIDIW31_INSTRUMENT_ACOUBASS, MIDIW31_INSTRUMENT_FINGBASS, MIDIW31_INSTRUMENT_PICKBASS, MIDIW31_INSTRUMENT_FRETLESS
>3935d7		d7 30 39 00 e3 30 39 00 ef 30 39 00 fb 30 39 00
>3935e7		07 31 39 00 13 31 39 00			                 .dword MIDIW31_INSTRUMENT_SLAPBAS1, MIDIW31_INSTRUMENT_SLAPBAS2, MIDIW31_INSTRUMENT_SYNBASS1, MIDIW31_INSTRUMENT_SYNBASS2, MIDIW31_INSTRUMENT_VIOLIN,   MIDIW31_INSTRUMENT_VIOLA
>3935ef		1f 31 39 00 2b 31 39 00 37 31 39 00 43 31 39 00
>3935ff		4f 31 39 00 5b 31 39 00			                 .dword MIDIW31_INSTRUMENT_CELLO,    MIDIW31_INSTRUMENT_CONTRAB,  MIDIW31_INSTRUMENT_TREMSTR,  MIDIW31_INSTRUMENT_PIZZ,     MIDIW31_INSTRUMENT_HARP,     MIDIW31_INSTRUMENT_TIMPANI
>393607		67 31 39 00 73 31 39 00 7f 31 39 00 8b 31 39 00
>393617		97 31 39 00 a3 31 39 00			                 .dword MIDIW31_INSTRUMENT_STRINGS,  MIDIW31_INSTRUMENT_SLOWSTR,  MIDIW31_INSTRUMENT_SYNSTR1,  MIDIW31_INSTRUMENT_SYNSTR2,  MIDIW31_INSTRUMENT_CHOIR,    MIDIW31_INSTRUMENT_OOHS
>39361f		af 31 39 00 bb 31 39 00 c7 31 39 00 d3 31 39 00
>39362f		df 31 39 00 eb 31 39 00			                 .dword MIDIW31_INSTRUMENT_SYNVOX,   MIDIW31_INSTRUMENT_ORCHIT,   MIDIW31_INSTRUMENT_TRUMPET,  MIDIW31_INSTRUMENT_TROMBONE, MIDIW31_INSTRUMENT_TUBA,     MIDIW31_INSTRUMENT_MUTETRP
>393637		f7 31 39 00 03 32 39 00 0f 32 39 00 1b 32 39 00
>393647		27 32 39 00 33 32 39 00			                 .dword MIDIW31_INSTRUMENT_FRHORN,   MIDIW31_INSTRUMENT_BRASS1,   MIDIW31_INSTRUMENT_SYNBRAS1, MIDIW31_INSTRUMENT_SYNBRAS2, MIDIW31_INSTRUMENT_SOPSAX,   MIDIW31_INSTRUMENT_ALTOSAX
>39364f		3f 32 39 00 4b 32 39 00 57 32 39 00 63 32 39 00
>39365f		6f 32 39 00 7b 32 39 00			                 .dword MIDIW31_INSTRUMENT_TENSAX,   MIDIW31_INSTRUMENT_BARISAX,  MIDIW31_INSTRUMENT_OBOE,     MIDIW31_INSTRUMENT_ENGLHORN, MIDIW31_INSTRUMENT_BASSOON,  MIDIW31_INSTRUMENT_CLARINET
>393667		87 32 39 00 93 32 39 00 9f 32 39 00 ab 32 39 00
>393677		b7 32 39 00 c3 32 39 00			                 .dword MIDIW31_INSTRUMENT_PICCOLO,  MIDIW31_INSTRUMENT_FLUTE1,   MIDIW31_INSTRUMENT_RECORDER, MIDIW31_INSTRUMENT_PANFLUTE, MIDIW31_INSTRUMENT_BOTTLEB,  MIDIW31_INSTRUMENT_SHAKU
>39367f		cf 32 39 00 db 32 39 00 e7 32 39 00 f3 32 39 00
>39368f		ff 32 39 00 0b 33 39 00			                 .dword MIDIW31_INSTRUMENT_WHISTLE,  MIDIW31_INSTRUMENT_OCARINA,  MIDIW31_INSTRUMENT_SQUARWAV, MIDIW31_INSTRUMENT_SAWWAV,   MIDIW31_INSTRUMENT_SYNCALLI, MIDIW31_INSTRUMENT_CHIFLEAD
>393697		17 33 39 00 23 33 39 00 2f 33 39 00 3b 33 39 00
>3936a7		47 33 39 00 53 33 39 00			                 .dword MIDIW31_INSTRUMENT_CHARANG,  MIDIW31_INSTRUMENT_SOLOVOX,  MIDIW31_INSTRUMENT_FIFTHSAW, MIDIW31_INSTRUMENT_BASSLEAD, MIDIW31_INSTRUMENT_FANTASIA, MIDIW31_INSTRUMENT_WARMPAD
>3936af		5f 33 39 00 6b 33 39 00 77 33 39 00 83 33 39 00
>3936bf		8f 33 39 00 9b 33 39 00			                 .dword MIDIW31_INSTRUMENT_POLYSYN,  MIDIW31_INSTRUMENT_SPACEVOX, MIDIW31_INSTRUMENT_BOWEDGLS, MIDIW31_INSTRUMENT_METALPAD, MIDIW31_INSTRUMENT_HALOPAD,  MIDIW31_INSTRUMENT_SWEEPPAD
>3936c7		a7 33 39 00 b3 33 39 00 bf 33 39 00 cb 33 39 00
>3936d7		d7 33 39 00 e3 33 39 00			                 .dword MIDIW31_INSTRUMENT_ICERAIN,  MIDIW31_INSTRUMENT_SOUNDTRK, MIDIW31_INSTRUMENT_CRYSTAL,  MIDIW31_INSTRUMENT_ATMOSPH,  MIDIW31_INSTRUMENT_BRIGHT,   MIDIW31_INSTRUMENT_GOBLIN
>3936df		ef 33 39 00 fb 33 39 00 07 34 39 00 13 34 39 00
>3936ef		1f 34 39 00 2b 34 39 00			                 .dword MIDIW31_INSTRUMENT_ECHODROP, MIDIW31_INSTRUMENT_STARTHEM, MIDIW31_INSTRUMENT_SITAR,    MIDIW31_INSTRUMENT_BANJO,    MIDIW31_INSTRUMENT_SHAMISEN, MIDIW31_INSTRUMENT_KOTO
>3936f7		37 34 39 00 43 34 39 00 4f 34 39 00 5b 34 39 00
>393707		67 34 39 00 73 34 39 00			                 .dword MIDIW31_INSTRUMENT_KALIMBA,  MIDIW31_INSTRUMENT_BAGPIPE,  MIDIW31_INSTRUMENT_FIDDLE,   MIDIW31_INSTRUMENT_SHANNAI,  MIDIW31_INSTRUMENT_TINKLBEL, MIDIW31_INSTRUMENT_AGOGO
>39370f		7f 34 39 00 8b 34 39 00 97 34 39 00 a3 34 39 00
>39371f		af 34 39 00 bb 34 39 00			                 .dword MIDIW31_INSTRUMENT_STEELDRM, MIDIW31_INSTRUMENT_WOODBLOK, MIDIW31_INSTRUMENT_TAIKO,    MIDIW31_INSTRUMENT_MELOTOM,  MIDIW31_INSTRUMENT_SYNDRUM,  MIDIW31_INSTRUMENT_REVRSCYM
>393727		c7 34 39 00 d3 34 39 00 df 34 39 00 eb 34 39 00
>393737		f7 34 39 00 03 35 39 00			                 .dword MIDIW31_INSTRUMENT_FRETNOIS, MIDIW31_INSTRUMENT_BRTHNOIS, MIDIW31_INSTRUMENT_SEASHORE, MIDIW31_INSTRUMENT_BIRDS,    MIDIW31_INSTRUMENT_TELEPHON, MIDIW31_INSTRUMENT_HELICOPT
>39373f		0f 35 39 00 1b 35 39 00 27 35 39 00 33 35 39 00
>39374f		3f 35 39 00 4b 35 39 00			                 .dword MIDIW31_INSTRUMENT_APPLAUSE, MIDIW31_INSTRUMENT_GUNSHOT

;******  Return to file: src\OPL2_Library.asm

>393757		3c 42 44 45 47 49 4b 4c		NOTE_INTRO  .byte  $3C, $42, $44, $45, $47, $49, $4B, $4C
.39375f						IOPL2_TONE_TEST
.39375f		e2 20		sep #$20	                SEP #$20        ; set A short
.393761		c2 10		rep #$10	                REP #$10        ; set X long
.393763		a2 00 00	ldx #$0000	                LDX #0
.393766						OPL2_TONE_TESTING_L1
.393766		bf 57 37 39	lda $393757,x	                LDA NOTE_INTRO, X
.39376a		29 0f		and #$0f	                AND #$F
.39376c		85 30		sta $30		                STA OPL2_NOTE ; start at C
.39376e		bf 57 37 39	lda $393757,x	                LDA NOTE_INTRO, X
.393772		29 70		and #$70	                AND #$70
.393774		4a		lsr a		                LSR A
.393775		4a		lsr a		                LSR A
.393776		4a		lsr a		                LSR A
.393777		4a		lsr a		                LSR A
.393778		85 31		sta $31		                STA OPL2_OCTAVE
.39377a		8a		txa		                TXA
.39377b		29 03		and #$03	                AND #$03        ; replace modulo 3 -  play each note on a different channel
.39377d		85 27		sta $27		                STA OPL2_CHANNEL
.39377f		22 4f 39 39	jsl $39394f	                JSL OPL2_PLAYNOTE
.393783		a0 00 00	ldy #$0000	                LDY #$0000
.393786						OPL2_TONE_TESTING_L2
.393786		ea		nop		                NOP
.393787		ea		nop		                NOP
.393788		ea		nop		                NOP
.393789		ea		nop		                NOP
.39378a		c8		iny		                INY
.39378b		c0 ff ff	cpy #$ffff	                CPY #$FFFF
.39378e		d0 f6		bne $393786	                BNE OPL2_TONE_TESTING_L2
.393790		e8		inx		                INX
.393791		e0 08 00	cpx #$0008	                CPX #8
.393794		d0 d0		bne $393766	                BNE OPL2_TONE_TESTING_L1
.393796		6b		rtl		                RTL
.393797						OPL2_INIT
.393797		c2 20		rep #$20	                REP #$20        ; set A long
.393799		a9 00 00	lda #$0000	                LDA #$0000
.39379c		85 28		sta $28		                STA OPL2_REG_REGION
.39379e		85 2a		sta $2a		                STA OPL2_REG_OFFSET
.3937a0		85 30		sta $30		                STA OPL2_NOTE
.3937a2		85 32		sta $32		                STA OPL2_PARAMETER0
.3937a4		85 34		sta $34		                STA OPL2_PARAMETER2
.3937a6		a9 21 17	lda #$1721	                LDA #<>INSTRUMENT_ACCORDN
.3937a9		85 50		sta $50		                STA RAD_ADDR
.3937ab		a9 39 00	lda #$0039	                LDA #<`INSTRUMENT_ACCORDN
.3937ae		85 52		sta $52		                STA RAD_ADDR + 2
.3937b0		e2 20		sep #$20	                SEP #$20        ; set A short
.3937b2		6b		rtl		                RTL
.3937b3						OPL2_Reset
.3937b3		6b		rtl		                RTL
.3937b4						OPL2_Get_FrequencyBlock
.3937b4		6b		rtl		                RTL
.3937b5						OPL2_GET_REGISTER
.3937b5		48		pha		                PHA             ; begin setdp macro
.3937b6		08		php		                PHP
.3937b7		c2 20		rep #$20	                REP #$20        ; set A long
.3937b9		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.3937bc		5b		tcd		                TCD
.3937bd		28		plp		                PLP
.3937be		68		pla		                PLA             ; end setdp macro
.3937bf		c2 20		rep #$20	                REP #$20        ; set A long
.3937c1		18		clc		              CLC
.3937c2		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.3937c5		65 32		adc $32		              ADC OPL2_PARAMETER0
.3937c7		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.3937c9		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.3937cc		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.3937ce		e2 20		sep #$20	                SEP #$20        ; set A short
.3937d0		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.3937d2		6b		rtl		              RTL
.3937d3						OPL2_GET_WAVEFORM_SELECT
.3937d3		48		pha		                PHA             ; begin setdp macro
.3937d4		08		php		                PHP
.3937d5		c2 20		rep #$20	                REP #$20        ; set A long
.3937d7		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.3937da		5b		tcd		                TCD
.3937db		28		plp		                PLP
.3937dc		68		pla		                PLA             ; end setdp macro
.3937dd		c2 20		rep #$20	                REP #$20        ; set A long
.3937df		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.3937e2		69 01 00	adc #$0001	              ADC #$0001
.3937e5		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.3937e7		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.3937ea		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.3937ec		e2 20		sep #$20	                SEP #$20        ; set A short
.3937ee		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.3937f0		29 20		and #$20	              AND #$20
.3937f2		6b		rtl		              RTL
.3937f3						OPL2_GET_SCALINGLEVEL
.3937f3		48		pha		                PHA             ; begin setdp macro
.3937f4		08		php		                PHP
.3937f5		c2 20		rep #$20	                REP #$20        ; set A long
.3937f7		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.3937fa		5b		tcd		                TCD
.3937fb		28		plp		                PLP
.3937fc		68		pla		                PLA             ; end setdp macro
.3937fd		c2 20		rep #$20	                REP #$20        ; set A long
.3937ff		a9 40 00	lda #$0040	              LDA #$0040  ;
.393802		85 28		sta $28		              STA OPL2_REG_REGION
.393804		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393807		e2 20		sep #$20	                SEP #$20        ; set A short
.393809		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.39380b		29 c0		and #$c0	              AND #$C0
.39380d		4a		lsr a		              LSR A
.39380e		4a		lsr a		              LSR A
.39380f		4a		lsr a		              LSR A
.393810		4a		lsr a		              LSR A
.393811		4a		lsr a		              LSR A
.393812		4a		lsr a		              LSR A
.393813		6b		rtl		              RTL
.393814						OPL2_GET_BLOCK
.393814		48		pha		                PHA             ; begin setdp macro
.393815		08		php		                PHP
.393816		c2 20		rep #$20	                REP #$20        ; set A long
.393818		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.39381b		5b		tcd		                TCD
.39381c		28		plp		                PLP
.39381d		68		pla		                PLA             ; end setdp macro
.39381e		e2 20		sep #$20	                SEP #$20        ; set A short
.393820		18		clc		              CLC
.393821		a5 27		lda $27		              LDA OPL2_CHANNEL
.393823		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
.393825		69 b0		adc #$b0	              ADC #$B0
.393827		85 2a		sta $2a		              STA OPL2_REG_OFFSET
.393829		a9 00		lda #$00	              LDA #$00
.39382b		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
.39382d		c2 30		rep #$30	                REP #$30        ; set A&X long
.39382f		18		clc		              CLC
.393830		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.393833		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
.393835		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393837		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.39383a		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.39383c		e2 20		sep #$20	                SEP #$20        ; set A short
.39383e		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393840		29 1c		and #$1c	              AND #$1C
.393842		4a		lsr a		              LSR A
.393843		4a		lsr a		              LSR A
.393844		6b		rtl		              RTL
.393845						OPL2_GET_KEYON
.393845		48		pha		                PHA             ; begin setdp macro
.393846		08		php		                PHP
.393847		c2 20		rep #$20	                REP #$20        ; set A long
.393849		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.39384c		5b		tcd		                TCD
.39384d		28		plp		                PLP
.39384e		68		pla		                PLA             ; end setdp macro
.39384f		e2 20		sep #$20	                SEP #$20        ; set A short
.393851		18		clc		              CLC
.393852		a5 27		lda $27		              LDA OPL2_CHANNEL
.393854		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
.393856		69 b0		adc #$b0	              ADC #$B0
.393858		85 2a		sta $2a		              STA OPL2_REG_OFFSET
.39385a		a9 00		lda #$00	              LDA #$00
.39385c		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
.39385e		c2 30		rep #$30	                REP #$30        ; set A&X long
.393860		18		clc		              CLC
.393861		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.393864		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
.393866		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393868		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.39386b		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.39386d		e2 20		sep #$20	                SEP #$20        ; set A short
.39386f		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393871		29 20		and #$20	              AND #$20
.393873		6b		rtl		              RTL
.393874						OPL2_GET_FEEDBACK
.393874		48		pha		                PHA             ; begin setdp macro
.393875		08		php		                PHP
.393876		c2 20		rep #$20	                REP #$20        ; set A long
.393878		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.39387b		5b		tcd		                TCD
.39387c		28		plp		                PLP
.39387d		68		pla		                PLA             ; end setdp macro
.39387e		e2 20		sep #$20	                SEP #$20        ; set A short
.393880		18		clc		              CLC
.393881		a5 27		lda $27		              LDA OPL2_CHANNEL
.393883		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
.393885		69 c0		adc #$c0	              ADC #$C0
.393887		85 2a		sta $2a		              STA OPL2_REG_OFFSET
.393889		a9 00		lda #$00	              LDA #$00
.39388b		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
.39388d		c2 30		rep #$30	                REP #$30        ; set A&X long
.39388f		18		clc		              CLC
.393890		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.393893		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
.393895		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393897		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.39389a		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.39389c		e2 20		sep #$20	                SEP #$20        ; set A short
.39389e		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.3938a0		29 e0		and #$e0	              AND #$E0
.3938a2		4a		lsr a		              LSR
.3938a3		6b		rtl		              RTL
.3938a4						OPL2_GET_SYNTHMODE
.3938a4		48		pha		                PHA             ; begin setdp macro
.3938a5		08		php		                PHP
.3938a6		c2 20		rep #$20	                REP #$20        ; set A long
.3938a8		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.3938ab		5b		tcd		                TCD
.3938ac		28		plp		                PLP
.3938ad		68		pla		                PLA             ; end setdp macro
.3938ae		e2 20		sep #$20	                SEP #$20        ; set A short
.3938b0		18		clc		              CLC
.3938b1		a5 27		lda $27		              LDA OPL2_CHANNEL
.3938b3		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
.3938b5		69 c0		adc #$c0	              ADC #$C0
.3938b7		85 2a		sta $2a		              STA OPL2_REG_OFFSET
.3938b9		a9 00		lda #$00	              LDA #$00
.3938bb		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
.3938bd		c2 30		rep #$30	                REP #$30        ; set A&X long
.3938bf		18		clc		              CLC
.3938c0		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.3938c3		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
.3938c5		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.3938c7		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.3938ca		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.3938cc		e2 20		sep #$20	                SEP #$20        ; set A short
.3938ce		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.3938d0		29 01		and #$01	              AND #$01
.3938d2		6b		rtl		              RTL
.3938d3						OPL2_GET_DEEPTREMOLO
.3938d3		48		pha		                PHA             ; begin setdp macro
.3938d4		08		php		                PHP
.3938d5		c2 20		rep #$20	                REP #$20        ; set A long
.3938d7		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.3938da		5b		tcd		                TCD
.3938db		28		plp		                PLP
.3938dc		68		pla		                PLA             ; end setdp macro
.3938dd		c2 20		rep #$20	                REP #$20        ; set A long
.3938df		a9 bd 00	lda #$00bd	              LDA #$00BD;
.3938e2		85 28		sta $28		              STA OPL2_REG_REGION
.3938e4		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.3938e7		e2 20		sep #$20	                SEP #$20        ; set A short
.3938e9		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.3938eb		29 80		and #$80	              AND #$80
.3938ed		6b		rtl		              RTL
.3938ee						OPL2_GET_DEEPVIBRATO
.3938ee		48		pha		                PHA             ; begin setdp macro
.3938ef		08		php		                PHP
.3938f0		c2 20		rep #$20	                REP #$20        ; set A long
.3938f2		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.3938f5		5b		tcd		                TCD
.3938f6		28		plp		                PLP
.3938f7		68		pla		                PLA             ; end setdp macro
.3938f8		c2 20		rep #$20	                REP #$20        ; set A long
.3938fa		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.3938fd		69 bd 00	adc #$00bd	              ADC #$00BD
.393900		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393902		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.393905		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.393907		e2 20		sep #$20	                SEP #$20        ; set A short
.393909		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.39390b		29 40		and #$40	              AND #$40
.39390d		6b		rtl		              RTL
.39390e						OPL2_GET_PERCUSSION
.39390e		48		pha		                PHA             ; begin setdp macro
.39390f		08		php		                PHP
.393910		c2 20		rep #$20	                REP #$20        ; set A long
.393912		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393915		5b		tcd		                TCD
.393916		28		plp		                PLP
.393917		68		pla		                PLA             ; end setdp macro
.393918		c2 20		rep #$20	                REP #$20        ; set A long
.39391a		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.39391d		69 bd 00	adc #$00bd	              ADC #$00BD
.393920		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393922		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.393925		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.393927		e2 20		sep #$20	                SEP #$20        ; set A short
.393929		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.39392b		29 20		and #$20	              AND #$20
.39392d		6b		rtl		              RTL
.39392e						OPL2_GET_DRUMS
.39392e		48		pha		                PHA             ; begin setdp macro
.39392f		08		php		                PHP
.393930		c2 20		rep #$20	                REP #$20        ; set A long
.393932		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393935		5b		tcd		                TCD
.393936		28		plp		                PLP
.393937		68		pla		                PLA             ; end setdp macro
.393938		c2 20		rep #$20	                REP #$20        ; set A long
.39393a		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.39393d		69 bd 00	adc #$00bd	              ADC #$00BD
.393940		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393942		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.393945		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.393947		e2 20		sep #$20	                SEP #$20        ; set A short
.393949		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.39394b		29 1f		and #$1f	              AND #$1F
.39394d		6b		rtl		              RTL
.39394e						OPL2_Get_WaveForm
.39394e		6b		rtl		                RTL
.39394f						OPL2_PLAYNOTE
.39394f		48		pha		                PHA             ; begin setdp macro
.393950		08		php		                PHP
.393951		c2 20		rep #$20	                REP #$20        ; set A long
.393953		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393956		5b		tcd		                TCD
.393957		28		plp		                PLP
.393958		68		pla		                PLA             ; end setdp macro
.393959		e2 20		sep #$20	                SEP #$20        ; set A short
.39395b		da		phx		                PHX
.39395c		a9 00		lda #$00	                LDA #$00
.39395e		85 32		sta $32		                STA OPL2_PARAMETER0 ; Set Keyon False
.393960		20 37 3f	jsr $393f37	                JSR OPL2_SET_KEYON
.393963		20 fc 3e	jsr $393efc	                JSR OPL2_SET_BLOCK  ; OPL2_SET_BLOCK Already to OPL2_OCTAVE
.393966		e2 10		sep #$10	                SEP #$10        ; set X short
.393968		a5 30		lda $30		                LDA OPL2_NOTE
.39396a		3a		dec a		                DEC A
.39396b		0a		asl a		                ASL A
.39396c		aa		tax		                TAX
.39396d		bf e6 16 39	lda $3916e6,x	                LDA @lnoteFNumbers,X
.393971		85 32		sta $32		                STA OPL2_PARAMETER0 ; Store the 8it in Param OPL2_PARAMETER0
.393973		e8		inx		                INX
.393974		bf e6 16 39	lda $3916e6,x	                LDA @lnoteFNumbers,X
.393978		85 33		sta $33		                STA OPL2_PARAMETER1 ; Store the 8bit in Param OPL2_PARAMETER1
.39397a		22 7a 3e 39	jsl $393e7a	                JSL OPL2_SET_FNUMBER
.39397e		a9 01		lda #$01	                LDA #$01
.393980		85 32		sta $32		                STA OPL2_PARAMETER0 ; Set Keyon False
.393982		20 37 3f	jsr $393f37	                JSR OPL2_SET_KEYON
.393985		c2 10		rep #$10	                REP #$10        ; set X long
.393987		fa		plx		                PLX
.393988		6b		rtl		                RTL
.393989						OPL2_PLAYDRUM
.393989		6b		rtl		                RTL
.39398a						OPL2_SET_INSTRUMENT
.39398a		48		pha		                PHA             ; begin setdp macro
.39398b		08		php		                PHP
.39398c		c2 20		rep #$20	                REP #$20        ; set A long
.39398e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393991		5b		tcd		                TCD
.393992		28		plp		                PLP
.393993		68		pla		                PLA             ; end setdp macro
.393994		38		sec		              SEC ; Set the WaveFormSelect to True
.393995		22 78 3b 39	jsl $393b78	              JSL OPL2_SET_WAVEFORMSELECT;
.393999		e2 20		sep #$20	                SEP #$20        ; set A short
.39399b		c2 10		rep #$10	                REP #$10        ; set X long
.39399d		a0 00 00	ldy #$0000	              LDY #$0000
.3939a0		a2 00 00	ldx #$0000	              LDX #$0000
.3939a3		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO],Y ; Pointer Location 0 in Instrument Profile
.3939a5		85 35		sta $35		              STA OPL2_PARAMETER3
.3939a7		c8		iny		              INY
.3939a8		c9 06		cmp #$06	              CMP #$06
.3939aa		d0 03		bne $3939af	              BNE PERCUSSION_NEXT07
.3939ac		82 70 01	brl $393b1f	              BRL Percussion_6
.3939af						PERCUSSION_NEXT07
.3939af		c9 07		cmp #$07	              CMP #$07
.3939b1		d0 03		bne $3939b6	              BNE PERCUSSION_NEXT08
.3939b3		82 44 01	brl $393afa	              BRL Percussion_7
.3939b6						PERCUSSION_NEXT08
.3939b6		c9 08		cmp #$08	              CMP #$08
.3939b8		d0 03		bne $3939bd	              BNE PERCUSSION_NEXT09
.3939ba		82 18 01	brl $393ad5	              BRL Percussion_8
.3939bd						PERCUSSION_NEXT09
.3939bd		c9 09		cmp #$09	              CMP #$09
.3939bf		d0 03		bne $3939c4	              BNE PERCUSSION_NEXT0A
.3939c1		82 ec 00	brl $393ab0	              BRL Percussion_9
.3939c4						PERCUSSION_NEXT0A
.3939c4		c9 0a		cmp #$0a	              CMP #$0A
.3939c6		d0 03		bne $3939cb	              BNE Percussion_Default
.3939c8		82 c0 00	brl $393a8b	              BRL Percussion_A
.3939cb						Percussion_Default
.3939cb		a9 00		lda #$00	              LDA #$00
.3939cd		85 26		sta $26		              STA OPL2_OPERATOR
.3939cf		c2 20		rep #$20	                REP #$20        ; set A long
.3939d1		a9 20 00	lda #$0020	              LDA #$0020;
.3939d4		85 28		sta $28		              STA OPL2_REG_REGION
.3939d6		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.3939d9		e2 20		sep #$20	                SEP #$20        ; set A short
.3939db		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
.3939dd		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.3939df		c8		iny		              INY
.3939e0		c2 20		rep #$20	                REP #$20        ; set A long
.3939e2		a9 40 00	lda #$0040	              LDA #$0040;
.3939e5		85 28		sta $28		              STA OPL2_REG_REGION
.3939e7		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.3939ea		e2 20		sep #$20	                SEP #$20        ; set A short
.3939ec		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
.3939ee		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.3939f0		c8		iny		              INY
.3939f1		c2 20		rep #$20	                REP #$20        ; set A long
.3939f3		a9 60 00	lda #$0060	              LDA #$0060;
.3939f6		85 28		sta $28		              STA OPL2_REG_REGION
.3939f8		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.3939fb		e2 20		sep #$20	                SEP #$20        ; set A short
.3939fd		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
.3939ff		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393a01		c8		iny		              INY
.393a02		c2 20		rep #$20	                REP #$20        ; set A long
.393a04		a9 80 00	lda #$0080	              LDA #$0080;
.393a07		85 28		sta $28		              STA OPL2_REG_REGION
.393a09		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393a0c		e2 20		sep #$20	                SEP #$20        ; set A short
.393a0e		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
.393a10		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393a12		c8		iny		              INY
.393a13		c2 20		rep #$20	                REP #$20        ; set A long
.393a15		a9 e0 00	lda #$00e0	              LDA #$00E0;
.393a18		85 28		sta $28		              STA OPL2_REG_REGION
.393a1a		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393a1d		e2 20		sep #$20	                SEP #$20        ; set A short
.393a1f		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
.393a21		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393a23		c8		iny		              INY
.393a24		e2 10		sep #$10	                SEP #$10        ; set X short
.393a26		a5 27		lda $27		              LDA OPL2_CHANNEL
.393a28		29 0f		and #$0f	              AND #$0F
.393a2a		aa		tax		              TAX
.393a2b		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 6 in Instrument Profile
.393a2d		9f c0 e6 af	sta $afe6c0,x	              STA @lOPL3_R_FEEDBACK,X
.393a31		c8		iny		              INY
.393a32		a9 01		lda #$01	              LDA #$01
.393a34		85 26		sta $26		              STA OPL2_OPERATOR
.393a36		c2 20		rep #$20	                REP #$20        ; set A long
.393a38		a9 20 00	lda #$0020	              LDA #$0020;
.393a3b		85 28		sta $28		              STA OPL2_REG_REGION
.393a3d		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393a40		e2 20		sep #$20	                SEP #$20        ; set A short
.393a42		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 7 in Instrument Profile
.393a44		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393a46		c8		iny		              INY
.393a47		c2 20		rep #$20	                REP #$20        ; set A long
.393a49		a9 40 00	lda #$0040	              LDA #$0040;
.393a4c		85 28		sta $28		              STA OPL2_REG_REGION
.393a4e		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393a51		e2 20		sep #$20	                SEP #$20        ; set A short
.393a53		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 8 in Instrument Profile
.393a55		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393a57		c8		iny		              INY
.393a58		c2 20		rep #$20	                REP #$20        ; set A long
.393a5a		a9 60 00	lda #$0060	              LDA #$0060;
.393a5d		85 28		sta $28		              STA OPL2_REG_REGION
.393a5f		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393a62		e2 20		sep #$20	                SEP #$20        ; set A short
.393a64		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 9 in Instrument Profile
.393a66		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393a68		c8		iny		              INY
.393a69		c2 20		rep #$20	                REP #$20        ; set A long
.393a6b		a9 80 00	lda #$0080	              LDA #$0080;
.393a6e		85 28		sta $28		              STA OPL2_REG_REGION
.393a70		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393a73		e2 20		sep #$20	                SEP #$20        ; set A short
.393a75		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location A in Instrument Profile
.393a77		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393a79		c8		iny		              INY
.393a7a		c2 20		rep #$20	                REP #$20        ; set A long
.393a7c		a9 e0 00	lda #$00e0	              LDA #$00E0;
.393a7f		85 28		sta $28		              STA OPL2_REG_REGION
.393a81		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393a84		e2 20		sep #$20	                SEP #$20        ; set A short
.393a86		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location B in Instrument Profile
.393a88		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393a8a		6b		rtl		                RTL
.393a8b						Percussion_A
.393a8b		e2 20		sep #$20	                SEP #$20        ; set A short
.393a8d		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
.393a8f		8f 31 e6 af	sta $afe631	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $11
.393a93		c8		iny		              INY
.393a94		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
.393a96		8f 51 e6 af	sta $afe651	              STA @lOPL3_R_KSL_TL + $11
.393a9a		c8		iny		              INY
.393a9b		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
.393a9d		8f 71 e6 af	sta $afe671	              STA @lOPL3_R_AR_DR + $11
.393aa1		c8		iny		              INY
.393aa2		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
.393aa4		8f 91 e6 af	sta $afe691	              STA @lOPL3_R_SL_RR + $11
.393aa8		c8		iny		              INY
.393aa9		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
.393aab		8f f1 e6 af	sta $afe6f1	              STA @lOPL3_R_WAVE_SELECT + $11
.393aaf		6b		rtl		                RTL
.393ab0						Percussion_9
.393ab0		e2 20		sep #$20	                SEP #$20        ; set A short
.393ab2		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
.393ab4		8f 35 e6 af	sta $afe635	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $15
.393ab8		c8		iny		              INY
.393ab9		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
.393abb		8f 55 e6 af	sta $afe655	              STA @lOPL3_R_KSL_TL + $15
.393abf		c8		iny		              INY
.393ac0		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
.393ac2		8f 75 e6 af	sta $afe675	              STA @lOPL3_R_AR_DR + $15
.393ac6		c8		iny		              INY
.393ac7		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
.393ac9		8f 95 e6 af	sta $afe695	              STA @lOPL3_R_SL_RR + $15
.393acd		c8		iny		              INY
.393ace		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
.393ad0		8f f5 e6 af	sta $afe6f5	              STA @lOPL3_R_WAVE_SELECT + $15
.393ad4		6b		rtl		              RTL
.393ad5						Percussion_8
.393ad5		e2 20		sep #$20	                SEP #$20        ; set A short
.393ad7		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
.393ad9		8f 32 e6 af	sta $afe632	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $12
.393add		c8		iny		              INY
.393ade		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
.393ae0		8f 52 e6 af	sta $afe652	              STA @lOPL3_R_KSL_TL + $12
.393ae4		c8		iny		              INY
.393ae5		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
.393ae7		8f 72 e6 af	sta $afe672	              STA @lOPL3_R_AR_DR + $12
.393aeb		c8		iny		              INY
.393aec		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
.393aee		8f 92 e6 af	sta $afe692	              STA @lOPL3_R_SL_RR + $12
.393af2		c8		iny		              INY
.393af3		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
.393af5		8f f2 e6 af	sta $afe6f2	              STA @lOPL3_R_WAVE_SELECT + $12
.393af9		6b		rtl		              RTL
.393afa						Percussion_7
.393afa		e2 20		sep #$20	                SEP #$20        ; set A short
.393afc		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
.393afe		8f 34 e6 af	sta $afe634	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $14
.393b02		c8		iny		              INY
.393b03		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
.393b05		8f 54 e6 af	sta $afe654	              STA @lOPL3_R_KSL_TL + $14
.393b09		c8		iny		              INY
.393b0a		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
.393b0c		8f 74 e6 af	sta $afe674	              STA @lOPL3_R_AR_DR + $14
.393b10		c8		iny		              INY
.393b11		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
.393b13		8f 94 e6 af	sta $afe694	              STA @lOPL3_R_SL_RR + $14
.393b17		c8		iny		              INY
.393b18		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
.393b1a		8f f4 e6 af	sta $afe6f4	              STA @lOPL3_R_WAVE_SELECT + $14
.393b1e		6b		rtl		              RTL
.393b1f						Percussion_6
.393b1f		e2 20		sep #$20	                SEP #$20        ; set A short
.393b21		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
.393b23		8f 30 e6 af	sta $afe630	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $10
.393b27		8f 33 e6 af	sta $afe633	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $13
.393b2b		c8		iny		              INY
.393b2c		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
.393b2e		8f 50 e6 af	sta $afe650	              STA @lOPL3_R_KSL_TL + $10
.393b32		8f 53 e6 af	sta $afe653	              STA @lOPL3_R_KSL_TL + $13
.393b36		c8		iny		              INY
.393b37		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
.393b39		8f 70 e6 af	sta $afe670	              STA @lOPL3_R_AR_DR + $10
.393b3d		8f 73 e6 af	sta $afe673	              STA @lOPL3_R_AR_DR + $13
.393b41		c8		iny		              INY
.393b42		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
.393b44		8f 90 e6 af	sta $afe690	              STA @lOPL3_R_SL_RR + $10
.393b48		8f 93 e6 af	sta $afe693	              STA @lOPL3_R_SL_RR + $13
.393b4c		c8		iny		              INY
.393b4d		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
.393b4f		8f f0 e6 af	sta $afe6f0	              STA @lOPL3_R_WAVE_SELECT + $10
.393b53		8f f3 e6 af	sta $afe6f3	              STA @lOPL3_R_WAVE_SELECT + $13
.393b57		6b		rtl		              RTL
.393b58						OPL2_SET_REGISTER
.393b58		48		pha		                PHA             ; begin setdp macro
.393b59		08		php		                PHP
.393b5a		c2 20		rep #$20	                REP #$20        ; set A long
.393b5c		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393b5f		5b		tcd		                TCD
.393b60		28		plp		                PLP
.393b61		68		pla		                PLA             ; end setdp macro
.393b62		c2 20		rep #$20	                REP #$20        ; set A long
.393b64		18		clc		              CLC
.393b65		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.393b68		65 32		adc $32		              ADC OPL2_PARAMETER0
.393b6a		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393b6c		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.393b6f		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.393b71		e2 20		sep #$20	                SEP #$20        ; set A short
.393b73		a5 33		lda $33		              LDA OPL2_PARAMETER1
.393b75		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393b77		6b		rtl		              RTL
.393b78						OPL2_SET_WAVEFORMSELECT
.393b78		48		pha		                PHA             ; begin setdp macro
.393b79		08		php		                PHP
.393b7a		c2 20		rep #$20	                REP #$20        ; set A long
.393b7c		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393b7f		5b		tcd		                TCD
.393b80		28		plp		                PLP
.393b81		68		pla		                PLA             ; end setdp macro
.393b82		c2 20		rep #$20	                REP #$20        ; set A long
.393b84		a9 01 e6	lda #$e601	              LDA #<>OPL3_R_BASE + $0001
.393b87		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393b89		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.393b8c		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.393b8e		e2 20		sep #$20	                SEP #$20        ; set A short
.393b90		b0 07		bcs $393b99	              BCS OPL2_Set_WaveFormSelect_set
.393b92		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393b94		29 df		and #$df	              AND #$DF
.393b96		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393b98		6b		rtl		              RTL
.393b99						OPL2_Set_WaveFormSelect_set
.393b99		48		pha		                PHA             ; begin setdp macro
.393b9a		08		php		                PHP
.393b9b		c2 20		rep #$20	                REP #$20        ; set A long
.393b9d		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393ba0		5b		tcd		                TCD
.393ba1		28		plp		                PLP
.393ba2		68		pla		                PLA             ; end setdp macro
.393ba3		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393ba5		09 20 00	ora #$0020	              ORA #$20
.393ba8		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393baa		6b		rtl		                RTL
.393bab						OPL2_SET_TREMOLO
.393bab		48		pha		                PHA             ; begin setdp macro
.393bac		08		php		                PHP
.393bad		c2 20		rep #$20	                REP #$20        ; set A long
.393baf		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393bb2		5b		tcd		                TCD
.393bb3		28		plp		                PLP
.393bb4		68		pla		                PLA             ; end setdp macro
.393bb5		08		php		                PHP ; Push the Carry
.393bb6		c2 20		rep #$20	                REP #$20        ; set A long
.393bb8		18		clc		                CLC
.393bb9		a9 20 00	lda #$0020	                LDA #$0020 ;
.393bbc		85 28		sta $28		                STA OPL2_REG_REGION
.393bbe		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393bc1		28		plp		                PLP ; Pull the Carry out
.393bc2		e2 20		sep #$20	                SEP #$20        ; set A short
.393bc4		b0 08		bcs $393bce	                BCS OPL2_Set_Tremolo_Set;
.393bc6		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393bc8		29 7f		and #$7f	                AND #$7F
.393bca		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393bcc		80 06		bra $393bd4	                BRA OPL2_Set_Tremolo_Exit
.393bce						OPL2_Set_Tremolo_Set
.393bce		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393bd0		09 80		ora #$80	                ORA #$80
.393bd2		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393bd4						OPL2_Set_Tremolo_Exit
.393bd4		6b		rtl		                RTL
.393bd5						OPL2_GET_TREMOLO
.393bd5		48		pha		                PHA             ; begin setdp macro
.393bd6		08		php		                PHP
.393bd7		c2 20		rep #$20	                REP #$20        ; set A long
.393bd9		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393bdc		5b		tcd		                TCD
.393bdd		28		plp		                PLP
.393bde		68		pla		                PLA             ; end setdp macro
.393bdf		c2 20		rep #$20	                REP #$20        ; set A long
.393be1		a9 20 00	lda #$0020	                LDA #$0020;
.393be4		85 28		sta $28		                STA OPL2_REG_REGION
.393be6		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393be9		e2 20		sep #$20	                SEP #$20        ; set A short
.393beb		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393bed		29 80		and #$80	                AND #$80
.393bef		6b		rtl		                RTL
.393bf0						OPL2_SET_VIBRATO
.393bf0		48		pha		                PHA             ; begin setdp macro
.393bf1		08		php		                PHP
.393bf2		c2 20		rep #$20	                REP #$20        ; set A long
.393bf4		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393bf7		5b		tcd		                TCD
.393bf8		28		plp		                PLP
.393bf9		68		pla		                PLA             ; end setdp macro
.393bfa		08		php		                PHP ; Push the Carry
.393bfb		c2 20		rep #$20	                REP #$20        ; set A long
.393bfd		18		clc		                CLC
.393bfe		a9 20 00	lda #$0020	                LDA #$0020;
.393c01		85 28		sta $28		                STA OPL2_REG_REGION
.393c03		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393c06		28		plp		                PLP ; Pull the Carry out
.393c07		e2 20		sep #$20	                SEP #$20        ; set A short
.393c09		b0 08		bcs $393c13	                BCS OPL2_Set_Vibrato_Set;
.393c0b		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393c0d		29 bf		and #$bf	                AND #$BF
.393c0f		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393c11		80 06		bra $393c19	                BRA OPL2_Set_Vibrato_Exit
.393c13						OPL2_Set_Vibrato_Set
.393c13		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393c15		09 40		ora #$40	                ORA #$40
.393c17		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393c19						OPL2_Set_Vibrato_Exit
.393c19		6b		rtl		                RTL
.393c1a						OPL2_GET_VIBRATO
.393c1a		48		pha		                PHA             ; begin setdp macro
.393c1b		08		php		                PHP
.393c1c		c2 20		rep #$20	                REP #$20        ; set A long
.393c1e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393c21		5b		tcd		                TCD
.393c22		28		plp		                PLP
.393c23		68		pla		                PLA             ; end setdp macro
.393c24		c2 20		rep #$20	                REP #$20        ; set A long
.393c26		a9 20 00	lda #$0020	                LDA #$0020;
.393c29		85 28		sta $28		                STA OPL2_REG_REGION
.393c2b		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393c2e		e2 20		sep #$20	                SEP #$20        ; set A short
.393c30		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393c32		29 40		and #$40	                AND #$40
.393c34		6b		rtl		                RTL
.393c35						OPL2_SET_MAINTAINSUSTAIN
.393c35		48		pha		                PHA             ; begin setdp macro
.393c36		08		php		                PHP
.393c37		c2 20		rep #$20	                REP #$20        ; set A long
.393c39		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393c3c		5b		tcd		                TCD
.393c3d		28		plp		                PLP
.393c3e		68		pla		                PLA             ; end setdp macro
.393c3f		08		php		              PHP ; Push the Carry
.393c40		c2 20		rep #$20	                REP #$20        ; set A long
.393c42		18		clc		              CLC
.393c43		a9 20 00	lda #$0020	              LDA #$0020;
.393c46		85 28		sta $28		              STA OPL2_REG_REGION
.393c48		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393c4b		28		plp		              PLP ; Pull the Carry out
.393c4c		e2 20		sep #$20	                SEP #$20        ; set A short
.393c4e		b0 08		bcs $393c58	              BCS OPL2_Set_MaintainSustain_Set;
.393c50		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393c52		29 df		and #$df	              AND #$DF
.393c54		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393c56		80 06		bra $393c5e	              BRA OPL2_Set_MaintainSustain_Exit
.393c58						OPL2_Set_MaintainSustain_Set
.393c58		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393c5a		09 20		ora #$20	              ORA #$20
.393c5c		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393c5e						OPL2_Set_MaintainSustain_Exit
.393c5e		6b		rtl		                RTL
.393c5f						OPL2_GET_MAINTAINSUSTAIN
.393c5f		48		pha		                PHA             ; begin setdp macro
.393c60		08		php		                PHP
.393c61		c2 20		rep #$20	                REP #$20        ; set A long
.393c63		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393c66		5b		tcd		                TCD
.393c67		28		plp		                PLP
.393c68		68		pla		                PLA             ; end setdp macro
.393c69		c2 20		rep #$20	                REP #$20        ; set A long
.393c6b		a9 20 00	lda #$0020	              LDA #$0020;
.393c6e		85 28		sta $28		              STA OPL2_REG_REGION
.393c70		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393c73		e2 20		sep #$20	                SEP #$20        ; set A short
.393c75		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393c77		29 20		and #$20	              AND #$20
.393c79		6b		rtl		                RTL
.393c7a						OPL2_SET_ENVELOPESCALING
.393c7a		48		pha		                PHA             ; begin setdp macro
.393c7b		08		php		                PHP
.393c7c		c2 20		rep #$20	                REP #$20        ; set A long
.393c7e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393c81		5b		tcd		                TCD
.393c82		28		plp		                PLP
.393c83		68		pla		                PLA             ; end setdp macro
.393c84		08		php		              PHP ; Push the Carry
.393c85		c2 20		rep #$20	                REP #$20        ; set A long
.393c87		18		clc		              CLC
.393c88		a9 20 00	lda #$0020	              LDA #$0020;
.393c8b		85 28		sta $28		              STA OPL2_REG_REGION
.393c8d		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393c90		28		plp		              PLP ; Pull the Carry out
.393c91		e2 20		sep #$20	                SEP #$20        ; set A short
.393c93		b0 08		bcs $393c9d	              BCS OPL2_Set_EnvelopeScaling_Set;
.393c95		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393c97		29 ef		and #$ef	              AND #$EF
.393c99		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393c9b		80 06		bra $393ca3	              BRA OPL2_Set_EnvelopeScaling_Exit
.393c9d						OPL2_Set_EnvelopeScaling_Set
.393c9d		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393c9f		09 10		ora #$10	              ORA #$10
.393ca1		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393ca3						OPL2_Set_EnvelopeScaling_Exit
.393ca3		6b		rtl		                RTL
.393ca4						OPL2_GET_ENVELOPESCALING
.393ca4		48		pha		                PHA             ; begin setdp macro
.393ca5		08		php		                PHP
.393ca6		c2 20		rep #$20	                REP #$20        ; set A long
.393ca8		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393cab		5b		tcd		                TCD
.393cac		28		plp		                PLP
.393cad		68		pla		                PLA             ; end setdp macro
.393cae		c2 20		rep #$20	                REP #$20        ; set A long
.393cb0		a9 20 00	lda #$0020	              LDA #$0020;
.393cb3		85 28		sta $28		              STA OPL2_REG_REGION
.393cb5		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393cb8		e2 20		sep #$20	                SEP #$20        ; set A short
.393cba		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393cbc		29 10		and #$10	              AND #$10
.393cbe		6b		rtl		                RTL
.393cbf						OPL2_GET_MODFREQMULTIPLE
.393cbf		48		pha		                PHA             ; begin setdp macro
.393cc0		08		php		                PHP
.393cc1		c2 20		rep #$20	                REP #$20        ; set A long
.393cc3		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393cc6		5b		tcd		                TCD
.393cc7		28		plp		                PLP
.393cc8		68		pla		                PLA             ; end setdp macro
.393cc9		c2 20		rep #$20	                REP #$20        ; set A long
.393ccb		a9 20 00	lda #$0020	              LDA #$0020;
.393cce		85 28		sta $28		              STA OPL2_REG_REGION
.393cd0		20 b6 40	jsr $3940b6	              JSR OPL2_GET_REG_OFFSET
.393cd3		e2 20		sep #$20	                SEP #$20        ; set A short
.393cd5		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393cd7		29 0f		and #$0f	              AND #$0F
.393cd9		6b		rtl		              RTL
.393cda						OPL2_SET_MODFREQMULTIPLE
.393cda		48		pha		                PHA             ; begin setdp macro
.393cdb		08		php		                PHP
.393cdc		c2 20		rep #$20	                REP #$20        ; set A long
.393cde		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393ce1		5b		tcd		                TCD
.393ce2		28		plp		                PLP
.393ce3		68		pla		                PLA             ; end setdp macro
.393ce4		c2 20		rep #$20	                REP #$20        ; set A long
.393ce6		a9 20 00	lda #$0020	                LDA #$0020;
.393ce9		85 28		sta $28		                STA OPL2_REG_REGION
.393ceb		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393cee		e2 20		sep #$20	                SEP #$20        ; set A short
.393cf0		a5 32		lda $32		                LDA OPL2_PARAMETER0
.393cf2		29 0f		and #$0f	                AND #$0F
.393cf4		85 32		sta $32		                STA OPL2_PARAMETER0
.393cf6		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393cf8		29 f0		and #$f0	                AND #$F0
.393cfa		05 32		ora $32		                ORA OPL2_PARAMETER0
.393cfc		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393cfe		6b		rtl		                RTL
.393cff						OPL2_SET_SCALINGLEVEL
.393cff		48		pha		                PHA             ; begin setdp macro
.393d00		08		php		                PHP
.393d01		c2 20		rep #$20	                REP #$20        ; set A long
.393d03		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393d06		5b		tcd		                TCD
.393d07		28		plp		                PLP
.393d08		68		pla		                PLA             ; end setdp macro
.393d09		c2 20		rep #$20	                REP #$20        ; set A long
.393d0b		a9 40 00	lda #$0040	                LDA #$0040;
.393d0e		85 28		sta $28		                STA OPL2_REG_REGION
.393d10		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393d13		e2 20		sep #$20	                SEP #$20        ; set A short
.393d15		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
.393d17		29 03		and #$03	                AND #$03
.393d19		0a		asl a		                ASL
.393d1a		0a		asl a		                ASL
.393d1b		0a		asl a		                ASL
.393d1c		0a		asl a		                ASL
.393d1d		0a		asl a		                ASL
.393d1e		0a		asl a		                ASL
.393d1f		85 32		sta $32		                STA OPL2_PARAMETER0
.393d21		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393d23		29 3f		and #$3f	                AND #$3F
.393d25		05 32		ora $32		                ORA OPL2_PARAMETER0
.393d27		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393d29		6b		rtl		                RTL
.393d2a						OPL2_SET_VOLUME
.393d2a		48		pha		                PHA             ; begin setdp macro
.393d2b		08		php		                PHP
.393d2c		c2 20		rep #$20	                REP #$20        ; set A long
.393d2e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393d31		5b		tcd		                TCD
.393d32		28		plp		                PLP
.393d33		68		pla		                PLA             ; end setdp macro
.393d34		c2 20		rep #$20	                REP #$20        ; set A long
.393d36		a9 40 00	lda #$0040	                LDA #$0040  ;
.393d39		85 28		sta $28		                STA OPL2_REG_REGION
.393d3b		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393d3e		e2 20		sep #$20	                SEP #$20        ; set A short
.393d40		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Volume
.393d42		29 3f		and #$3f	                AND #$3F
.393d44		85 32		sta $32		                STA OPL2_PARAMETER0
.393d46		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393d48		29 c0		and #$c0	                AND #$C0
.393d4a		05 32		ora $32		                ORA OPL2_PARAMETER0
.393d4c		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393d4e		6b		rtl		                RTL
.393d4f						OPL2_GET_VOLUME
.393d4f		48		pha		                PHA             ; begin setdp macro
.393d50		08		php		                PHP
.393d51		c2 20		rep #$20	                REP #$20        ; set A long
.393d53		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393d56		5b		tcd		                TCD
.393d57		28		plp		                PLP
.393d58		68		pla		                PLA             ; end setdp macro
.393d59		c2 20		rep #$20	                REP #$20        ; set A long
.393d5b		a9 40 00	lda #$0040	                LDA #$0040  ;
.393d5e		85 28		sta $28		                STA OPL2_REG_REGION
.393d60		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393d63		e2 20		sep #$20	                SEP #$20        ; set A short
.393d65		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393d67		29 3f		and #$3f	                AND #$3F
.393d69		6b		rtl		                RTL
.393d6a						OPL2_SET_ATTACK
.393d6a		48		pha		                PHA             ; begin setdp macro
.393d6b		08		php		                PHP
.393d6c		c2 20		rep #$20	                REP #$20        ; set A long
.393d6e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393d71		5b		tcd		                TCD
.393d72		28		plp		                PLP
.393d73		68		pla		                PLA             ; end setdp macro
.393d74		c2 20		rep #$20	                REP #$20        ; set A long
.393d76		a9 60 00	lda #$0060	                LDA #$0060  ;
.393d79		85 28		sta $28		                STA OPL2_REG_REGION
.393d7b		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393d7e		e2 20		sep #$20	                SEP #$20        ; set A short
.393d80		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
.393d82		29 0f		and #$0f	                AND #$0F
.393d84		0a		asl a		                ASL
.393d85		0a		asl a		                ASL
.393d86		0a		asl a		                ASL
.393d87		0a		asl a		                ASL
.393d88		85 32		sta $32		                STA OPL2_PARAMETER0
.393d8a		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393d8c		29 0f		and #$0f	                AND #$0F
.393d8e		05 32		ora $32		                ORA OPL2_PARAMETER0
.393d90		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393d92		6b		rtl		                RTL
.393d93						OPL2_GET_ATTACK
.393d93		48		pha		                PHA             ; begin setdp macro
.393d94		08		php		                PHP
.393d95		c2 20		rep #$20	                REP #$20        ; set A long
.393d97		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393d9a		5b		tcd		                TCD
.393d9b		28		plp		                PLP
.393d9c		68		pla		                PLA             ; end setdp macro
.393d9d		c2 20		rep #$20	                REP #$20        ; set A long
.393d9f		a9 60 00	lda #$0060	                LDA #$0060
.393da2		85 28		sta $28		                STA OPL2_REG_REGION
.393da4		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393da7		e2 20		sep #$20	                SEP #$20        ; set A short
.393da9		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393dab		29 f0		and #$f0	                AND #$F0
.393dad		4a		lsr a		                LSR
.393dae		4a		lsr a		                LSR
.393daf		4a		lsr a		                LSR
.393db0		4a		lsr a		                LSR
.393db1		6b		rtl		                RTL
.393db2						OPL2_SET_DECAY
.393db2		48		pha		                PHA             ; begin setdp macro
.393db3		08		php		                PHP
.393db4		c2 20		rep #$20	                REP #$20        ; set A long
.393db6		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393db9		5b		tcd		                TCD
.393dba		28		plp		                PLP
.393dbb		68		pla		                PLA             ; end setdp macro
.393dbc		c2 20		rep #$20	                REP #$20        ; set A long
.393dbe		a9 60 00	lda #$0060	                LDA #$0060;
.393dc1		85 28		sta $28		                STA OPL2_REG_REGION
.393dc3		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393dc6		e2 20		sep #$20	                SEP #$20        ; set A short
.393dc8		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
.393dca		29 0f		and #$0f	                AND #$0F
.393dcc		85 32		sta $32		                STA OPL2_PARAMETER0
.393dce		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393dd0		29 f0		and #$f0	                AND #$F0
.393dd2		05 32		ora $32		                ORA OPL2_PARAMETER0
.393dd4		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393dd6		6b		rtl		                RTL
.393dd7						OPL2_GET_DECAY
.393dd7		48		pha		                PHA             ; begin setdp macro
.393dd8		08		php		                PHP
.393dd9		c2 20		rep #$20	                REP #$20        ; set A long
.393ddb		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393dde		5b		tcd		                TCD
.393ddf		28		plp		                PLP
.393de0		68		pla		                PLA             ; end setdp macro
.393de1		c2 20		rep #$20	                REP #$20        ; set A long
.393de3		a9 60 00	lda #$0060	                LDA #$0060
.393de6		85 28		sta $28		                STA OPL2_REG_REGION
.393de8		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393deb		e2 20		sep #$20	                SEP #$20        ; set A short
.393ded		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393def		29 0f		and #$0f	                AND #$0F
.393df1		6b		rtl		                RTL
.393df2						OPL2_SET_SUSTAIN
.393df2		48		pha		                PHA             ; begin setdp macro
.393df3		08		php		                PHP
.393df4		c2 20		rep #$20	                REP #$20        ; set A long
.393df6		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393df9		5b		tcd		                TCD
.393dfa		28		plp		                PLP
.393dfb		68		pla		                PLA             ; end setdp macro
.393dfc		c2 20		rep #$20	                REP #$20        ; set A long
.393dfe		a9 80 00	lda #$0080	                LDA #$0080;
.393e01		85 28		sta $28		                STA OPL2_REG_REGION
.393e03		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393e06		e2 20		sep #$20	                SEP #$20        ; set A short
.393e08		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
.393e0a		29 0f		and #$0f	                AND #$0F
.393e0c		0a		asl a		                ASL
.393e0d		0a		asl a		                ASL
.393e0e		0a		asl a		                ASL
.393e0f		0a		asl a		                ASL
.393e10		85 32		sta $32		                STA OPL2_PARAMETER0
.393e12		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393e14		29 0f		and #$0f	                AND #$0F
.393e16		05 32		ora $32		                ORA OPL2_PARAMETER0
.393e18		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393e1a		6b		rtl		                RTL
.393e1b						OPL2_GET_SUSTAIN
.393e1b		48		pha		                PHA             ; begin setdp macro
.393e1c		08		php		                PHP
.393e1d		c2 20		rep #$20	                REP #$20        ; set A long
.393e1f		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393e22		5b		tcd		                TCD
.393e23		28		plp		                PLP
.393e24		68		pla		                PLA             ; end setdp macro
.393e25		c2 20		rep #$20	                REP #$20        ; set A long
.393e27		a9 80 00	lda #$0080	                LDA #$0080
.393e2a		85 28		sta $28		                STA OPL2_REG_REGION
.393e2c		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393e2f		e2 20		sep #$20	                SEP #$20        ; set A short
.393e31		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393e33		29 f0		and #$f0	                AND #$F0
.393e35		4a		lsr a		                LSR
.393e36		4a		lsr a		                LSR
.393e37		4a		lsr a		                LSR
.393e38		4a		lsr a		                LSR
.393e39		6b		rtl		                RTL
.393e3a						OPL2_SET_RELEASE
.393e3a		48		pha		                PHA             ; begin setdp macro
.393e3b		08		php		                PHP
.393e3c		c2 20		rep #$20	                REP #$20        ; set A long
.393e3e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393e41		5b		tcd		                TCD
.393e42		28		plp		                PLP
.393e43		68		pla		                PLA             ; end setdp macro
.393e44		c2 20		rep #$20	                REP #$20        ; set A long
.393e46		a9 80 00	lda #$0080	                LDA #$0080;
.393e49		85 28		sta $28		                STA OPL2_REG_REGION
.393e4b		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393e4e		e2 20		sep #$20	                SEP #$20        ; set A short
.393e50		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
.393e52		29 0f		and #$0f	                AND #$0F
.393e54		85 32		sta $32		                STA OPL2_PARAMETER0
.393e56		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393e58		29 f0		and #$f0	                AND #$F0
.393e5a		05 32		ora $32		                ORA OPL2_PARAMETER0
.393e5c		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393e5e		6b		rtl		                RTL
.393e5f						OPL2_GET_RELEASE
.393e5f		48		pha		                PHA             ; begin setdp macro
.393e60		08		php		                PHP
.393e61		c2 20		rep #$20	                REP #$20        ; set A long
.393e63		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393e66		5b		tcd		                TCD
.393e67		28		plp		                PLP
.393e68		68		pla		                PLA             ; end setdp macro
.393e69		c2 20		rep #$20	                REP #$20        ; set A long
.393e6b		a9 80 00	lda #$0080	                LDA #$0080
.393e6e		85 28		sta $28		                STA OPL2_REG_REGION
.393e70		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.393e73		e2 20		sep #$20	                SEP #$20        ; set A short
.393e75		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393e77		29 0f		and #$0f	                AND #$0F
.393e79		6b		rtl		                RTL
.393e7a						OPL2_SET_FNUMBER
.393e7a		48		pha		                PHA             ; begin setdp macro
.393e7b		08		php		                PHP
.393e7c		c2 20		rep #$20	                REP #$20        ; set A long
.393e7e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393e81		5b		tcd		                TCD
.393e82		28		plp		                PLP
.393e83		68		pla		                PLA             ; end setdp macro
.393e84		e2 20		sep #$20	                SEP #$20        ; set A short
.393e86		18		clc		                CLC
.393e87		a5 27		lda $27		                LDA OPL2_CHANNEL
.393e89		29 0f		and #$0f	                AND #$0F  ; This is just precaution, it should be between 0 to 8
.393e8b		69 a0		adc #$a0	                ADC #$A0
.393e8d		85 2a		sta $2a		                STA OPL2_REG_OFFSET
.393e8f		a9 00		lda #$00	                LDA #$00
.393e91		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
.393e93		c2 30		rep #$30	                REP #$30        ; set A&X long
.393e95		18		clc		                CLC
.393e96		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
.393e99		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
.393e9b		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
.393e9d		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
.393ea0		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
.393ea2		e2 20		sep #$20	                SEP #$20        ; set A short
.393ea4		a5 32		lda $32		                LDA OPL2_PARAMETER0     ; Load the first 8 Bits Value of FNumber
.393ea6		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]  ; Load
.393ea8		18		clc		                CLC
.393ea9		a5 2c		lda $2c		                LDA OPL2_IND_ADDY_LL
.393eab		69 10		adc #$10	                ADC #$10
.393ead		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
.393eaf		a5 33		lda $33		                LDA OPL2_PARAMETER1
.393eb1		29 03		and #$03	                AND #$03
.393eb3		85 33		sta $33		                STA OPL2_PARAMETER1
.393eb5		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393eb7		29 fc		and #$fc	                AND #$FC
.393eb9		05 33		ora $33		                ORA OPL2_PARAMETER1
.393ebb		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393ebd		6b		rtl		                RTL
.393ebe						OPL2_GET_FNUMBER
.393ebe		48		pha		                PHA             ; begin setdp macro
.393ebf		08		php		                PHP
.393ec0		c2 20		rep #$20	                REP #$20        ; set A long
.393ec2		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393ec5		5b		tcd		                TCD
.393ec6		28		plp		                PLP
.393ec7		68		pla		                PLA             ; end setdp macro
.393ec8		e2 20		sep #$20	                SEP #$20        ; set A short
.393eca		18		clc		                CLC
.393ecb		a5 27		lda $27		                LDA OPL2_CHANNEL
.393ecd		29 0f		and #$0f	                AND #$0F  ; This is just precaution, it should be between 0 to 8
.393ecf		69 a0		adc #$a0	                ADC #$A0
.393ed1		85 2a		sta $2a		                STA OPL2_REG_OFFSET
.393ed3		a9 00		lda #$00	                LDA #$00
.393ed5		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
.393ed7		c2 30		rep #$30	                REP #$30        ; set A&X long
.393ed9		18		clc		                CLC
.393eda		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
.393edd		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
.393edf		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
.393ee1		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
.393ee4		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
.393ee6		e2 20		sep #$20	                SEP #$20        ; set A short
.393ee8		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393eea		85 32		sta $32		                STA OPL2_PARAMETER0
.393eec		18		clc		                CLC
.393eed		a5 2c		lda $2c		                LDA OPL2_IND_ADDY_LL
.393eef		69 10		adc #$10	                ADC #$10
.393ef1		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
.393ef3		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393ef5		29 03		and #$03	                AND #$03
.393ef7		85 33		sta $33		                STA OPL2_PARAMETER1
.393ef9		6b		rtl		                RTL
.393efa						OPL2_Set_Frequency
.393efa		6b		rtl		                RTL
.393efb						OPL2_Get_Frequency
.393efb		6b		rtl		                RTL
.393efc						OPL2_SET_BLOCK
.393efc		48		pha		                PHA             ; begin setdp macro
.393efd		08		php		                PHP
.393efe		c2 20		rep #$20	                REP #$20        ; set A long
.393f00		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393f03		5b		tcd		                TCD
.393f04		28		plp		                PLP
.393f05		68		pla		                PLA             ; end setdp macro
.393f06		e2 20		sep #$20	                SEP #$20        ; set A short
.393f08		18		clc		                CLC
.393f09		a5 27		lda $27		                LDA OPL2_CHANNEL
.393f0b		29 0f		and #$0f	                AND #$0F  ; This is just precaution, it should be between 0 to 8
.393f0d		69 b0		adc #$b0	                ADC #$B0
.393f0f		85 2a		sta $2a		                STA OPL2_REG_OFFSET
.393f11		a9 00		lda #$00	                LDA #$00
.393f13		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
.393f15		c2 30		rep #$30	                REP #$30        ; set A&X long
.393f17		18		clc		                CLC
.393f18		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
.393f1b		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
.393f1d		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
.393f1f		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
.393f22		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
.393f24		e2 20		sep #$20	                SEP #$20        ; set A short
.393f26		a5 31		lda $31		                LDA OPL2_OCTAVE
.393f28		29 07		and #$07	                AND #$07
.393f2a		0a		asl a		                ASL
.393f2b		0a		asl a		                ASL
.393f2c		85 31		sta $31		                STA OPL2_OCTAVE
.393f2e		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393f30		29 e3		and #$e3	                AND #$E3
.393f32		05 31		ora $31		                ORA OPL2_OCTAVE
.393f34		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393f36		60		rts		                RTS
.393f37						OPL2_SET_KEYON
.393f37		48		pha		                PHA             ; begin setdp macro
.393f38		08		php		                PHP
.393f39		c2 20		rep #$20	                REP #$20        ; set A long
.393f3b		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393f3e		5b		tcd		                TCD
.393f3f		28		plp		                PLP
.393f40		68		pla		                PLA             ; end setdp macro
.393f41		e2 20		sep #$20	                SEP #$20        ; set A short
.393f43		18		clc		                CLC
.393f44		a5 27		lda $27		                LDA OPL2_CHANNEL
.393f46		29 0f		and #$0f	                AND #$0F  ; This is just precaution, it should be between 0 to 8
.393f48		69 b0		adc #$b0	                ADC #$B0
.393f4a		85 2a		sta $2a		                STA OPL2_REG_OFFSET
.393f4c		a9 00		lda #$00	                LDA #$00
.393f4e		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
.393f50		c2 30		rep #$30	                REP #$30        ; set A&X long
.393f52		18		clc		                CLC
.393f53		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
.393f56		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
.393f58		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
.393f5a		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
.393f5d		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
.393f5f		e2 20		sep #$20	                SEP #$20        ; set A short
.393f61		a5 32		lda $32		                LDA OPL2_PARAMETER0
.393f63		29 01		and #$01	                AND #$01
.393f65		f0 02		beq $393f69	                BEQ SET_KEYON_OFF
.393f67		a9 20		lda #$20	                LDA #$20
.393f69						    SET_KEYON_OFF
.393f69		85 32		sta $32		                STA OPL2_PARAMETER0
.393f6b		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.393f6d		29 df		and #$df	                AND #$DF
.393f6f		05 32		ora $32		                ORA OPL2_PARAMETER0
.393f71		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.393f73		60		rts		                RTS
.393f74						OPL2_SET_FEEDBACK
.393f74		48		pha		                PHA             ; begin setdp macro
.393f75		08		php		                PHP
.393f76		c2 20		rep #$20	                REP #$20        ; set A long
.393f78		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393f7b		5b		tcd		                TCD
.393f7c		28		plp		                PLP
.393f7d		68		pla		                PLA             ; end setdp macro
.393f7e		e2 20		sep #$20	                SEP #$20        ; set A short
.393f80		18		clc		              CLC
.393f81		a5 27		lda $27		              LDA OPL2_CHANNEL
.393f83		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
.393f85		69 c0		adc #$c0	              ADC #$C0
.393f87		85 2a		sta $2a		              STA OPL2_REG_OFFSET
.393f89		a9 00		lda #$00	              LDA #$00
.393f8b		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
.393f8d		c2 30		rep #$30	                REP #$30        ; set A&X long
.393f8f		18		clc		              CLC
.393f90		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.393f93		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
.393f95		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393f97		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.393f9a		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.393f9c		e2 20		sep #$20	                SEP #$20        ; set A short
.393f9e		a5 32		lda $32		              LDA OPL2_PARAMETER0
.393fa0		29 07		and #$07	              AND #$07
.393fa2		0a		asl a		              ASL
.393fa3		85 32		sta $32		              STA OPL2_PARAMETER0
.393fa5		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393fa7		29 01		and #$01	              AND #$01
.393fa9		05 32		ora $32		              ORA OPL2_PARAMETER0
.393fab		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393fad		6b		rtl		                RTL
.393fae						OPL2_SET_SYNTHMODE
.393fae		48		pha		                PHA             ; begin setdp macro
.393faf		08		php		                PHP
.393fb0		c2 20		rep #$20	                REP #$20        ; set A long
.393fb2		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393fb5		5b		tcd		                TCD
.393fb6		28		plp		                PLP
.393fb7		68		pla		                PLA             ; end setdp macro
.393fb8		08		php		              PHP ; Push the Carry
.393fb9		e2 20		sep #$20	                SEP #$20        ; set A short
.393fbb		18		clc		              CLC
.393fbc		a5 27		lda $27		              LDA OPL2_CHANNEL
.393fbe		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
.393fc0		69 c0		adc #$c0	              ADC #$C0
.393fc2		85 2a		sta $2a		              STA OPL2_REG_OFFSET
.393fc4		a9 00		lda #$00	              LDA #$00
.393fc6		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
.393fc8		c2 30		rep #$30	                REP #$30        ; set A&X long
.393fca		18		clc		              CLC
.393fcb		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
.393fce		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
.393fd0		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393fd2		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.393fd5		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.393fd7		28		plp		              PLP ; Pull the Carry out
.393fd8		e2 20		sep #$20	                SEP #$20        ; set A short
.393fda		b0 08		bcs $393fe4	              BCS OPL2_Set_Synthmode_Set;
.393fdc		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393fde		29 fe		and #$fe	              AND #$FE
.393fe0		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393fe2		80 06		bra $393fea	              BRA OPL2_Set_Synthmode_Exit
.393fe4						OPL2_Set_Synthmode_Set
.393fe4		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.393fe6		09 01		ora #$01	              ORA #$01
.393fe8		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.393fea						OPL2_Set_Synthmode_Exit
.393fea		6b		rtl		                RTL
.393feb						OPL2_SET_DEEPTREMOLO
.393feb		48		pha		                PHA             ; begin setdp macro
.393fec		08		php		                PHP
.393fed		c2 20		rep #$20	                REP #$20        ; set A long
.393fef		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.393ff2		5b		tcd		                TCD
.393ff3		28		plp		                PLP
.393ff4		68		pla		                PLA             ; end setdp macro
.393ff5		c2 20		rep #$20	                REP #$20        ; set A long
.393ff7		a9 bd e6	lda #$e6bd	              LDA #<>OPL3_R_BASE + $00BD
.393ffa		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.393ffc		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.393fff		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.394001		e2 20		sep #$20	                SEP #$20        ; set A short
.394003		b0 08		bcs $39400d	              BCS OPL2_Set_DeepTremolo_Set;
.394005		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.394007		29 7f		and #$7f	              AND #$7F
.394009		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.39400b		80 06		bra $394013	              BRA OPL2_Set_DeepTremolo_Exit
.39400d						OPL2_Set_DeepTremolo_Set
.39400d		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.39400f		09 80		ora #$80	              ORA #$80
.394011		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.394013						OPL2_Set_DeepTremolo_Exit
.394013		6b		rtl		                RTL
.394014						OPL2_SET_DEEPVIBRATO
.394014		48		pha		                PHA             ; begin setdp macro
.394015		08		php		                PHP
.394016		c2 20		rep #$20	                REP #$20        ; set A long
.394018		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.39401b		5b		tcd		                TCD
.39401c		28		plp		                PLP
.39401d		68		pla		                PLA             ; end setdp macro
.39401e		c2 20		rep #$20	                REP #$20        ; set A long
.394020		a9 bd e6	lda #$e6bd	              LDA #<>OPL3_R_BASE + $00BD
.394023		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
.394025		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
.394028		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
.39402a		e2 20		sep #$20	                SEP #$20        ; set A short
.39402c		b0 08		bcs $394036	              BCS OPL2_Set_DeepVibrato_Set;
.39402e		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.394030		29 bf		and #$bf	              AND #$BF
.394032		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.394034		80 06		bra $39403c	              BRA OPL2_Set_DeepVibrato_Exit
.394036						OPL2_Set_DeepVibrato_Set
.394036		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
.394038		09 40		ora #$40	              ORA #$40
.39403a		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
.39403c						OPL2_Set_DeepVibrato_Exit
.39403c		6b		rtl		                RTL
.39403d						OPL2_SET_PERCUSSION
.39403d		48		pha		                PHA             ; begin setdp macro
.39403e		08		php		                PHP
.39403f		c2 20		rep #$20	                REP #$20        ; set A long
.394041		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.394044		5b		tcd		                TCD
.394045		28		plp		                PLP
.394046		68		pla		                PLA             ; end setdp macro
.394047		c2 20		rep #$20	                REP #$20        ; set A long
.394049		a9 bd e6	lda #$e6bd	                LDA #<>OPL3_R_BASE + $00BD
.39404c		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
.39404e		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
.394051		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
.394053		e2 20		sep #$20	                SEP #$20        ; set A short
.394055		b0 08		bcs $39405f	                BCS OPL2_Set_Percussion_Set;
.394057		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.394059		29 df		and #$df	                AND #$DF
.39405b		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.39405d		80 06		bra $394065	                BRA OPL2_Set_Percussion_Exit
.39405f						OPL2_Set_Percussion_Set
.39405f		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.394061		09 20		ora #$20	                ORA #$20
.394063		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.394065						OPL2_Set_Percussion_Exit
.394065		6b		rtl		                RTL
.394066						OPL2_SET_DRUMS
.394066		48		pha		                PHA             ; begin setdp macro
.394067		08		php		                PHP
.394068		c2 20		rep #$20	                REP #$20        ; set A long
.39406a		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.39406d		5b		tcd		                TCD
.39406e		28		plp		                PLP
.39406f		68		pla		                PLA             ; end setdp macro
.394070		c2 20		rep #$20	                REP #$20        ; set A long
.394072		a9 bd e6	lda #$e6bd	                LDA #<>OPL3_R_BASE + $00BD
.394075		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
.394077		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
.39407a		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
.39407c		e2 20		sep #$20	                SEP #$20        ; set A short
.39407e		a5 32		lda $32		                LDA OPL2_PARAMETER0
.394080		29 1f		and #$1f	                AND #$1F
.394082		85 32		sta $32		                STA OPL2_PARAMETER0
.394084		49 ff		eor #$ff	                EOR #$FF
.394086		85 33		sta $33		                STA OPL2_PARAMETER1
.394088		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.39408a		25 33		and $33		                AND OPL2_PARAMETER1
.39408c		05 32		ora $32		                ORA OPL2_PARAMETER0
.39408e		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.394090		6b		rtl		                RTL
.394091						OPL2_SET_WAVEFORM
.394091		48		pha		                PHA             ; begin setdp macro
.394092		08		php		                PHP
.394093		c2 20		rep #$20	                REP #$20        ; set A long
.394095		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
.394098		5b		tcd		                TCD
.394099		28		plp		                PLP
.39409a		68		pla		                PLA             ; end setdp macro
.39409b		c2 20		rep #$20	                REP #$20        ; set A long
.39409d		a9 e0 00	lda #$00e0	                LDA #$00E0;
.3940a0		85 28		sta $28		                STA OPL2_REG_REGION
.3940a2		20 b6 40	jsr $3940b6	                JSR OPL2_GET_REG_OFFSET
.3940a5		e2 20		sep #$20	                SEP #$20        ; set A short
.3940a7		a5 32		lda $32		                LDA OPL2_PARAMETER0
.3940a9		29 03		and #$03	                AND #$03
.3940ab		85 32		sta $32		                STA OPL2_PARAMETER0
.3940ad		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
.3940af		29 fc		and #$fc	                AND #$FC
.3940b1		05 32		ora $32		                ORA OPL2_PARAMETER0
.3940b3		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
.3940b5		6b		rtl		                RTL
.3940b6						OPL2_GET_REG_OFFSET
.3940b6		e2 30		sep #$30	                SEP #$30        ; set A&X short
.3940b8		a5 27		lda $27		                LDA OPL2_CHANNEL
.3940ba		29 0f		and #$0f	                AND #$0F
.3940bc		aa		tax		                TAX
.3940bd		a5 26		lda $26		                LDA OPL2_OPERATOR   ; 0 = operator 1, other = operator 2
.3940bf		d0 06		bne $3940c7	                BNE OPL2_Get_Register_Offset_l0
.3940c1		bf fe 16 39	lda $3916fe,x	                LDA @lregisterOffsets_operator0, X
.3940c5		80 04		bra $3940cb	                BRA OPL2_Get_Register_Offset_exit
.3940c7						OPL2_Get_Register_Offset_l0
.3940c7		bf 07 17 39	lda $391707,x	                LDA @lregisterOffsets_operator1, X
.3940cb						OPL2_Get_Register_Offset_exit
.3940cb		85 2a		sta $2a		                STA OPL2_REG_OFFSET
.3940cd		a9 00		lda #$00	                LDA #$00
.3940cf		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
.3940d1		c2 30		rep #$30	                REP #$30        ; set A&X long
.3940d3		18		clc		                CLC
.3940d4		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
.3940d7		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
.3940d9		65 28		adc $28		                ADC OPL2_REG_REGION ; Ex: $20, or $40, $60, $80 (in 16bits)
.3940db		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
.3940dd		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
.3940e0		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
.3940e2		60		rts		                RTS

;******  Return to file: src\kernel.asm


;******  Processing file: src\sdcard_controller_def.asm

=$afea00					SDC_VERSION_REG         = $AFEA00    ; Ought to read 12
=$afea01					SDC_CONTROL_REG         = $AFEA01    ; Bit0 1 = Reset core logic, and registers. Self clearing
=$afea02					SDC_TRANS_TYPE_REG      = $AFEA02  ; Bit[1:0]
=$00						SDC_TRANS_DIRECT      = $00   ; 00 = Direct Access
=$01						SDC_TRANS_INIT_SD     = $01   ; 01 = Init SD
=$02						SDC_TRANS_READ_BLK    = $02   ; 10 = RW_READ_BLOCK (512 Bytes)
=$03						SDC_TRANS_WRITE_BLK   = $03   ; 11 = RW_WRITE_SD_BLOCK
=$afea03					SDC_TRANS_CONTROL_REG   = $AFEA03
=$01						SDC_TRANS_START         = $01
=$afea04					SDC_TRANS_STATUS_REG    = $AFEA04
=$01						SDC_TRANS_BUSY          = $01     ;  1= Transaction Busy
=$afea05					SDC_TRANS_ERROR_REG     = $AFEA05
=$00						SDC_TRANS_INIT_NO_ERR   = $00   ; Init Error Report [1:0]
=$01						SDC_TRANS_INIT_CMD0_ERR = $01
=$02						SDC_TRANS_INIT_CMD1_ERR = $02
=$00						SDC_TRANS_RD_NO_ERR     = $00   ; Read Error Report [3:2]
=$04						SDC_TRANS_RD_CMD_ERR    = $04
=$08						SDC_TRANS_RD_TOKEN_ERR  = $08
=$00						SDC_TRANS_WR_NO_ERR     = $00   ; Write Report Error  [5:4]
=$10						SDC_TRANS_WR_CMD_ERR    = $10   ;
=$20						SDC_TRANS_WR_DATA_ERR   = $20
=$30						SDC_TRANS_WR_BUSY_ERR   = $30
=$afea06					SDC_DIRECT_ACCESS_REG   = $AFEA06 ; SPI Direct Read and Write - Set DATA before initiating direct Access Transaction
=$afea07					SDC_SD_ADDR_7_0_REG     = $AFEA07 ; Set the ADDR before a block read or block write
=$afea08					SDC_SD_ADDR_15_8_REG    = $AFEA08 ; Addr0 [8:0] Always should be 0, since each block is 512Bytes
=$afea09					SDC_SD_ADDR_23_16_REG   = $AFEA09
=$afea0a					SDC_SD_ADDR_31_24_REG   = $AFEA0A
=$afea0b					SDC_SPI_CLK_DEL_REG     = $AFEA0B
=$afea10					SDC_RX_FIFO_DATA_REG    = $AFEA10 ; Data from the Block Read
=$afea12					SDC_RX_FIFO_DATA_CNT_HI = $AFEA12 ; How many Bytes in the FIFO HI
=$afea13					SDC_RX_FIFO_DATA_CNT_LO = $AFEA13 ; How many Bytes in the FIFO LO
=$afea14					SDC_RX_FIFO_CTRL_REG    = $AFEA14 ; Bit0  Force Empty - Set to 1 to clear FIFO, self clearing (the bit)
=$afea20					SDC_TX_FIFO_DATA_REG    = $AFEA20 ; Write Data Block here
=$afea24					SDC_TX_FIFO_CTRL_REG    = $AFEA24 ; Bit0  Force Empty - Set to 1 to clear FIFO, self clearing (the bit)

;******  Return to file: src\kernel.asm


;******  Processing file: src\sdos.asm


;******  Processing file: src\sdos_fat.asm


;******  Processing file: src\sdos_bios.asm

=$80						BIOS_TIMEOUT = $80              ; Flag to indicate if a time out has occurred (see ISETTIMEOUT)
=0						BIOS_DEV_FDC = 0                ; Floppy 0
=1						BIOS_DEV_FD1 = 1                ; Future support: Floppy 1 (not likely to be attached)
=2						BIOS_DEV_SD = 2                 ; SD card, partition 0
=3						BIOS_DEV_SD1 = 3                ; Future support: SD card, partition 1
=4						BIOS_DEV_SD2 = 4                ; Future support: SD card, partition 2
=5						BIOS_DEV_SD3 = 5                ; Future support: SD card, partition 3
=6						BIOS_DEV_HD0 = 6                ; Future support: IDE Drive 0, partition 0
=7						BIOS_DEV_HD1 = 7                ; Future support: IDE Drive 0, partition 1
=8						BIOS_DEV_HD2 = 8                ; Future support: IDE Drive 0, partition 2
=9						BIOS_DEV_HD3 = 9                ; Future support: IDE Drive 0, partition 3
=$80						BIOS_ERR_BADDEV = $80           ; BIOS bad device # error
=$81						BIOS_ERR_MOUNT = $81            ; BIOS failed to mount the device
=$82						BIOS_ERR_READ = $82             ; BIOS failed to read from a device
=$83						BIOS_ERR_WRITE = $83            ; BIOS failed to write to a device
=$84						BIOS_ERR_TRACK = $84            ; BIOS failed to seek to the correct track
=$85						BIOS_ERR_CMD = $85              ; A general block device command error
=$86						BIOS_ERR_WRITEPROT = $86        ; The media was write-protected
=$87						BIOS_ERR_NOMEDIA = $87          ; No media detected... unable to read/write in time
=$88						BIOS_ERR_RESULT = $88           ; Couldn't get the result bytes for some reason
=$89						BIOS_ERR_OOS = $89              ; FDC state is somehow out of sync with the driver.
=$8a						BIOS_ERR_NOTATA = $8A           ; IDE drive is not ATA
=$8b						BIOS_ERR_NOTINIT = $8B          ; Could not initilize the device
=$8c						BIOS_ERR_TIMEOUT = $8C          ; Timeout error
.3940e3						ITRACE
.3940e3		08		php		                PHP
.3940e4		c2 30		rep #$30	                REP #$30        ; set A&X long
.3940e6		8b		phb		                PHB                 ; Print the text
.3940e7		a3 06		lda $06,s	                LDA #6,S            ; Get bits[15..0] of string pointer
.3940e9		aa		tax		                TAX                 ; ... into X
.3940ea		e2 20		sep #$20	                SEP #$20        ; set A short
.3940ec		a3 08		lda $08,s	                LDA #8,S            ; Get bits[23..16] of string pointer
.3940ee		48		pha		                PHA
.3940ef		ab		plb		                PLB                 ; ... into B
.3940f0		22 87 07 39	jsl $390787	                JSL IPUTS           ; Print the string
.3940f4		c2 20		rep #$20	                REP #$20        ; set A long
.3940f6		a3 04		lda $04,s	                LDA #4,S            ; Move P and return address down over the string pointer
.3940f8		83 08		sta $08,s	                STA #8,S
.3940fa		a3 02		lda $02,s	                LDA #2,S
.3940fc		83 06		sta $06,s	                STA #6,S
.3940fe		ab		plb		                PLB
.3940ff		68		pla		                PLA                 ; Clean up the stack
.394100		68		pla		                PLA
.394101		28		plp		                PLP
.394102		6b		rtl		                RTL
.394103						ISETTIMEOUT
.394103		8b		phb		                PHB
.394104		0b		phd		                PHD
.394105		08		php		                PHP
.394106		48		pha		                PHA             ; begin setdbr macro
.394107		08		php		                PHP
.394108		e2 20		sep #$20	                SEP #$20        ; set A short
.39410a		a9 00		lda #$00	                LDA #0
.39410c		48		pha		                PHA
.39410d		ab		plb		                PLB
.39410e		28		plp		                PLP
.39410f		68		pla		                PLA             ; end setdbr macro
.394110		48		pha		                PHA             ; begin setdp macro
.394111		08		php		                PHP
.394112		c2 20		rep #$20	                REP #$20        ; set A long
.394114		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394117		5b		tcd		                TCD
.394118		28		plp		                PLP
.394119		68		pla		                PLA             ; end setdp macro
.39411a		78		sei		                SEI                             ; We don't want to be interrupted
.39411b		e2 20		sep #$20	                SEP #$20        ; set A short
.39411d		85 0d		sta $032d	                STA @b BIOS_TIMER               ; Set the number of ticks to wait
.39411f		a5 0c		lda $032c	                LDA @b BIOS_FLAGS               ; Clear the BIOS_TIMEOUT flag
.394121		29 7f		and #$7f	                AND #~BIOS_TIMEOUT
.394123		85 0c		sta $032c	                STA @b BIOS_FLAGS
.394125		28		plp		done            PLP
.394126		2b		pld		                PLD
.394127		ab		plb		                PLB
.394128		6b		rtl		                RTL
.394129						ICMDBLOCK
.394129		0b		phd		                PHD
.39412a		08		php		                PHP
.39412b		48		pha		                PHA             ; begin setdp macro
.39412c		08		php		                PHP
.39412d		c2 20		rep #$20	                REP #$20        ; set A long
.39412f		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394132		5b		tcd		                TCD
.394133		28		plp		                PLP
.394134		68		pla		                PLA             ; end setdp macro
.394135		e2 20		sep #$20	                SEP #$20        ; set A short
.394137		a5 01		lda $0321	                LDA BIOS_DEV                ; Get the device number
.394139		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC           ; Check to see if we're sending to the floppy
.39413b		d0 06		bne $394143	                BNE ret_success             ; No: just return
.39413d		22 d6 68 39	jsl $3968d6	                JSL FDC_CMDBLOCK            ; Yes: call upon the floppy code
.394141		90 0c		bcc $39414f	                BCC pass_failure
.394143						ret_success
.394143		e2 20		sep #$20	                SEP #$20        ; set A short
.394145		64 00		stz $0320	                STZ BIOS_STATUS
.394147		28		plp		                PLP
.394148		2b		pld		                PLD
.394149		38		sec		                SEC
.39414a		6b		rtl		                RTL
.39414b						ret_failure
.39414b		e2 20		sep #$20	                SEP #$20        ; set A short
.39414d		85 00		sta $0320	                STA BIOS_STATUS
.39414f		28		plp		pass_failure    PLP
.394150		2b		pld		                PLD
.394151		18		clc		                CLC
.394152		6b		rtl		                RTL
.394153						IGETBLOCK
.394153		5a		phy		                PHY
.394154		0b		phd		                PHD
.394155		8b		phb		                PHB
.394156		08		php		                PHP
.394157		48		pha		                PHA             ; begin setdbr macro
.394158		08		php		                PHP
.394159		e2 20		sep #$20	                SEP #$20        ; set A short
.39415b		a9 00		lda #$00	                LDA #0
.39415d		48		pha		                PHA
.39415e		ab		plb		                PLB
.39415f		28		plp		                PLP
.394160		68		pla		                PLA             ; end setdbr macro
.394161		48		pha		                PHA             ; begin setdp macro
.394162		08		php		                PHP
.394163		c2 20		rep #$20	                REP #$20        ; set A long
.394165		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394168		5b		tcd		                TCD
.394169		28		plp		                PLP
.39416a		68		pla		                PLA             ; end setdp macro
.39416b		e2 20		sep #$20	                SEP #$20        ; set A short
.39416d		a0 00 00	ldy #$0000	                LDY #0
.394170		a9 5a		lda #$5a	                LDA #$5A                            ; Fill the buffer with a pattern we can recognize
.394172		97 06		sta [$0326],y	clr_loop        STA [BIOS_BUFF_PTR],Y               ; To make errors loading obvious
.394174		c8		iny		                INY
.394175		c0 00 02	cpy #$0200	                CPY #512
.394178		d0 f8		bne $394172	                BNE clr_loop
.39417a		a5 01		lda $0321	                LDA BIOS_DEV                        ; Check the device number
.39417c		c9 02		cmp #$02	                CMP #BIOS_DEV_SD                    ; Is it for the SDC?
.39417e		f0 14		beq $394194	                BEQ sd_getblock                     ; Yes: go to the SDC GETBLOCK routine
.394180		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC                   ; Is it for the floppy drive?
.394182		f0 18		beq $39419c	                BEQ fd_getblock                     ; Yes: go to the FDC GETBLOCK routine
.394184		c9 06		cmp #$06	                CMP #BIOS_DEV_HD0                   ; Is it for the IDE drive?
.394186		f0 1c		beq $3941a4	                BEQ hd_getblock
.394188		a9 80		lda #$80	                LDA #BIOS_ERR_BADDEV                ; Otherwise: return a bad device error
.39418a						ret_failure
.39418a		e2 20		sep #$20	                SEP #$20        ; set A short
.39418c		85 00		sta $0320	                STA BIOS_STATUS                     ; Set BIOS STATUS
.39418e		28		plp		                PLP
.39418f		ab		plb		                PLB
.394190		2b		pld		                PLD
.394191		7a		ply		                PLY
.394192		38		sec		                SEC                                 ; Return failure
.394193		6b		rtl		                RTL
.394194		22 f8 5d 39	jsl $395df8	sd_getblock     JSL SDC_GETBLOCK                    ; Call the SDC GETBLOCK routine
.394198		b0 12		bcs $3941ac	                BCS ret_success
.39419a		80 ee		bra $39418a	                BRA ret_failure
.39419c		22 db 66 39	jsl $3966db	fd_getblock     JSL FDC_GETBLOCK                    ; Call the FDC GETBLOCK routine
.3941a0		b0 0a		bcs $3941ac	                BCS ret_success
.3941a2		80 e6		bra $39418a	                BRA ret_failure
.3941a4		22 e9 6c 39	jsl $396ce9	hd_getblock     JSL IDE_GETBLOCK                    ; Call the IDE GETBLOCK routine
.3941a8		b0 02		bcs $3941ac	                BCS ret_success
.3941aa		80 de		bra $39418a	                BRA ret_failure
.3941ac						ret_success
.3941ac		e2 20		sep #$20	                SEP #$20        ; set A short
.3941ae		64 00		stz $0320	                STZ BIOS_STATUS                     ; Set BIOS STATUS to OK
.3941b0		28		plp		                PLP
.3941b1		ab		plb		                PLB
.3941b2		2b		pld		                PLD
.3941b3		7a		ply		                PLY
.3941b4		38		sec		                SEC                                 ; Return success
.3941b5		6b		rtl		                RTL
.3941b6						IPUTBLOCK
.3941b6		0b		phd		                PHD
.3941b7		8b		phb		                PHB
.3941b8		08		php		                PHP
.3941b9		48		pha		                PHA             ; begin setdbr macro
.3941ba		08		php		                PHP
.3941bb		e2 20		sep #$20	                SEP #$20        ; set A short
.3941bd		a9 00		lda #$00	                LDA #0
.3941bf		48		pha		                PHA
.3941c0		ab		plb		                PLB
.3941c1		28		plp		                PLP
.3941c2		68		pla		                PLA             ; end setdbr macro
.3941c3		48		pha		                PHA             ; begin setdp macro
.3941c4		08		php		                PHP
.3941c5		c2 20		rep #$20	                REP #$20        ; set A long
.3941c7		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3941ca		5b		tcd		                TCD
.3941cb		28		plp		                PLP
.3941cc		68		pla		                PLA             ; end setdp macro
.3941cd		e2 20		sep #$20	                SEP #$20        ; set A short
.3941cf		a5 01		lda $0321	                LDA BIOS_DEV                        ; Check the device number
.3941d1		c9 02		cmp #$02	                CMP #BIOS_DEV_SD                    ; Is it for the SDC?
.3941d3		f0 13		beq $3941e8	                BEQ sd_putblock                     ; Yes: go to the SDC PUTBLOCK routine
.3941d5		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC                   ; Is it for the FDC?
.3941d7		f0 17		beq $3941f0	                BEQ fd_putblock                     ; Yes: go to the FDC PUTBLOCK routine
.3941d9		c9 06		cmp #$06	                CMP #BIOS_DEV_HD0                   ; Is it for the IDE drive?
.3941db		f0 1b		beq $3941f8	                BEQ hd_putblock
.3941dd		a9 80		lda #$80	                LDA #BIOS_ERR_BADDEV                ; Otherwise: return a bad device error
.3941df						ret_failure
.3941df		e2 20		sep #$20	                SEP #$20        ; set A short
.3941e1		85 00		sta $0320	                STA BIOS_STATUS                     ; Set BIOS STATUS
.3941e3		28		plp		                PLP
.3941e4		ab		plb		                PLB
.3941e5		2b		pld		                PLD
.3941e6		18		clc		                CLC                                 ; Return failure
.3941e7		6b		rtl		                RTL
.3941e8		22 98 5e 39	jsl $395e98	sd_putblock     JSL SDC_PUTBLOCK                    ; Call the SDC PUTBLOCK routine
.3941ec		90 f1		bcc $3941df	                BCC ret_failure
.3941ee		80 10		bra $394200	                BRA ret_success
.3941f0		22 40 67 39	jsl $396740	fd_putblock     JSL FDC_PUTBLOCK                    ; Call the FDC PUTBLOCK routine
.3941f4		90 e9		bcc $3941df	                BCC ret_failure
.3941f6		80 08		bra $394200	                BRA ret_success
.3941f8		22 7a 6d 39	jsl $396d7a	hd_putblock     JSL IDE_PUTBLOCK                    ; Call the IDE PUTBLOCK routine
.3941fc		90 e1		bcc $3941df	                BCC ret_failure
.3941fe		80 00		bra $394200	                BRA ret_success
.394200						ret_success
.394200		e2 20		sep #$20	                SEP #$20        ; set A short
.394202		64 00		stz $0320	                STZ BIOS_STATUS                     ; Set BIOS STATUS to OK
.394204		28		plp		                PLP
.394205		ab		plb		                PLB
.394206		2b		pld		                PLD
.394207		38		sec		                SEC                                 ; Return success
.394208		6b		rtl		                RTL

;******  Return to file: src\sdos_fat.asm


;******  Processing file: src\sdos_dir.asm

.394209						DOS_DIROPEN
.394209		da		phx		                PHX
.39420a		5a		phy		                PHY
.39420b		0b		phd		                PHD
.39420c		8b		phb		                PHB
.39420d		08		php		                PHP
.39420e		48		pha		                PHA             ; begin setdbr macro
.39420f		08		php		                PHP
.394210		e2 20		sep #$20	                SEP #$20        ; set A short
.394212		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.394214		48		pha		                PHA
.394215		ab		plb		                PLB
.394216		28		plp		                PLP
.394217		68		pla		                PLA             ; end setdbr macro
.394218		48		pha		                PHA             ; begin setdp macro
.394219		08		php		                PHP
.39421a		c2 20		rep #$20	                REP #$20        ; set A long
.39421c		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39421f		5b		tcd		                TCD
.394220		28		plp		                PLP
.394221		68		pla		                PLA             ; end setdp macro
.394222		ad 20 a0	lda $38a020	                LDA ROOT_DIR_FIRST_CLUSTER  ; Set the cluster (or sector for FAT12)
.394225		8d 32 a0	sta $38a032	                STA DOS_DIR_BLOCK_ID        ; to that of the root directory's start
.394228		ad 22 a0	lda $38a022	                LDA ROOT_DIR_FIRST_CLUSTER+2
.39422b		8d 34 a0	sta $38a034	                STA DOS_DIR_BLOCK_ID+2
.39422e		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Point to the directory cluster buffer for loading
.394231		85 1c		sta $033c	                STA DOS_BUFF_PTR
.394233		85 18		sta $0338	                STA DOS_DIR_PTR
.394235		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
.394238		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
.39423a		85 1a		sta $033a	                STA DOS_DIR_PTR+2
.39423c		e2 20		sep #$20	                SEP #$20        ; set A short
.39423e		ad 01 a0	lda $38a001	                LDA FILE_SYSTEM             ; Check the file system
.394241		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12        ; Is it FAT12?
.394243		d0 24		bne $394269	                BNE fetch_fat32             ; No: handle processing the diretory as FAT32
.394245						fetch_fat12
.394245		e2 20		sep #$20	                SEP #$20        ; set A short
.394247		a9 00		lda #$00	                LDA #DOS_DIR_TYPE_FAT12ROOT ; Set the directory type to FAT12 root directory
.394249		8d 45 a0	sta $38a045	                STA DOS_DIR_TYPE
.39424c		c2 20		rep #$20	                REP #$20        ; set A long
.39424e		a5 18		lda $0338	                LDA DOS_DIR_PTR             ; Set the BIOS buffer pointer
.394250		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394252		a5 1a		lda $033a	                LDA DOS_DIR_PTR+2
.394254		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.394256		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Set the LBA of the sector
.394259		85 02		sta $0322	                STA BIOS_LBA
.39425b		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
.39425e		85 04		sta $0324	                STA BIOS_LBA+2
.394260		22 44 10 00	jsl $001044	                JSL GETBLOCK                ; Get the sector from the FAT12 device
.394264		b0 1f		bcs $394285	                BCS do_success              ; If sucessful, set the directory cursor
.394266		82 15 17	brl $39597e	                BRL IF_PASSFAILURE          ; Otherwise: pass up the failure
.394269						fetch_fat32
.394269		e2 20		sep #$20	                SEP #$20        ; set A short
.39426b		a9 01		lda #$01	                LDA #DOS_DIR_TYPE_FILE      ; Set the directory type to file type (all FAT32, any FAT12 subdirectory)
.39426d		8d 45 a0	sta $38a045	                STA DOS_DIR_TYPE
.394270		c2 20		rep #$20	                REP #$20        ; set A long
.394272		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID
.394275		85 10		sta $0330	                STA DOS_CLUS_ID
.394277		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
.39427a		85 12		sta $0332	                STA DOS_CLUS_ID+2
.39427c		22 ec 47 39	jsl $3947ec	                JSL DOS_GETCLUSTER          ; Try to read the first cluster
.394280		b0 03		bcs $394285	                BCS do_success              ; If successful: set the directory cursor
.394282		82 f9 16	brl $39597e	                BRL IF_PASSFAILURE          ; Otherwise: pass up the failure
.394285		82 fd 16	brl $395985	do_success      BRL IF_SUCCESS
.394288						DOS_DIRFIRST
.394288		0b		phd		                PHD
.394289		08		php		                PHP
.39428a		48		pha		                PHA             ; begin setdp macro
.39428b		08		php		                PHP
.39428c		c2 20		rep #$20	                REP #$20        ; set A long
.39428e		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394291		5b		tcd		                TCD
.394292		28		plp		                PLP
.394293		68		pla		                PLA             ; end setdp macro
.394294		c2 20		rep #$20	                REP #$20        ; set A long
.394296		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER
.394299		85 18		sta $0338	                STA DOS_DIR_PTR
.39429b		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
.39429e		85 1a		sta $033a	                STA DOS_DIR_PTR+2
.3942a0		28		plp		                PLP
.3942a1		2b		pld		                PLD
.3942a2		6b		rtl		                RTL
.3942a3						DOS_DIRNEXT
.3942a3		da		phx		                PHX
.3942a4		5a		phy		                PHY
.3942a5		0b		phd		                PHD
.3942a6		8b		phb		                PHB
.3942a7		08		php		                PHP
.3942a8		48		pha		                PHA             ; begin setdbr macro
.3942a9		08		php		                PHP
.3942aa		e2 20		sep #$20	                SEP #$20        ; set A short
.3942ac		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.3942ae		48		pha		                PHA
.3942af		ab		plb		                PLB
.3942b0		28		plp		                PLP
.3942b1		68		pla		                PLA             ; end setdbr macro
.3942b2		48		pha		                PHA             ; begin setdp macro
.3942b3		08		php		                PHP
.3942b4		c2 20		rep #$20	                REP #$20        ; set A long
.3942b6		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3942b9		5b		tcd		                TCD
.3942ba		28		plp		                PLP
.3942bb		68		pla		                PLA             ; end setdp macro
.3942bc		c2 20		rep #$20	                REP #$20        ; set A long
.3942be		18		clc		                CLC                         ; Advance the directory entry pointer to the next entry
.3942bf		a5 18		lda $0338	                LDA DOS_DIR_PTR
.3942c1		69 20 00	adc #$0020	                ADC #DOS_DIR_ENTRY_SIZE
.3942c4		85 18		sta $0338	                STA DOS_DIR_PTR
.3942c6		a5 1a		lda $033a	                LDA DOS_DIR_PTR+2
.3942c8		69 00 00	adc #$0000	                ADC #0
.3942cb		85 1a		sta $033a	                STA DOS_DIR_PTR+2
.3942cd		38		sec		                SEC                         ; Check to see if we've reached the end of the sector buffer
.3942ce		a9 00 a3	lda #$a300	                LDA #<>DOS_DIR_CLUSTER_END
.3942d1		e5 18		sbc $0338	                SBC DOS_DIR_PTR
.3942d3		85 28		sta $0348	                STA DOS_TEMP
.3942d5		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER_END
.3942d8		e5 1a		sbc $033a	                SBC DOS_DIR_PTR+2
.3942da		85 2a		sta $034a	                STA DOS_TEMP+2
.3942dc		30 0c		bmi $3942ea	                BMI get_next_block          ; Yes: try to fetch the next directory entry
.3942de		f0 03		beq $3942e3	                BEQ check_lower
.3942e0		82 a2 16	brl $395985	                BRL IF_SUCCESS
.3942e3		a5 28		lda $0348	check_lower     LDA DOS_TEMP
.3942e5		f0 03		beq $3942ea	                BEQ get_next_block
.3942e7		82 9b 16	brl $395985	                BRL IF_SUCCESS
.3942ea						get_next_block
.3942ea		e2 20		sep #$20	                SEP #$20        ; set A short
.3942ec		ad 45 a0	lda $38a045	                LDA DOS_DIR_TYPE            ; Check the type of the directory
.3942ef		c9 01		cmp #$01	                CMP #DOS_DIR_TYPE_FILE
.3942f1		f0 38		beq $39432b	                BEQ next_cluster            ; FILE TYPE: it's cluster based (FAT32, or FAT12 non-root)
.3942f3						next_sector
.3942f3		c2 20		rep #$20	                REP #$20        ; set A long
.3942f5		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID
.3942f8		1a		inc a		                INC A
.3942f9		8d 32 a0	sta $38a032	                STA DOS_DIR_BLOCK_ID        ; Increment the sector number (FAT12 root directory is sector based)
.3942fc		c9 0a 00	cmp #$000a	                CMP #10                     ; See if we're at the end (TODO: calculate this)
.3942ff		d0 07		bne $394308	                BNE read_sector
.394301		e2 20		sep #$20	                SEP #$20        ; set A short
.394303		a9 00		lda #$00	                LDA #0
.394305		82 72 16	brl $39597a	                BRL IF_FAILURE
.394308						read_sector
.394308		c2 20		rep #$20	                REP #$20        ; set A long
.39430a		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Set the LBA to the sector #
.39430d		85 02		sta $0322	                STA BIOS_LBA
.39430f		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
.394312		85 04		sta $0324	                STA BIOS_LBA+2
.394314		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Set the pointers to the buffer
.394317		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394319		85 18		sta $0338	                STA DOS_DIR_PTR
.39431b		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
.39431e		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.394320		85 1a		sta $033a	                STA DOS_DIR_PTR+2
.394322		22 44 10 00	jsl $001044	                JSL GETBLOCK                ; Attempt to read the sector from the FAT12 device
.394326		b0 39		bcs $394361	                BCS do_success              ; If successful: set the directory cursor
.394328		82 53 16	brl $39597e	                BRL IF_PASSFAILURE          ; Otherwise: pass up the failure
.39432b						next_cluster
.39432b		c2 20		rep #$20	                REP #$20        ; set A long
.39432d		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Get the current block (cluster) ID
.394330		85 10		sta $0330	                STA DOS_CLUS_ID
.394332		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
.394335		85 12		sta $0332	                STA DOS_CLUS_ID+2
.394337		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER
.39433a		85 1c		sta $033c	                STA DOS_BUFF_PTR
.39433c		85 18		sta $0338	                STA DOS_DIR_PTR
.39433e		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
.394341		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
.394343		85 1a		sta $033a	                STA DOS_DIR_PTR+2
.394345		22 fc 4b 39	jsl $394bfc	                JSL NEXTCLUSTER             ; Try to find the next cluster
.394349		b0 03		bcs $39434e	                BCS set_next
.39434b		82 30 16	brl $39597e	                BRL IF_PASSFAILURE          ; If error: pass it up the chain
.39434e		a5 10		lda $0330	set_next        LDA DOS_CLUS_ID             ; Save the cluster as the current directory cluster
.394350		8d 32 a0	sta $38a032	                STA DOS_DIR_BLOCK_ID
.394353		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.394355		8d 34 a0	sta $38a034	                STA DOS_DIR_BLOCK_ID+2
.394358		22 ec 47 39	jsl $3947ec	                JSL DOS_GETCLUSTER          ; Try to read the first cluster
.39435c		b0 03		bcs $394361	                BCS do_success              ; If successful: set the directory cursor
.39435e		82 1d 16	brl $39597e	                BRL IF_PASSFAILURE          ; Otherwise: pass up the failure
.394361		82 21 16	brl $395985	do_success      BRL IF_SUCCESS
.394364						DOS_DIRFINDFREE
.394364		da		phx		                PHX
.394365		5a		phy		                PHY
.394366		0b		phd		                PHD
.394367		8b		phb		                PHB
.394368		08		php		                PHP
.394369		48		pha		                PHA             ; begin setdbr macro
.39436a		08		php		                PHP
.39436b		e2 20		sep #$20	                SEP #$20        ; set A short
.39436d		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.39436f		48		pha		                PHA
.394370		ab		plb		                PLB
.394371		28		plp		                PLP
.394372		68		pla		                PLA             ; end setdbr macro
.394373		48		pha		                PHA             ; begin setdp macro
.394374		08		php		                PHP
.394375		c2 20		rep #$20	                REP #$20        ; set A long
.394377		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39437a		5b		tcd		                TCD
.39437b		28		plp		                PLP
.39437c		68		pla		                PLA             ; end setdp macro
.39437d		22 07 56 39	jsl $395607	                JSL IF_DIROPEN
.394381		b0 06		bcs $394389	                BCS start_walk
.394383		a9 08 00	lda #$0008	                LDA #DOS_ERR_NODIR          ; Return that we could not read the directory
.394386		82 28 00	brl $3943b1	                BRL ret_failure
.394389		a0 00 00	ldy #$0000	start_walk      LDY #0                      ; We check the first character of the entry
.39438c						chk_entry
.39438c		e2 20		sep #$20	                SEP #$20        ; set A short
.39438e		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y         ; Get the first byte of the directory entry
.394390		f0 1c		beq $3943ae	                BEQ ret_success             ; If 0: we have a blank... return it
.394392		c9 e5		cmp #$e5	                CMP #DOS_DIR_ENT_UNUSED     ; Is it an unused (deleted) entry?
.394394		f0 18		beq $3943ae	                BEQ ret_success             ; Yes: return it
.394396		22 41 56 39	jsl $395641	                JSL IF_DIRNEXT              ; Go to the next directory entry
.39439a		b0 ed		bcs $394389	                BCS start_walk              ; If we got one, start walking it
.39439c		22 b4 43 39	jsl $3943b4	                JSL DOS_DIRAPPEND           ; If there isn't one, create a blank cluster
.3943a0		90 0f		bcc $3943b1	                BCC ret_failure             ; If that didn't work, return the failure
.3943a2		c2 20		rep #$20	                REP #$20        ; set A long
.3943a4		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Return the first entry
.3943a7		85 18		sta $0338	                STA DOS_DIR_PTR
.3943a9		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
.3943ac		85 1a		sta $033a	                STA DOS_DIR_PTR+2
.3943ae		82 d4 15	brl $395985	ret_success     BRL IF_SUCCESS
.3943b1		82 c6 15	brl $39597a	ret_failure     BRL IF_FAILURE
.3943b4						DOS_DIRAPPEND
.3943b4		da		phx		                PHX
.3943b5		8b		phb		                PHB
.3943b6		0b		phd		                PHD
.3943b7		08		php		                PHP
.3943b8		48		pha		                PHA             ; begin setdbr macro
.3943b9		08		php		                PHP
.3943ba		e2 20		sep #$20	                SEP #$20        ; set A short
.3943bc		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.3943be		48		pha		                PHA
.3943bf		ab		plb		                PLB
.3943c0		28		plp		                PLP
.3943c1		68		pla		                PLA             ; end setdbr macro
.3943c2		48		pha		                PHA             ; begin setdp macro
.3943c3		08		php		                PHP
.3943c4		c2 20		rep #$20	                REP #$20        ; set A long
.3943c6		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3943c9		5b		tcd		                TCD
.3943ca		28		plp		                PLP
.3943cb		68		pla		                PLA             ; end setdp macro
.3943cc		e2 20		sep #$20	                SEP #$20        ; set A short
.3943ce		ad 45 a0	lda $38a045	                LDA DOS_DIR_TYPE
.3943d1		c9 01		cmp #$01	                CMP #DOS_DIR_TYPE_FILE          ; Are we looking at a file type directory
.3943d3		f0 09		beq $3943de	                BEQ clr_sector                  ; Yes: clear out the directory data
.3943d5						ret_failure
.3943d5		e2 20		sep #$20	                SEP #$20        ; set A short
.3943d7		a9 15		lda #$15	                LDA #DOS_ERR_DIRFULL            ; No: return a directory-full error
.3943d9		85 0e		sta $032e	                STA DOS_STATUS
.3943db		82 3e 00	brl $39441c	                BRL pass_failure
.3943de						clr_sector
.3943de		c2 20		rep #$20	                REP #$20        ; set A long
.3943e0		a9 00 00	lda #$0000	                LDA #0
.3943e3		a2 00 00	ldx #$0000	                LDX #0
.3943e6		9d 00 a1	sta $38a100,x	clr_loop        STA DOS_DIR_CLUSTER,X           ; Clear the directory cluster
.3943e9		e8		inx		                INX
.3943ea		e8		inx		                INX
.3943eb		e0 00 02	cpx #$0200	                CPX #512
.3943ee		d0 f6		bne $3943e6	                BNE clr_loop
.3943f0		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER          ; Point to the new, blank directory data
.3943f3		85 1c		sta $033c	                STA DOS_BUFF_PTR
.3943f5		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
.3943f8		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
.3943fa		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID            ; We want to append it to the current directory
.3943fd		85 10		sta $0330	                STA DOS_CLUS_ID
.3943ff		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
.394402		85 12		sta $0332	                STA DOS_CLUS_ID+2
.394404		22 1d 50 39	jsl $39501d	                JSL DOS_APPENDCLUS              ; Attempt to append the blank data as a new cluster
.394408		90 12		bcc $39441c	                BCC pass_failure                ; If there was an error, pass it up the chain
.39440a		ad 36 a0	lda $38a036	                LDA DOS_NEW_CLUSTER             ; Set the block ID of the new directory cluster
.39440d		8d 32 a0	sta $38a032	                STA DOS_DIR_BLOCK_ID
.394410		ad 38 a0	lda $38a038	                LDA DOS_NEW_CLUSTER+2
.394413		8d 34 a0	sta $38a034	                STA DOS_DIR_BLOCK_ID+2
.394416		28		plp		ret_success     PLP
.394417		2b		pld		                PLD
.394418		ab		plb		                PLB
.394419		fa		plx		                PLX
.39441a		38		sec		                SEC
.39441b		6b		rtl		                RTL
.39441c		28		plp		pass_failure    PLP
.39441d		2b		pld		                PLD
.39441e		ab		plb		                PLB
.39441f		fa		plx		                PLX
.394420		18		clc		                CLC
.394421		6b		rtl		                RTL
.394422						DOS_DIRWRITE
.394422		da		phx		                PHX
.394423		5a		phy		                PHY
.394424		0b		phd		                PHD
.394425		8b		phb		                PHB
.394426		08		php		                PHP
.394427		48		pha		                PHA             ; begin setdbr macro
.394428		08		php		                PHP
.394429		e2 20		sep #$20	                SEP #$20        ; set A short
.39442b		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.39442d		48		pha		                PHA
.39442e		ab		plb		                PLB
.39442f		28		plp		                PLP
.394430		68		pla		                PLA             ; end setdbr macro
.394431		48		pha		                PHA             ; begin setdp macro
.394432		08		php		                PHP
.394433		c2 20		rep #$20	                REP #$20        ; set A long
.394435		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394438		5b		tcd		                TCD
.394439		28		plp		                PLP
.39443a		68		pla		                PLA             ; end setdp macro
.39443b		e2 20		sep #$20	                SEP #$20        ; set A short
.39443d		ad 45 a0	lda $38a045	                LDA DOS_DIR_TYPE            ; Check the type of the directory
.394440		c9 01		cmp #$01	                CMP #DOS_DIR_TYPE_FILE      ; Is it a file type directory (FAT32 or FAT12 non-root?)
.394442		f0 1f		beq $394463	                BEQ write_cluster           ; Yes: write it back using a cluster ID
.394444						write_sector
.394444		c2 20		rep #$20	                REP #$20        ; set A long
.394446		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Set the BIOS_LBA to the LBA of the sector
.394449		85 02		sta $0322	                STA BIOS_LBA
.39444b		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
.39444e		85 04		sta $0324	                STA BIOS_LBA+2
.394450		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Set the pointer to the directory buffer
.394453		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394455		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
.394458		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.39445a		22 24 10 00	jsl $001024	                JSL PUTBLOCK                ; Try to write the sector to disk
.39445e		b0 1f		bcs $39447f	                BCS ret_success
.394460		82 17 15	brl $39597a	ret_failure     BRL IF_FAILURE
.394463						write_cluster
.394463		c2 20		rep #$20	                REP #$20        ; set A long
.394465		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Set the DOS_CLUS_ID to the ID of the cluster
.394468		85 10		sta $0330	                STA DOS_CLUS_ID
.39446a		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
.39446d		85 12		sta $0332	                STA DOS_CLUS_ID+2
.39446f		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Set the pointer to the directory buffer
.394472		85 1c		sta $033c	                STA DOS_BUFF_PTR
.394474		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
.394477		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
.394479		22 29 48 39	jsl $394829	                JSL DOS_PUTCLUSTER          ; Try to write the cluster to disk
.39447d		90 e1		bcc $394460	                BCC ret_failure
.39447f		82 03 15	brl $395985	ret_success     BRL IF_SUCCESS

;******  Return to file: src\sdos_fat.asm

.0000						DEVICE_DESC
>0000						DEVNAME         .dword ?            ; A pointer to the ASCIIZ name of the device
>0004						DEVNUMBER       .byte ?           ; The BIOS_DEV number for the device
>0005						NEXT            .dword ?            ; A pointer to the next device descriptor
.0000						DIRENTRY
>0000						SHORTNAME               .fill 11        ; $00 - The short name of the file (8 name, 3 extension)
>000b						ATTRIBUTE               .byte ?         ; $0B - The attribute bits
>000c						IGNORED1                .word ?         ; $0C - Unused (by us) bytes
>000e						CREATE_TIME             .word ?         ; $0E - Creation time
>0010						CREATE_DATE             .word ?         ; $10 - Creation date
>0012						ACCESS_DATE             .word ?         ; $12 - Last access date
>0014						CLUSTER_H               .word ?         ; $14 - High word of the first cluster #
>0016						MODIFIED_TIME           .word ?         ; $16 - Last modified time
>0018						MODIFIED_DATE           .word ?         ; $18 - Last modified date
>001a						CLUSTER_L               .word ?         ; $1A - Low word of the first cluster #
>001c						SIZE                    .dword ?        ; $1C - The size of the file (in bytes)
=$01						DOS_ATTR_RO = $01                       ; File is read-only
=$02						DOS_ATTR_HIDDEN = $02                   ; File is hidden
=$04						DOS_ATTR_SYSTEM = $04                   ; File is a system file
=$08						DOS_ATTR_VOLUME = $08                   ; Entry is the volume label
=$10						DOS_ATTR_DIR = $10                      ; Entry is a directory
=$20						DOS_ATTR_ARCH = $20                     ; Entry has changed since last backup
=$0f						DOS_ATTR_LONGNAME = $0F                 ; Entry is the long file name
.0000						FILEDESC
>0000						STATUS              .byte ?             ; The status flags of the file descriptor (open, closed, error, EOF, etc.)
>0001						DEV                 .byte ?             ; The ID of the device holding the file
>0002						PATH                .dword ?            ; Pointer to a NULL terminated path string
>0006						CLUSTER             .dword ?            ; The current cluster of the file.
>000a						FIRST_CLUSTER       .dword ?            ; The ID of the first cluster in the file
>000e						BUFFER              .dword ?            ; Pointer to a cluster-sized buffer
>0012						SIZE                .dword ?            ; The size of the file
>0016						CREATE_DATE         .word ?             ; The creation date of the file
>0018						CREATE_TIME         .word ?             ; The creation time of the file
>001a						MODIFIED_DATE       .word ?             ; The modification date of the file
>001c						MODIFIED_TIME       .word ?             ; The modification time of the file
>001e						RESERVED            .word ?             ; Two reserved bytes to bring the descriptor up to 32 bytes
=$01						FD_STAT_READ = $01                      ; The file is readable
=$02						FD_STAT_WRITE = $02                     ; The file is writable
=$10						FD_STAT_ALLOC = $10                     ; The file descriptor has been allocated
=$38						FD_STAT_OPEN = $38                      ; The file is open
=$40						FD_STAT_ERROR = $40                     ; The file is in an error condition
=$80						FD_STAT_EOF = $80                       ; The file cursor is at the end of the file
=$0fffffff					FAT_LAST_CLUSTER = $0FFFFFFF            ; Code to mark the last cluster of a file
=1						VOLUMEMAX = 1                           ; The maximum number of mounted volumes we support
=32						DOS_DIR_ENTRY_SIZE = 32                 ; The size of a directory entry
=512						DOS_SECTOR_SIZE = 512                   ; The size of a sector
=$e5						DOS_DIR_ENT_UNUSED = $E5                ; Marker for an unused directory entry
=$00						PART_TYPE_FAT12 = $00                   ; "Partition" type: FAT12, used for floppy disks
=$0c						PART_TYPE_FAT32_LBA = $0C               ; Patition type: FAT32 with LBA addressing
=$29						BPB_EXTENDED_RECORD = $29               ; If SIGNATUREB of the BPB has this byte, the volume label is valid
=0						DOS_DIR_TYPE_FAT12ROOT = 0              ; Directory is a FAT12 root directory
=1						DOS_DIR_TYPE_FILE = 1                   ; Directory is a file type directory
=8						DOS_FD_MAX = 8                          ; The maximum number of open file descriptors
=1						DOS_ERR_READ = 1                        ; We could not read a sector, check BIOS_STATUS for details
=2						DOS_ERR_NOTMBR = 2                      ; We could not find the MBR
=3						DOS_ERR_NOFAT32 = 3                     ; We could not find a FAT32 parition using LBA
=4						DOS_ERR_NOINIT = 4                      ; We could not INIT the block device
=5						DOS_ERR_VOLID = 5                       ; Volume ID sector could not be loaded
=6						DOS_ERR_FAT = 6                         ; Can't scan the FAT for some reason
=7						DOS_ERR_BADPATH = 7                     ; The path was badly formatted
=8						DOS_ERR_NODIR = 8                       ; Could not read the directory
=9						DOS_ERR_NOTFOUND = 9                    ; File/directory requested was not found
=10						DOS_ERR_NOCLUSTER = 10                  ; There are no more clusters
=11						DOS_ERR_FILEEXISTS = 11                 ; There is already a file of that name
=12						DOS_ERR_NOTOPEN = 12                    ; File has not been open
=13						DOS_ERR_NOTREAD = 13                    ; File is not open for reading
=14						DOS_ERR_NOTWRITE = 14                   ; File is not open for writing
=15						DOS_ERR_OPEN = 15                       ; File is already open
=16						DOS_ERR_PGXSIG = 16                     ; File does not have the PGX signature
=17						DOS_ERR_NOEXEC = 17                     ; File does is not an executable format
=18						DOS_ERR_MEDIAFULL = 18                  ; There are no more free clusters on the drive
=19						DOS_ERR_WRITEPROT = 19                  ; The medium is write-protected
=20						DOS_ERR_FATUPDATE = 20                  ; Can't update the FAT
=21						DOS_ERR_DIRFULL = 21                    ; The directory is full
=22						DOS_ERR_NOFD = 22                       ; No file descriptors are available for allocation
=446						PART0_OFF = 446                         ; Offset to the first partition in the MBR
=4						PART_TYPE_OFF = 4                       ; Offset to the partition's type
=8						PART_LBA_OFF = 8                        ; Offset to the LBA of the first sector of the partition
=13						PART_SECT_COUNT_OFF = 13                ; Offset to the sector count of the partition
=510						MBR_SIGNATURE = 510                     ; The offset to the MBR signature bytes
=11						BPB_BYTEPERSEC_OFF = 11                 ; Offset in the BPB sector to the Bytes Per Sector
=13						BPB_SECPERCLUS_OFF = 13                 ; Offset in the BPB sector to the Sectors Per Cluster
=14						BPB_RSRVCLUS_OFF = 14                   ; Offset in the BPB sector to the Number of Reserved Clusters
=16						BPB_NUMFAT_OFF = 16                     ; Offset in the BPB sector to the Number of FATs
=17						BPB_ROOT_MAX_ENTRY_OFF = 17             ; Offset in the BPB sector to the Maximum # of entries in the root directory (FAT12)
=19						BPB_TOTAL_SECTORS = 19                  ; Offset in the BPB sector to the number of sectors on the partition or disk (FAT12)
=$24						BPB_SECPERFAT_OFF = $24                 ; Offset in the BPB sector to the Sectors Per FAT
=38						BPB_SIGNATUREB = 38                     ; Offset in the BPB sector to the second signature byte
=39						BPB_VOLUMEID = 39                       ; Offset in the BPB sector to the volume ID
=$2c						BPB_ROOTCLUS_OFF = $2C                  ; Offset in the BPB sector to the Root Cluster Number
=510						BPB_SIGNATURE = 510                     ; The offset to the MBR signature bytes
=$38a000					DOS_HIGH_VARIABLES      = $38A000
=$38a000					DEVICE                  = $38A000       ; 1 byte - The number of the block device
=$38a001					FILE_SYSTEM             = $38A001       ; 1 byte - The type of filesystem (FAT12, FAT32, etc.)
=$38a002					PARTITION               = $38A002       ; 1 byte - The number of the partitions on the device
=$38a003					SECTORS_PER_CLUSTER     = $38A003       ; 1 byte - The number of sectors in a cluster
=$38a004					FIRSTSECTOR             = $38A004       ; 4 bytes - The LBA of the first sector on the volume
=$38a008					SECTORCOUNT             = $38A008       ; 4 bytes - The number of sectors in the volume
=$38a00c					NUM_RSRV_SEC            = $38A00C       ; 2 bytes - The number of hidden or reserved sectors
=$38a00e					CLUSTER_SIZE            = $38A00E       ; 2 bytes - The size of a cluster in bytes
=$38a010					SEC_PER_FAT             = $38A010       ; 4 bytes - The number of sectors per FAT
=$38a014					FAT_BEGIN_LBA           = $38A014       ; 4 bytes - The LBA of the first sector of FAT #1
=$38a018					FAT2_BEGIN_LBA          = $38A018       ; 4 bytes - The LBA of the first sector of FAT #2
=$38a01c					CLUSTER_BEGIN_LBA       = $38A01C       ; 4 bytes - The LBA of the first cluster in the storage area
=$38a020					ROOT_DIR_FIRST_CLUSTER  = $38A020       ; 4 bytes - The number of the first cluster in the root directory
=$38a024					ROOT_DIR_MAX_ENTRY      = $38A024       ; 2 bytes - The maximum number of entries in the root directory (0 = no limit)
=$38a026					VOLUME_ID               = $38A026       ; 4 bytes - The ID of the volume
=$38a02a					DOS_CURR_CLUS           = $38A02A       ; 4 bytes - The current cluster (for delete)
=$38a02e					DOS_NEXT_CLUS           = $38A02E       ; 4 bytes - The next cluster in a file (for delete)
=$38a032					DOS_DIR_BLOCK_ID        = $38A032       ; 4 bytes - The ID of the current directory block
=$38a036					DOS_NEW_CLUSTER         = $38A036       ; 4 bytes - Space to store a newly written cluster ID
=$38a03a					DOS_SHORT_NAME          = $38A03A       ; 11 bytes - The short name for a desired file
=$38a045					DOS_DIR_TYPE            = $38A045       ; 1 byte - a code indicating the type of the current directory (0 = cluster based, $80 = sector based)
=$38a046					DOS_CURR_DIR_ID         = $38A046       ; 4 byte - the ID of the first sector or cluster of the current directory
=$38a04a					DOS_DEV_NAMES           = $38A04A       ; 4 byte - pointer to the linked list of device names
=$38a04e					FDC_MOTOR_TIMER         = $38A04E       ; 2 bytes - count-down timer to automatically turn off the FDC spindle motor
=$38a050					DOS_MOUNT_DEV           = $38A050       ; 1 byte - the device code of the currently mounted device
=$38a100					DOS_DIR_CLUSTER         = $38A100       ; 512 bytes - A buffer for directory entries
=$38a300					DOS_DIR_CLUSTER_END     = $38A300       ; The byte just past the end of the directory cluster buffer
=$38a300					DOS_SECTOR              = $38A300       ; 512 bytes - A buffer for block device read/write
=$38a500					DOS_SECTOR_END          = $38A500       ; The byte just past the end of the cluster buffer
=$38a500					DOS_FAT_SECTORS         = $38A500       ; 1024 bytes - two sectors worth of the FAT
=$38a900					DOS_FAT_SECTORS_END     = $38A900       ; The byte just past the end of the FAT buffers
=$38a900					DOS_BOOT_SECTOR         = $38A900       ; A sector for holding the boot sector
=$38ab00					DOS_BOOT_SECTOR_END     = $38AB00
=$38ab00					DOS_SPARE_SECTOR        = $38AB00       ; A spare 512 byte buffer for loading sectors
=$38ad00					DOS_SPARE_SECTOR_END    = $38AD00
=$38ad00					DOS_SPARE_FD            = $38AD00       ; A spare file descriptor buffer
=3714336					DOS_SPARE_FD_END        = DOS_SPARE_FD + SIZE(FILEDESC)
=3714336					DOS_FILE_DESCS          = DOS_SPARE_FD_END
=3714592					DOS_FILE_DESCS_END      = DOS_FILE_DESCS + SIZE(FILEDESC) * DOS_FD_MAX
=$38b000					DOS_FILE_BUFFS          = $38B000
=3719168					DOS_FILE_BUFFS_END      = DOS_FILE_BUFFS + DOS_SECTOR_SIZE * DOS_FD_MAX
.394482						DOS_INIT
.394482		8b		phb		                PHB
.394483		0b		phd		                PHD
.394484		08		php		                PHP
.394485		48		pha		                PHA             ; begin setdbr macro
.394486		08		php		                PHP
.394487		e2 20		sep #$20	                SEP #$20        ; set A short
.394489		a9 00		lda #$00	                LDA #0
.39448b		48		pha		                PHA
.39448c		ab		plb		                PLB
.39448d		28		plp		                PLP
.39448e		68		pla		                PLA             ; end setdbr macro
.39448f		48		pha		                PHA             ; begin setdp macro
.394490		08		php		                PHP
.394491		c2 20		rep #$20	                REP #$20        ; set A long
.394493		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394496		5b		tcd		                TCD
.394497		28		plp		                PLP
.394498		68		pla		                PLA             ; end setdp macro
.394499		e2 20		sep #$20	                SEP #$20        ; set A short
.39449b		c2 10		rep #$10	                REP #$10        ; set X long
.39449d		a2 00 00	ldx #$0000	                LDX #0                  ; Zero out all the bank 0 variables
.3944a0		a9 00		lda #$00	                LDA #0
.3944a2		9d 20 03	sta $0320,x	b0_clr_loop     STA @w SDOS_VARIABLES,X
.3944a5		e8		inx		                INX
.3944a6		e0 15 02	cpx #$0215	                CPX #<>(FDC_CMD_RETRY - SDOS_VARIABLES + 1)
.3944a9		d0 f7		bne $3944a2	                BNE b0_clr_loop
.3944ab		48		pha		                PHA             ; begin setdbr macro
.3944ac		08		php		                PHP
.3944ad		e2 20		sep #$20	                SEP #$20        ; set A short
.3944af		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.3944b1		48		pha		                PHA
.3944b2		ab		plb		                PLB
.3944b3		28		plp		                PLP
.3944b4		68		pla		                PLA             ; end setdbr macro
.3944b5		48		pha		                PHA             ; begin setdp macro
.3944b6		08		php		                PHP
.3944b7		c2 20		rep #$20	                REP #$20        ; set A long
.3944b9		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3944bc		5b		tcd		                TCD
.3944bd		28		plp		                PLP
.3944be		68		pla		                PLA             ; end setdp macro
.3944bf		e2 20		sep #$20	                SEP #$20        ; set A short
.3944c1		c2 10		rep #$10	                REP #$10        ; set X long
.3944c3		a2 00 00	ldx #$0000	                LDX #0                  ; Zero out all the bank $38 variables
.3944c6		a9 00		lda #$00	                LDA #0
.3944c8		9d 00 a0	sta $38a000,x	b38_clr_loop    STA @w DOS_HIGH_VARIABLES,X
.3944cb		e8		inx		                INX
.3944cc		e0 01 20	cpx #$2001	                CPX #<>(DOS_FILE_BUFFS_END - DOS_HIGH_VARIABLES + 1)
.3944cf		d0 f7		bne $3944c8	                BNE b38_clr_loop
.3944d1		c2 20		rep #$20	                REP #$20        ; set A long
.3944d3		a9 81 48	lda #$4881	                LDA #<>DOS_HD_DESC      ; Initialize the device names list
.3944d6		8f 4a a0 38	sta $38a04a	                STA @l DOS_DEV_NAMES
.3944da		a9 39 00	lda #$0039	                LDA #`DOS_HD_DESC
.3944dd		8f 4c a0 38	sta $38a04c	                STA @l DOS_DEV_NAMES+2
.3944e1		e2 20		sep #$20	                SEP #$20        ; set A short
.3944e3		a9 02		lda #$02	                LDA #BIOS_DEV_SD        ; Default to the SD card
.3944e5		85 01		sta $0321	                STA BIOS_DEV
.3944e7		a9 ff		lda #$ff	                LDA #$FF                ; Set the mounted device to a sentinel value
.3944e9		8f 50 a0 38	sta $38a050	                STA @l DOS_MOUNT_DEV
.3944ed		a9 00		lda #$00	                LDA #0
.3944ef		a2 00 00	ldx #$0000	                LDX #0
.3944f2		9d 20 ad	sta $38ad20,x	fd_zero_loop    STA @w DOS_FILE_DESCS,X
.3944f5		e8		inx		                INX
.3944f6		e0 00 01	cpx #$0100	                CPX #(DOS_FILE_DESCS_END - DOS_FILE_DESCS)
.3944f9		d0 f7		bne $3944f2	                BNE fd_zero_loop
.3944fb		a9 00		lda #$00	                LDA #0
.3944fd		a2 00 00	ldx #$0000	                LDX #0
.394500		9d 00 b0	sta $38b000,x	sect_zero_loop  STA @w DOS_FILE_BUFFS,X
.394503		e8		inx		                INX
.394504		e0 00 10	cpx #$1000	                CPX #(DOS_FILE_BUFFS_END - DOS_FILE_BUFFS)
.394507		d0 f7		bne $394500	                BNE sect_zero_loop
.394509		c2 20		rep #$20	                REP #$20        ; set A long
.39450b		a9 20 ad	lda #$ad20	                LDA #<>DOS_FILE_DESCS   ; Initialize a pointer to the file descriptors
.39450e		85 20		sta $0340	                STA @b DOS_FD_PTR
.394510		a9 38 00	lda #$0038	                LDA #`DOS_FILE_DESCS
.394513		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.394515		a9 00 b0	lda #$b000	                LDA #<>DOS_FILE_BUFFS   ; Initialize a pointer to the sector buffers
.394518		85 28		sta $0348	                STA @b DOS_TEMP
.39451a		a9 38 00	lda #$0038	                LDA #`DOS_FILE_BUFFS
.39451d		85 2a		sta $034a	                STA @b DOS_TEMP+2
.39451f		a2 08 00	ldx #$0008	                LDX #DOS_FD_MAX         ; Set how many file descriptors to update
.394522		a0 0e 00	ldy #$000e	fd_buff_loop    LDY #FILEDESC.BUFFER    ; Set the file descriptor's buffer pointer
.394525		a5 28		lda $0348	                LDA @b DOS_TEMP
.394527		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.394529		c8		iny		                INY
.39452a		c8		iny		                INY
.39452b		a5 2a		lda $034a	                LDA @b DOS_TEMP+2
.39452d		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.39452f		18		clc		                CLC                     ; Advance the file descriptor pointer to the next file descriptor
.394530		a5 20		lda $0340	                LDA @b DOS_FD_PTR
.394532		69 20 00	adc #$0020	                ADC #SIZE(FILEDESC)
.394535		85 20		sta $0340	                STA @b DOS_FD_PTR
.394537		a5 22		lda $0342	                LDA @b DOS_FD_PTR+2
.394539		69 00 00	adc #$0000	                ADC #0
.39453c		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.39453e		18		clc		                CLC                     ; Advance the sector buffer pointer to the next buffer
.39453f		a5 28		lda $0348	                LDA @b DOS_TEMP
.394541		69 00 02	adc #$0200	                ADC #DOS_SECTOR_SIZE
.394544		85 28		sta $0348	                STA @b DOS_TEMP
.394546		a5 2a		lda $034a	                LDA @b DOS_TEMP+2
.394548		69 00 00	adc #$0000	                ADC #0
.39454b		85 2a		sta $034a	                STA @b DOS_TEMP+2
.39454d		ca		dex		                DEX                     ; Count down the descriptors...
.39454e		d0 d2		bne $394522	                BNE fd_buff_loop        ; If not zero, keep setting the buffer pointers
.394550		28		plp		                PLP
.394551		2b		pld		                PLD
.394552		ab		plb		                PLB
.394553		6b		rtl		                RTL
.394554						DOS_MOUNT
.394554		8b		phb		                PHB
.394555		0b		phd		                PHD
.394556		08		php		                PHP
.394557		48		pha		                PHA             ; begin setdbr macro
.394558		08		php		                PHP
.394559		e2 20		sep #$20	                SEP #$20        ; set A short
.39455b		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.39455d		48		pha		                PHA
.39455e		ab		plb		                PLB
.39455f		28		plp		                PLP
.394560		68		pla		                PLA             ; end setdbr macro
.394561		48		pha		                PHA             ; begin setdp macro
.394562		08		php		                PHP
.394563		c2 20		rep #$20	                REP #$20        ; set A long
.394565		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394568		5b		tcd		                TCD
.394569		28		plp		                PLP
.39456a		68		pla		                PLA             ; end setdp macro
.39456b		e2 20		sep #$20	                SEP #$20        ; set A short
.39456d		a5 01		lda $0321	                LDA BIOS_DEV            ; Get the device to moount
.39456f		8f 50 a0 38	sta $38a050	try_mount       STA @l DOS_MOUNT_DEV    ; Save the device we're going to try to mount
.394573		c9 02		cmp #$02	                CMP #BIOS_DEV_SD        ; Is it the SDC?
.394575		f0 1f		beq $394596	                BEQ do_sdc_mount        ; Yes: attempt to mount it
.394577		c9 06		cmp #$06	                CMP #BIOS_DEV_HD0       ; Is it HD0?
.394579		f0 26		beq $3945a1	                BEQ do_ide_mount        ; Yes: attempt to mount the IDE drive
.39457b		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC       ; Is it the FDC?
.39457d		f0 0b		beq $39458a	                BEQ do_fdc_mount        ; Yes: attempt to mount it
.39457f		a9 04		lda #$04	                LDA #DOS_ERR_NOINIT     ; Otherwise: return a bad device error
.394581		85 0e		sta $032e	                STA DOS_STATUS
.394583		a9 80		lda #$80	                LDA #BIOS_ERR_BADDEV
.394585		85 00		sta $0320	                STA BIOS_STATUS
.394587		82 7c 01	brl $394706	                BRL ret_failure
.39458a		22 ac 67 39	jsl $3967ac	do_fdc_mount    JSL FDC_MOUNT           ; Attempt to mount the floppy disk
.39458e		b0 03		bcs $394593	                BCS fdc_success
.394590		82 73 01	brl $394706	                BRL ret_failure
.394593		82 67 01	brl $3946fd	fdc_success     BRL ret_success
.394596		22 b6 5d 39	jsl $395db6	do_sdc_mount    JSL SDC_INIT            ; Yes: Initialize access to the SDC
.39459a		b0 10		bcs $3945ac	                BCS get_mbr             ; Continue if success
.39459c		a9 04		lda #$04	                LDA #DOS_ERR_NOINIT     ; Otherwise: return an error
.39459e		82 65 01	brl $394706	                BRL ret_failure
.3945a1		22 f4 6b 39	jsl $396bf4	do_ide_mount    JSL IDE_INIT            ; Yes: Initialize access to the IDE drive
.3945a5		b0 05		bcs $3945ac	                BCS get_mbr             ; Continue if success
.3945a7		a9 04		lda #$04	                LDA #DOS_ERR_NOINIT     ; Otherwise: return an error
.3945a9		82 5a 01	brl $394706	                BRL ret_failure
.3945ac						get_mbr
.3945ac		c2 30		rep #$30	                REP #$30        ; set A&X long
.3945ae		64 02		stz $0322	                STZ BIOS_LBA            ; Get the MBR
.3945b0		64 04		stz $0324	                STZ BIOS_LBA+2
.3945b2		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR       ; Into DOS_SECTOR
.3945b5		85 06		sta $0326	                STA BIOS_BUFF_PTR
.3945b7		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
.3945ba		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.3945bc		22 44 10 00	jsl $001044	                JSL GETBLOCK            ; Try to read the MBR
.3945c0		b0 07		bcs $3945c9	                BCS chk_signature       ; If success, check the signature bytes
.3945c2		e2 20		sep #$20	                SEP #$20        ; set A short
.3945c4		a9 01		lda #$01	                LDA #DOS_ERR_READ       ; Otherwise: report we couldn't read the first sector
.3945c6		82 3d 01	brl $394706	                BRL ret_failure
.3945c9						chk_signature
.3945c9		e2 20		sep #$20	                SEP #$20        ; set A short
.3945cb		ad fe a4	lda $38a4fe	                LDA DOS_SECTOR+MBR_SIGNATURE
.3945ce		c9 55		cmp #$55	                CMP #$55                ; Is first byte of signature $55?
.3945d0		d0 07		bne $3945d9	                BNE not_mbr             ; No: signal we could find the MBR
.3945d2		ad ff a4	lda $38a4ff	                LDA DOS_SECTOR+MBR_SIGNATURE+1
.3945d5		c9 aa		cmp #$aa	                CMP #$AA                ; Is second byte of signature $AA?
.3945d7		f0 05		beq $3945de	                BEQ chk_part_type       ; Yes: we have an MBR
.3945d9		a9 02		lda #$02	not_mbr         LDA #DOS_ERR_NOTMBR     ; Return that we didn't find the MBR
.3945db		82 28 01	brl $394706	                BRL ret_failure
.3945de		ad c2 a4	lda $38a4c2	chk_part_type   LDA DOS_SECTOR+PART0_OFF+PART_TYPE_OFF
.3945e1		c9 0c		cmp #$0c	                CMP #PART_TYPE_FAT32_LBA
.3945e3		f0 05		beq $3945ea	                BEQ get_LBA             ; Is FAT32 with LBA?
.3945e5		a9 03		lda #$03	                LDA #DOS_ERR_NOFAT32    ; No: return No FAT32 found error
.3945e7		82 1c 01	brl $394706	                BRL ret_failure
.3945ea		8d 01 a0	sta $38a001	get_LBA         STA FILE_SYSTEM         ; Save the file system of the partition
.3945ed		c2 20		rep #$20	                REP #$20        ; set A long
.3945ef		ad c6 a4	lda $38a4c6	                LDA DOS_SECTOR+PART0_OFF+PART_LBA_OFF
.3945f2		8d 04 a0	sta $38a004	                STA FIRSTSECTOR
.3945f5		ad c8 a4	lda $38a4c8	                LDA DOS_SECTOR+PART0_OFF+PART_LBA_OFF+2
.3945f8		8d 06 a0	sta $38a006	                STA FIRSTSECTOR+2
.3945fb		ad cb a4	lda $38a4cb	                LDA DOS_SECTOR+PART0_OFF+PART_SECT_COUNT_OFF
.3945fe		8d 08 a0	sta $38a008	                STA SECTORCOUNT
.394601		ad cd a4	lda $38a4cd	                LDA DOS_SECTOR+PART0_OFF+PART_SECT_COUNT_OFF+2
.394604		8d 0a a0	sta $38a00a	                STA SECTORCOUNT+2
.394607		e2 20		sep #$20	                SEP #$20        ; set A short
.394609		a5 01		lda $0321	                LDA BIOS_DEV            ; Save the device number
.39460b		8d 00 a0	sta $38a000	                STA DEVICE
.39460e		a9 00		lda #$00	                LDA #0
.394610		8d 02 a0	sta $38a002	                STA PARTITION           ; For the moment, we only support the first partition
.394613		c2 20		rep #$20	                REP #$20        ; set A long
.394615		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR
.394618		85 06		sta $0326	                STA BIOS_BUFF_PTR
.39461a		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
.39461d		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.39461f		ad 04 a0	lda $38a004	                LDA FIRSTSECTOR
.394622		85 02		sta $0322	                STA BIOS_LBA
.394624		ad 06 a0	lda $38a006	                LDA FIRSTSECTOR+2
.394627		85 04		sta $0324	                STA BIOS_LBA+2
.394629		22 44 10 00	jsl $001044	                JSL GETBLOCK            ; Attempt to load the volume ID
.39462d		b0 1c		bcs $39464b	                BCS get_first_sec       ; Got it? Start parsing it
.39462f		e2 20		sep #$20	                SEP #$20        ; set A short
.394631		a9 05		lda #$05	                LDA #DOS_ERR_VOLID      ; Otherwise: return an error
.394633		82 d0 00	brl $394706	                BRL ret_failure
.394636						chk_bpb_sig
.394636		e2 20		sep #$20	                SEP #$20        ; set A short
.394638		ad fe a4	lda $38a4fe	                LDA DOS_SECTOR+BPB_SIGNATURE
.39463b		c9 55		cmp #$55	                CMP #$55                ; Is first byte of signature $55?
.39463d		d0 07		bne $394646	                BNE not_bpb             ; No: signal we could find the volume ID
.39463f		ad ff a4	lda $38a4ff	                LDA DOS_SECTOR+BPB_SIGNATURE+1
.394642		c9 aa		cmp #$aa	                CMP #$AA                ; Is second byte of signature $AA?
.394644		f0 05		beq $39464b	                BEQ get_first_sec       ; Yes: we have an volume ID
.394646		a9 05		lda #$05	not_bpb         LDA #DOS_ERR_VOLID      ; Return that we didn't find the Volume ID (BPB)
.394648		82 bb 00	brl $394706	                BRL ret_failure
.39464b						get_first_sec
.39464b		c2 20		rep #$20	                REP #$20        ; set A long
.39464d		ad 2c a3	lda $38a32c	                LDA DOS_SECTOR+BPB_ROOTCLUS_OFF
.394650		8d 20 a0	sta $38a020	                STA ROOT_DIR_FIRST_CLUSTER
.394653		ad 2e a3	lda $38a32e	                LDA DOS_SECTOR+BPB_ROOTCLUS_OFF+2
.394656		8d 22 a0	sta $38a022	                STA ROOT_DIR_FIRST_CLUSTER+2
.394659		ad 0e a3	lda $38a30e	                LDA DOS_SECTOR+BPB_RSRVCLUS_OFF
.39465c		8d 0c a0	sta $38a00c	                STA NUM_RSRV_SEC
.39465f		18		clc		                CLC                     ; fat_begin_lba := FirstSector + Number_of_Reserved_Sectors
.394660		ad 04 a0	lda $38a004	                LDA FIRSTSECTOR
.394663		6d 0c a0	adc $38a00c	                ADC NUM_RSRV_SEC
.394666		8d 14 a0	sta $38a014	                STA FAT_BEGIN_LBA
.394669		ad 06 a0	lda $38a006	                LDA FIRSTSECTOR+2
.39466c		69 00 00	adc #$0000	                ADC #0
.39466f		8d 16 a0	sta $38a016	                STA FAT_BEGIN_LBA+2
.394672		e2 20		sep #$20	                SEP #$20        ; set A short
.394674		a2 00 00	ldx #$0000	                LDX #0
.394677		bf 24 a3 38	lda $38a324,x	cpy_secperfat   LDA @l DOS_SECTOR+BPB_SECPERFAT_OFF,X
.39467b		9f 10 a0 38	sta $38a010,x	                STA @l SEC_PER_FAT,X
.39467f		e8		inx		                INX
.394680		e0 04 00	cpx #$0004	                CPX #4
.394683		d0 f2		bne $394677	                BNE cpy_secperfat
.394685		ad 10 a0	lda $38a010	                LDA SEC_PER_FAT
.394688		0a		asl a		                ASL A
.394689		8d 1c a0	sta $38a01c	                STA CLUSTER_BEGIN_LBA
.39468c		ad 11 a0	lda $38a011	                LDA SEC_PER_FAT+1
.39468f		2a		rol a		                ROL A
.394690		8d 1d a0	sta $38a01d	                STA CLUSTER_BEGIN_LBA+1
.394693		ad 12 a0	lda $38a012	                LDA SEC_PER_FAT+2
.394696		2a		rol a		                ROL A
.394697		8d 1e a0	sta $38a01e	                STA CLUSTER_BEGIN_LBA+2
.39469a		ad 13 a0	lda $38a013	                LDA SEC_PER_FAT+3
.39469d		2a		rol a		                ROL A
.39469e		8d 1f a0	sta $38a01f	                STA CLUSTER_BEGIN_LBA+3
.3946a1		18		clc		                CLC
.3946a2		ad 1c a0	lda $38a01c	                LDA CLUSTER_BEGIN_LBA
.3946a5		6d 14 a0	adc $38a014	                ADC FAT_BEGIN_LBA
.3946a8		8d 1c a0	sta $38a01c	                STA CLUSTER_BEGIN_LBA
.3946ab		ad 1d a0	lda $38a01d	                LDA CLUSTER_BEGIN_LBA+1
.3946ae		6d 15 a0	adc $38a015	                ADC FAT_BEGIN_LBA+1
.3946b1		8d 1d a0	sta $38a01d	                STA CLUSTER_BEGIN_LBA+1
.3946b4		ad 1e a0	lda $38a01e	                LDA CLUSTER_BEGIN_LBA+2
.3946b7		6d 16 a0	adc $38a016	                ADC FAT_BEGIN_LBA+2
.3946ba		8d 1e a0	sta $38a01e	                STA CLUSTER_BEGIN_LBA+2
.3946bd		ad 1f a0	lda $38a01f	                LDA CLUSTER_BEGIN_LBA+3
.3946c0		6d 17 a0	adc $38a017	                ADC FAT_BEGIN_LBA+3
.3946c3		8d 1f a0	sta $38a01f	                STA CLUSTER_BEGIN_LBA+3
.3946c6		e2 20		sep #$20	                SEP #$20        ; set A short
.3946c8		ad 0d a3	lda $38a30d	                LDA DOS_SECTOR+BPB_SECPERCLUS_OFF
.3946cb		8d 03 a0	sta $38a003	                STA SECTORS_PER_CLUSTER
.3946ce		18		clc		                CLC
.3946cf		ad 14 a0	lda $38a014	                LDA FAT_BEGIN_LBA                       ; Compute the address of the first sector of
.3946d2		6d 10 a0	adc $38a010	                ADC SEC_PER_FAT                         ; the second copy of the FAT
.3946d5		8d 18 a0	sta $38a018	                STA FAT2_BEGIN_LBA
.3946d8		ad 15 a0	lda $38a015	                LDA FAT_BEGIN_LBA+1
.3946db		6d 11 a0	adc $38a011	                ADC SEC_PER_FAT+1
.3946de		8d 19 a0	sta $38a019	                STA FAT2_BEGIN_LBA+1
.3946e1		ad 16 a0	lda $38a016	                LDA FAT_BEGIN_LBA+2
.3946e4		6d 12 a0	adc $38a012	                ADC SEC_PER_FAT+2
.3946e7		8d 1a a0	sta $38a01a	                STA FAT2_BEGIN_LBA+2
.3946ea		ad 17 a0	lda $38a017	                LDA FAT_BEGIN_LBA+3
.3946ed		6d 13 a0	adc $38a013	                ADC SEC_PER_FAT+3
.3946f0		8d 1b a0	sta $38a01b	                STA FAT2_BEGIN_LBA+3
.3946f3		a9 00		lda #$00	                LDA #<DOS_SECTOR_SIZE                   ; Default to one sector's worth of bytes
.3946f5		8d 0e a0	sta $38a00e	                STA CLUSTER_SIZE
.3946f8		a9 02		lda #$02	                LDA #>DOS_SECTOR_SIZE
.3946fa		8d 0f a0	sta $38a00f	                STA CLUSTER_SIZE+1
.3946fd						ret_success
.3946fd		e2 20		sep #$20	                SEP #$20        ; set A short
.3946ff		64 0e		stz $032e	                STZ DOS_STATUS          ; Set status code to 0
.394701		28		plp		                PLP
.394702		2b		pld		                PLD
.394703		ab		plb		                PLB
.394704		38		sec		                SEC
.394705		6b		rtl		                RTL
.394706						ret_failure
.394706		e2 20		sep #$20	                SEP #$20        ; set A short
.394708		85 0e		sta $032e	                STA DOS_STATUS          ; Save the status code
.39470a		28		plp		                PLP
.39470b		2b		pld		                PLD
.39470c		ab		plb		                PLB
.39470d		18		clc		                CLC
.39470e		6b		rtl		                RTL
.39470f						DOS_TESTBOOT
.39470f		8b		phb		                PHB
.394710		0b		phd		                PHD
.394711		da		phx		                PHX
.394712		08		php		                PHP
.394713		48		pha		                PHA             ; begin setdbr macro
.394714		08		php		                PHP
.394715		e2 20		sep #$20	                SEP #$20        ; set A short
.394717		a9 00		lda #$00	                LDA #0
.394719		48		pha		                PHA
.39471a		ab		plb		                PLB
.39471b		28		plp		                PLP
.39471c		68		pla		                PLA             ; end setdbr macro
.39471d		48		pha		                PHA             ; begin setdp macro
.39471e		08		php		                PHP
.39471f		c2 20		rep #$20	                REP #$20        ; set A long
.394721		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394724		5b		tcd		                TCD
.394725		28		plp		                PLP
.394726		68		pla		                PLA             ; end setdp macro
.394727		c2 10		rep #$10	                REP #$10        ; set X long
.394729						chk_dev
.394729		e2 20		sep #$20	                SEP #$20        ; set A short
.39472b		a5 01		lda $0321	                LDA @b BIOS_DEV             ; Look at the device #
.39472d		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC           ; Is it the floppy drive?
.39472f		f0 24		beq $394755	                BEQ chk_vbr_brl             ; Yes: check if BRL is in the right place in the VBR
.394731		c2 30		rep #$30	                REP #$30        ; set A&X long
.394733		a9 00 00	lda #$0000	                LDA #0                      ; Point to the MBR
.394736		85 02		sta $0322	                STA @b BIOS_LBA
.394738		85 04		sta $0324	                STA @b BIOS_LBA+2
.39473a		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR           ; And the buffer
.39473d		85 06		sta $0326	                STA @b BIOS_BUFF_PTR
.39473f		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
.394742		85 08		sta $0328	                STA @b BIOS_BUFF_PTR+2
.394744		22 44 10 00	jsl $001044	                JSL GETBLOCK                ; Try to load the MBR
.394748		b0 03		bcs $39474d	                BCS chk_mbr_brl
.39474a		82 47 00	brl $394794	                BRL done                    ; If failed... just return
.39474d						chk_mbr_brl
.39474d		e2 20		sep #$20	                SEP #$20        ; set A short
.39474f		af 00 a3 38	lda $38a300	                LDA @l DOS_SECTOR           ; Check the first byte of the MBR
.394753		80 04		bra $394759	                BRA chk_brl
.394755		af 3e a3 38	lda $38a33e	chk_vbr_brl     LDA @l DOS_SECTOR+FDC_BOOT_START
.394759		c9 80		cmp #$80	chk_brl         CMP #$80                    ; Is the first byte a BRL/BRA instruction?
.39475b		f0 06		beq $394763	                BEQ chk_magic               ; Yes: check for the magic text
.39475d		c9 82		cmp #$82	                CMP #$82
.39475f		f0 02		beq $394763	                BEQ chk_magic
.394761		80 31		bra $394794	                BRA done                    ; No: just return
.394763		a2 00 00	ldx #$0000	chk_magic       LDX #0
.394766		bf 03 a3 38	lda $38a303,x	magic_loop      LDA @l DOS_SECTOR+3,X       ; Check the "vendor" byte
.39476a		df 99 47 39	cmp $394799,x	                CMP DOS_BOOT_MAGIC,X        ; Compare it against our boot magic code
.39476e		d0 24		bne $394794	                BNE done                    ; If it's not equal, just return
.394770		e8		inx		                INX                         ; Otherwise, check the next one
.394771		e0 08 00	cpx #$0008	                CPX #8
.394774		d0 f0		bne $394766	                BNE magic_loop              ; Until we've checked all 8 bytes
.394776		c2 30		rep #$30	                REP #$30        ; set A&X long
.394778		a9 00 02	lda #$0200	                LDA #DOS_SECTOR_SIZE
.39477b		a2 00 a5	ldx #$a500	                LDX #<>(DOS_SECTOR+DOS_SECTOR_SIZE)
.39477e		a0 00 ab	ldy #$ab00	                LDY #<>(DOS_BOOT_SECTOR+DOS_SECTOR_SIZE)
.394781		44 38 38	mvp $38,$38	                MVP #`DOS_SECTOR, #`DOS_BOOT_SECTOR
.394784		e2 20		sep #$20	                SEP #$20        ; set A short
.394786		a5 01		lda $0321	                LDA @b BIOS_DEV             ; Check the device
.394788		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC           ; Is it the FDC?
.39478a		f0 04		beq $394790	                BEQ jmp_fdc_start           ; Yes: jump to the start of the VBR code
.39478c		5c 00 a9 38	jmp $38a900	                JML DOS_BOOT_SECTOR         ; No: it's an MBR, start at the first byte
.394790		5c 3e a9 38	jmp $38a93e	jmp_fdc_start   JML DOS_BOOT_SECTOR+FDC_BOOT_START
.394794		28		plp		done            PLP
.394795		2b		pld		                PLD
.394796		ab		plb		                PLB
.394797		fa		plx		                PLX
.394798		6b		rtl		                RTL
>394799		43 32 35 36 44 4f 53 20		DOS_BOOT_MAGIC  .text "C256DOS "
.3947a1						DOS_CALC_LBA
.3947a1		8b		phb		                PHB
.3947a2		0b		phd		                PHD
.3947a3		08		php		                PHP
.3947a4		48		pha		                PHA             ; begin setdbr macro
.3947a5		08		php		                PHP
.3947a6		e2 20		sep #$20	                SEP #$20        ; set A short
.3947a8		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.3947aa		48		pha		                PHA
.3947ab		ab		plb		                PLB
.3947ac		28		plp		                PLP
.3947ad		68		pla		                PLA             ; end setdbr macro
.3947ae		48		pha		                PHA             ; begin setdp macro
.3947af		08		php		                PHP
.3947b0		c2 20		rep #$20	                REP #$20        ; set A long
.3947b2		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3947b5		5b		tcd		                TCD
.3947b6		28		plp		                PLP
.3947b7		68		pla		                PLA             ; end setdp macro
.3947b8		c2 20		rep #$20	                REP #$20        ; set A long
.3947ba		38		sec		                SEC
.3947bb		a5 10		lda $0330	                LDA DOS_CLUS_ID                     ; cluster - 2
.3947bd		e9 02 00	sbc #$0002	                SBC #2
.3947c0		85 28		sta $0348	                STA DOS_TEMP
.3947c2		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.3947c4		e9 00 00	sbc #$0000	                SBC #0
.3947c7		85 2a		sta $034a	                STA DOS_TEMP+2
.3947c9		e2 10		sep #$10	                SEP #$10        ; set X short
.3947cb		ae 03 a0	ldx $38a003	                LDX SECTORS_PER_CLUSTER
.3947ce		e0 01		cpx #$01	mult_loop       CPX #1
.3947d0		f0 07		beq $3947d9	                BEQ add_offset
.3947d2		06 28		asl $0348	                ASL DOS_TEMP
.3947d4		26 28		rol $0348	                ROL DOS_TEMP
.3947d6		ca		dex		                DEX
.3947d7		80 f5		bra $3947ce	                BRA mult_loop
.3947d9		18		clc		add_offset      CLC
.3947da		a5 28		lda $0348	                LDA DOS_TEMP                        ; cluster_being_lba + (cluster - 2) * SECTORS_PER_CLUSTER
.3947dc		6d 1c a0	adc $38a01c	                ADC CLUSTER_BEGIN_LBA
.3947df		85 02		sta $0322	                STA BIOS_LBA
.3947e1		a5 2a		lda $034a	                LDA DOS_TEMP+2
.3947e3		6d 1e a0	adc $38a01e	                ADC CLUSTER_BEGIN_LBA+2
.3947e6		85 04		sta $0324	                STA BIOS_LBA+2
.3947e8		28		plp		                PLP
.3947e9		2b		pld		                PLD
.3947ea		ab		plb		                PLB
.3947eb		6b		rtl		                RTL
.3947ec						DOS_GETCLUSTER
.3947ec		8b		phb		                PHB
.3947ed		0b		phd		                PHD
.3947ee		08		php		                PHP
.3947ef		48		pha		                PHA             ; begin setdbr macro
.3947f0		08		php		                PHP
.3947f1		e2 20		sep #$20	                SEP #$20        ; set A short
.3947f3		a9 00		lda #$00	                LDA #0
.3947f5		48		pha		                PHA
.3947f6		ab		plb		                PLB
.3947f7		28		plp		                PLP
.3947f8		68		pla		                PLA             ; end setdbr macro
.3947f9		48		pha		                PHA             ; begin setdp macro
.3947fa		08		php		                PHP
.3947fb		c2 20		rep #$20	                REP #$20        ; set A long
.3947fd		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394800		5b		tcd		                TCD
.394801		28		plp		                PLP
.394802		68		pla		                PLA             ; end setdp macro
.394803		c2 20		rep #$20	                REP #$20        ; set A long
.394805		a5 1c		lda $033c	                LDA DOS_BUFF_PTR                    ; Set the BIOS BUFFER
.394807		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394809		a5 1e		lda $033e	                LDA DOS_BUFF_PTR+2
.39480b		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.39480d		22 a1 47 39	jsl $3947a1	                JSL DOS_CALC_LBA                    ; Convert the cluster # to the first sector's LBA
.394811		22 44 10 00	jsl $001044	                JSL GETBLOCK                        ; Get the first block of the cluster
.394815		90 09		bcc $394820	                BCC ret_failure
.394817						ret_success
.394817		e2 20		sep #$20	                SEP #$20        ; set A short
.394819		64 0e		stz $032e	                STZ DOS_STATUS
.39481b		28		plp		                PLP
.39481c		2b		pld		                PLD
.39481d		ab		plb		                PLB
.39481e		38		sec		                SEC
.39481f		6b		rtl		                RTL
.394820						ret_failure
.394820		e2 20		sep #$20	                SEP #$20        ; set A short
.394822		85 0e		sta $032e	                STA DOS_STATUS
.394824		28		plp		                PLP
.394825		2b		pld		                PLD
.394826		ab		plb		                PLB
.394827		18		clc		                CLC
.394828		6b		rtl		                RTL
.394829						DOS_PUTCLUSTER
.394829		8b		phb		                PHB
.39482a		0b		phd		                PHD
.39482b		08		php		                PHP
.39482c		48		pha		                PHA             ; begin setdbr macro
.39482d		08		php		                PHP
.39482e		e2 20		sep #$20	                SEP #$20        ; set A short
.394830		a9 00		lda #$00	                LDA #0
.394832		48		pha		                PHA
.394833		ab		plb		                PLB
.394834		28		plp		                PLP
.394835		68		pla		                PLA             ; end setdbr macro
.394836		48		pha		                PHA             ; begin setdp macro
.394837		08		php		                PHP
.394838		c2 20		rep #$20	                REP #$20        ; set A long
.39483a		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39483d		5b		tcd		                TCD
.39483e		28		plp		                PLP
.39483f		68		pla		                PLA             ; end setdp macro
.394840		c2 20		rep #$20	                REP #$20        ; set A long
.394842		a5 1c		lda $033c	                LDA DOS_BUFF_PTR                    ; Set the BIOS BUFFER
.394844		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394846		a5 1e		lda $033e	                LDA DOS_BUFF_PTR+2
.394848		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.39484a		22 a1 47 39	jsl $3947a1	                JSL DOS_CALC_LBA                    ; Convert the cluster # to the first sector's LBA
.39484e		22 24 10 00	jsl $001024	                JSL PUTBLOCK                        ; PUT the first block of the cluster
.394852		90 09		bcc $39485d	                BCC ret_failure
.394854						ret_success
.394854		e2 20		sep #$20	                SEP #$20        ; set A short
.394856		64 0e		stz $032e	                STZ DOS_STATUS
.394858		28		plp		                PLP
.394859		2b		pld		                PLD
.39485a		ab		plb		                PLB
.39485b		38		sec		                SEC
.39485c		6b		rtl		                RTL
.39485d						ret_failure
.39485d		e2 20		sep #$20	                SEP #$20        ; set A short
.39485f		85 0e		sta $032e	                STA DOS_STATUS
.394861		28		plp		                PLP
.394862		2b		pld		                PLD
.394863		ab		plb		                PLB
.394864		18		clc		                CLC
.394865		6b		rtl		                RTL
>394866		40 46 00			DOS_FDC_NAME    .null "@F"
.394869						DOS_FDC_DESC
>394869		66 48 39 00			DEVNAME         .dword DOS_FDC_NAME            ; A pointer to the ASCIIZ name of the device
>39486d		00				DEVNUMBER       .byte BIOS_DEV_FDC           ; The BIOS_DEV number for the device
>39486e		00 00 00 00			NEXT            .dword 0            ; A pointer to the next device descriptor
>394872		40 53 00			DOS_SDC_NAME    .null "@S"
.394875						DOS_SDC_DESC
>394875		72 48 39 00			DEVNAME         .dword DOS_SDC_NAME            ; A pointer to the ASCIIZ name of the device
>394879		02				DEVNUMBER       .byte BIOS_DEV_SD           ; The BIOS_DEV number for the device
>39487a		69 48 39 00			NEXT            .dword DOS_FDC_DESC            ; A pointer to the next device descriptor
>39487e		40 48 00			DOS_HDC_NAME    .null "@H"
.394881						DOS_HD_DESC
>394881		7e 48 39 00			DEVNAME         .dword DOS_HDC_NAME            ; A pointer to the ASCIIZ name of the device
>394885		06				DEVNUMBER       .byte BIOS_DEV_HD0           ; The BIOS_DEV number for the device
>394886		75 48 39 00			NEXT            .dword DOS_SDC_DESC            ; A pointer to the next device descriptor
.39488a						DOS_PARSE_DEV
.39488a		8b		phb		                PHB
.39488b		0b		phd		                PHD
.39488c		08		php		                PHP
.39488d		48		pha		                PHA             ; begin setdbr macro
.39488e		08		php		                PHP
.39488f		e2 20		sep #$20	                SEP #$20        ; set A short
.394891		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.394893		48		pha		                PHA
.394894		ab		plb		                PLB
.394895		28		plp		                PLP
.394896		68		pla		                PLA             ; end setdbr macro
.394897		48		pha		                PHA             ; begin setdp macro
.394898		08		php		                PHP
.394899		c2 20		rep #$20	                REP #$20        ; set A long
.39489b		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39489e		5b		tcd		                TCD
.39489f		28		plp		                PLP
.3948a0		68		pla		                PLA             ; end setdp macro
.3948a1		c2 30		rep #$30	                REP #$30        ; set A&X long
.3948a3		af 4a a0 38	lda $38a04a	                LDA @l DOS_DEV_NAMES        ; Point to the first device name to check
.3948a7		85 28		sta $0348	                STA DOS_TEMP
.3948a9		af 4c a0 38	lda $38a04c	                LDA @l DOS_DEV_NAMES+2
.3948ad		85 2a		sta $034a	                STA DOS_TEMP+2
.3948af		a9 00 04	lda #$0400	                LDA #<>DOS_PATH_BUFF        ; Make DOS_STR2_PTR point to the path to check
.3948b2		85 48		sta $0368	                STA DOS_STR2_PTR
.3948b4		a9 00 00	lda #$0000	                LDA #`DOS_PATH_BUFF
.3948b7		85 4a		sta $036a	                STA DOS_STR2_PTR+2
.3948b9		a0 00 00	ldy #$0000	dev_loop        LDY #DEVICE_DESC.DEVNAME    ; Get the name of the current device into DOS_STR1_PTR
.3948bc		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
.3948be		85 44		sta $0364	                STA DOS_STR1_PTR
.3948c0		c8		iny		                INY
.3948c1		c8		iny		                INY
.3948c2		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
.3948c4		85 46		sta $0366	                STA DOS_STR1_PTR+2
.3948c6		e2 20		sep #$20	                SEP #$20        ; set A short
.3948c8		a0 00 00	ldy #$0000	                LDY #0
.3948cb		b7 44		lda [$0364],y	cmp_loop        LDA [DOS_STR1_PTR],Y        ; Get the Yth character of the device name
.3948cd		f0 24		beq $3948f3	                BEQ found                   ; If it's NULL, we found a match
.3948cf		d7 48		cmp [$0368],y	                CMP [DOS_STR2_PTR],Y        ; Compare it to the Yth character of the path
.3948d1		d0 03		bne $3948d6	                BNE next_device             ; If no match, try to load the next device
.3948d3		c8		iny		                INY                         ; Go to the next character
.3948d4		80 f5		bra $3948cb	                BRA cmp_loop
.3948d6						next_device
.3948d6		c2 20		rep #$20	                REP #$20        ; set A long
.3948d8		a0 05 00	ldy #$0005	                LDY #DEVICE_DESC.NEXT       ; DOS_TEMP := DOS_TEMP->NEXT
.3948db		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
.3948dd		48		pha		                PHA
.3948de		c8		iny		                INY
.3948df		c8		iny		                INY
.3948e0		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
.3948e2		85 2a		sta $034a	                STA DOS_TEMP+2
.3948e4		68		pla		                PLA
.3948e5		85 28		sta $0348	                STA DOS_TEMP
.3948e7		a5 28		lda $0348	                LDA DOS_TEMP                ; Is DOS_TEMP = NULL?
.3948e9		d0 ce		bne $3948b9	                BNE dev_loop                ; No: check this device
.3948eb		a5 2a		lda $034a	                LDA DOS_TEMP+2
.3948ed		d0 ca		bne $3948b9	                BNE dev_loop
.3948ef		28		plp		done            PLP                         ; Otherwise, return having not found a match
.3948f0		2b		pld		                PLD
.3948f1		ab		plb		                PLB
.3948f2		6b		rtl		                RTL
.3948f3		22 04 49 39	jsl $394904	found           JSL DOS_ADJUSTPATH          ; Remove the device name from the buffer
.3948f7		e2 20		sep #$20	                SEP #$20        ; set A short
.3948f9		a0 04 00	ldy #$0004	                LDY #DEVICE_DESC.DEVNUMBER  ; Set the BIOS device number from the found device
.3948fc		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
.3948fe		8f 21 03 00	sta $000321	                STA @l BIOS_DEV
.394902		80 eb		bra $3948ef	                BRA done
.394904						DOS_ADJUSTPATH
.394904		da		phx		                PHX
.394905		5a		phy		                PHY
.394906		8b		phb		                PHB
.394907		0b		phd		                PHD
.394908		08		php		                PHP
.394909		48		pha		                PHA             ; begin setdbr macro
.39490a		08		php		                PHP
.39490b		e2 20		sep #$20	                SEP #$20        ; set A short
.39490d		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.39490f		48		pha		                PHA
.394910		ab		plb		                PLB
.394911		28		plp		                PLP
.394912		68		pla		                PLA             ; end setdbr macro
.394913		48		pha		                PHA             ; begin setdp macro
.394914		08		php		                PHP
.394915		c2 20		rep #$20	                REP #$20        ; set A long
.394917		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39491a		5b		tcd		                TCD
.39491b		28		plp		                PLP
.39491c		68		pla		                PLA             ; end setdp macro
.39491d		c2 30		rep #$30	                REP #$30        ; set A&X long
.39491f		84 4b		sty $036b	                STY DOS_SCRATCH                 ; Save the index to later compute the size
.394921		98		tya		                TYA                             ; Compute the address of the first source byte
.394922		18		clc		                CLC
.394923		69 00 04	adc #$0400	                ADC #<>DOS_PATH_BUFF
.394926		aa		tax		                TAX
.394927		a9 00 04	lda #$0400	                LDA #<>DOS_PATH_BUFF            ; Compute the destination address for the source byte
.39492a		a8		tay		                TAY
.39492b		38		sec		                SEC                             ; Compute the number of bytes to copy
.39492c		a9 00 01	lda #$0100	                LDA #256
.39492f		e5 4b		sbc $036b	                SBC DOS_SCRATCH
.394931		54 00 00	mvn $00,$00	                MVN #`DOS_PATH_BUFF, #`DOS_PATH_BUFF
.394934		28		plp		                PLP
.394935		2b		pld		                PLD
.394936		ab		plb		                PLB
.394937		7a		ply		                PLY
.394938		fa		plx		                PLX
.394939		6b		rtl		                RTL
.39493a						DOS_PARSE_PATH
.39493a		8b		phb		                PHB
.39493b		0b		phd		                PHD
.39493c		08		php		                PHP
.39493d		48		pha		                PHA             ; begin setdbr macro
.39493e		08		php		                PHP
.39493f		e2 20		sep #$20	                SEP #$20        ; set A short
.394941		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.394943		48		pha		                PHA
.394944		ab		plb		                PLB
.394945		28		plp		                PLP
.394946		68		pla		                PLA             ; end setdbr macro
.394947		48		pha		                PHA             ; begin setdp macro
.394948		08		php		                PHP
.394949		c2 20		rep #$20	                REP #$20        ; set A long
.39494b		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39494e		5b		tcd		                TCD
.39494f		28		plp		                PLP
.394950		68		pla		                PLA             ; end setdp macro
.394951		c2 10		rep #$10	                REP #$10        ; set X long
.394953		e2 20		sep #$20	                SEP #$20        ; set A short
.394955		a2 00 00	ldx #$0000	                LDX #0
.394958		b5 e0		lda $0400,x	upcase_loop     LDA DOS_PATH_BUFF,X     ; Get the character
.39495a		f0 1b		beq $394977	                BEQ parse_dev           ; If it's NULL, the path is upper case, attempt to parse the device
.39495c		c9 20		cmp #$20	                CMP #' '                ; Is a control character?
.39495e		b0 05		bcs $394965	                BGE check_case          ; No: check the case
.394960		a9 07		lda #$07	                LDA #DOS_ERR_BADPATH    ; Yes: return a bad path error
.394962		82 64 00	brl $3949c9	                BRL ret_failure
.394965		c9 61		cmp #$61	check_case      CMP #'a'                ; Is the character lower case?
.394967		90 08		bcc $394971	                BLT next_char
.394969		c9 7b		cmp #$7b	                CMP #'z'+1
.39496b		b0 04		bcs $394971	                BGE next_char
.39496d		29 5f		and #$5f	                AND #%01011111          ; Yes: Convert to uppercase
.39496f		95 e0		sta $0400,x	                STA DOS_PATH_BUFF,X
.394971		e8		inx		next_char       INX                     ; Move to the next character
.394972		e0 00 01	cpx #$0100	                CPX #$100
.394975		d0 e1		bne $394958	                BNE upcase_loop
.394977		22 8a 48 39	jsl $39488a	parse_dev       JSL DOS_PARSE_DEV       ; Parse and extract a device specifier ":xxx:"
.39497b		a5 e0		lda $0400	                LDA DOS_PATH_BUFF       ; Check the first character of the path
.39497d		c9 3a		cmp #$3a	                CMP #':'
.39497f		d0 07		bne $394988	                BNE clr_name            ; If not colon, treat it as a file name
.394981		a0 01 00	ldy #$0001	                LDY #1                  ; Otherwise...
.394984		22 04 49 39	jsl $394904	                JSL DOS_ADJUSTPATH      ; For now, just remove the leading ":"
.394988		a0 00 00	ldy #$0000	clr_name        LDY #0                  ; Set the short name to blanks
.39498b		a9 20		lda #$20	                LDA #' '
.39498d		99 3a a0	sta $38a03a,y	clr_loop        STA DOS_SHORT_NAME,Y
.394990		c8		iny		                INY
.394991		c0 0b 00	cpy #$000b	                CPY #11
.394994		d0 f7		bne $39498d	                BNE clr_loop
.394996		a2 00 00	ldx #$0000	                LDX #0
.394999		a0 00 00	ldy #$0000	                LDY #0
.39499c		b5 e0		lda $0400,x	cpy_name_loop   LDA DOS_PATH_BUFF,X     ; Get the character of the name
.39499e		f0 20		beq $3949c0	                BEQ ret_success         ; If NULL: we've finished parsing the path
.3949a0		c9 2e		cmp #$2e	                CMP #'.'                ; If it's a dot, we've finished the name part
.3949a2		f0 0a		beq $3949ae	                BEQ cpy_ext             ; And move to the extension
.3949a4		99 3a a0	sta $38a03a,y	                STA DOS_SHORT_NAME,Y    ; Otherwise, store it to the name portion
.3949a7		e8		inx		                INX
.3949a8		c8		iny		                INY                     ; Move to the next character
.3949a9		c0 08 00	cpy #$0008	                CPY #8                  ; Have we processed 8?
.3949ac		d0 ee		bne $39499c	                BNE cpy_name_loop       ; No: process this one
.3949ae		e8		inx		cpy_ext         INX                     ; Skip the dot
.3949af		a0 08 00	ldy #$0008	                LDY #8
.3949b2		b5 e0		lda $0400,x	cpy_ext_loop    LDA DOS_PATH_BUFF,X     ; Get the character of the extension
.3949b4		f0 0a		beq $3949c0	                BEQ ret_success         ; If it's NULL, we've finished
.3949b6		99 3a a0	sta $38a03a,y	                STA DOS_SHORT_NAME,Y    ; Otherwise, copy it to the short name
.3949b9		e8		inx		                INX
.3949ba		c8		iny		                INY                     ; Move to the next character
.3949bb		c0 0b 00	cpy #$000b	                CPY #11                 ; Have we processed the three ext characters?
.3949be		d0 f2		bne $3949b2	                BNE cpy_ext_loop        ; No: process this one
.3949c0						ret_success
.3949c0		e2 20		sep #$20	                SEP #$20        ; set A short
.3949c2		64 0e		stz $032e	                STZ DOS_STATUS
.3949c4		28		plp		                PLP
.3949c5		2b		pld		                PLD
.3949c6		ab		plb		                PLB
.3949c7		38		sec		                SEC
.3949c8		6b		rtl		                RTL
.3949c9						ret_failure
.3949c9		e2 20		sep #$20	                SEP #$20        ; set A short
.3949cb		85 0e		sta $032e	                STA DOS_STATUS
.3949cd		28		plp		                PLP
.3949ce		2b		pld		                PLD
.3949cf		ab		plb		                PLB
.3949d0		18		clc		                CLC
.3949d1		6b		rtl		                RTL
.3949d2						DOS_FINDFILE
.3949d2		8b		phb		                PHB
.3949d3		0b		phd		                PHD
.3949d4		08		php		                PHP
.3949d5		48		pha		                PHA             ; begin setdbr macro
.3949d6		08		php		                PHP
.3949d7		e2 20		sep #$20	                SEP #$20        ; set A short
.3949d9		a9 00		lda #$00	                LDA #0
.3949db		48		pha		                PHA
.3949dc		ab		plb		                PLB
.3949dd		28		plp		                PLP
.3949de		68		pla		                PLA             ; end setdbr macro
.3949df		48		pha		                PHA             ; begin setdp macro
.3949e0		08		php		                PHP
.3949e1		c2 20		rep #$20	                REP #$20        ; set A long
.3949e3		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3949e6		5b		tcd		                TCD
.3949e7		28		plp		                PLP
.3949e8		68		pla		                PLA             ; end setdp macro
.3949e9		c2 30		rep #$30	                REP #$30        ; set A&X long
.3949eb		22 3a 49 39	jsl $39493a	                JSL DOS_PARSE_PATH              ; Break out the path into its components
.3949ef		b0 05		bcs $3949f6	                BCS mount                       ; If success: try to open the directory
.3949f1		28		plp		pass_failure    PLP                             ; If failure, just pass the failure back up
.3949f2		2b		pld		                PLD
.3949f3		ab		plb		                PLB
.3949f4		18		clc		                CLC
.3949f5		6b		rtl		                RTL
.3949f6		22 54 45 39	jsl $394554	mount           JSL DOS_MOUNT
.3949fa		b0 03		bcs $3949ff	                BCS get_directory
.3949fc		82 56 00	brl $394a55	                BRL ret_failure
.3949ff						get_directory
.3949ff		c2 20		rep #$20	                REP #$20        ; set A long
.394a01		22 09 42 39	jsl $394209	                JSL DOS_DIROPEN                 ; Get the directory
.394a05		b0 07		bcs $394a0e	                BCS scan_entries                ; If success: start scanning the directory entries
.394a07		e2 20		sep #$20	                SEP #$20        ; set A short
.394a09		a9 08		lda #$08	                LDA #DOS_ERR_NODIR              ; Otherwise: return a no directory error
.394a0b		82 47 00	brl $394a55	                BRL ret_failure
.394a0e		22 88 42 39	jsl $394288	scan_entries    JSL DOS_DIRFIRST                ; Move the DIR pointer to the beginning of the sector
.394a12						scan_loop
.394a12		e2 20		sep #$20	                SEP #$20        ; set A short
.394a14		a0 00 00	ldy #$0000	                LDY #0
.394a17		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y             ; Check the directory entry
.394a19		d0 05		bne $394a20	                BNE chk_unused                  ; If there's an entry, check to see if it's unused
.394a1b		a9 09		lda #$09	                LDA #DOS_ERR_NOTFOUND           ; If end-of-directory, we couldn't find a match
.394a1d		82 35 00	brl $394a55	                BRL ret_failure
.394a20		c9 e5		cmp #$e5	chk_unused      CMP #DOS_DIR_ENT_UNUSED         ; If it's unused...
.394a22		f0 26		beq $394a4a	                BEQ next_entry                  ; Go to the next entry
.394a24		a0 0b 00	ldy #$000b	                LDY #DIRENTRY.ATTRIBUTE         ; Check the entry's attributes
.394a27		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
.394a29		89 08		bit #$08	                BIT #DOS_ATTR_VOLUME            ; Is it a volume name?
.394a2b		d0 1d		bne $394a4a	                BNE next_entry                  ; Yes: skip it!
.394a2d		29 0f		and #$0f	                AND #DOS_ATTR_LONGNAME
.394a2f		c9 0f		cmp #$0f	                CMP #DOS_ATTR_LONGNAME          ; Is it a long name field?
.394a31		f0 17		beq $394a4a	                BEQ next_entry                  ; Yes: skip it!
.394a33		a2 00 00	ldx #$0000	                LDX #0
.394a36		a0 00 00	ldy #$0000	                LDY #DIRENTRY.SHORTNAME
.394a39		b7 18		lda [$0338],y	scan_cmp_loop   LDA [DOS_DIR_PTR],Y             ; Get the X'th character of the entry
.394a3b		df 3a a0 38	cmp $38a03a,x	                CMP DOS_SHORT_NAME,X            ; And compare to the X'th character of the name we want
.394a3f		d0 09		bne $394a4a	                BNE next_entry                  ; If not equal: try the next entry
.394a41		c8		iny		                INY                             ; Advance to the next character
.394a42		e8		inx		                INX
.394a43		e0 0b 00	cpx #$000b	                CPX #11                         ; Did we reach the end of the names?
.394a46		f0 16		beq $394a5e	                BEQ match                       ; Yes: we have a match!
.394a48		80 ef		bra $394a39	                BRA scan_cmp_loop               ; No: keep checking
.394a4a		22 a3 42 39	jsl $3942a3	next_entry      JSL DOS_DIRNEXT                 ; Try to get the next directory entry
.394a4e		90 05		bcc $394a55	                BCC ret_failure                 ; If we're at the end of the directory, return a failure.
.394a50		82 bf ff	brl $394a12	                BRL scan_loop                   ; If found: keep scanning
.394a53		a9 08		lda #$08	bad_dir         LDA #DOS_ERR_NODIR              ; Otherwise: fail with a NODIR error (maybe something else is better)
.394a55						ret_failure
.394a55		e2 20		sep #$20	                SEP #$20        ; set A short
.394a57		85 0e		sta $032e	                STA DOS_STATUS
.394a59		28		plp		                PLP
.394a5a		2b		pld		                PLD
.394a5b		ab		plb		                PLB
.394a5c		18		clc		                CLC
.394a5d		6b		rtl		                RTL
.394a5e						match
.394a5e		c2 20		rep #$20	                REP #$20        ; set A long
.394a60		a0 1a 00	ldy #$001a	                LDY #DIRENTRY.CLUSTER_L         ; Copy the cluster number from the directory entry
.394a63		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
.394a65		85 10		sta $0330	                STA DOS_CLUS_ID                 ; To DOS_CLUS_ID
.394a67		a0 14 00	ldy #$0014	                LDY #DIRENTRY.CLUSTER_H
.394a6a		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
.394a6c		85 12		sta $0332	                STA DOS_CLUS_ID+2
.394a6e						ret_success
.394a6e		e2 20		sep #$20	                SEP #$20        ; set A short
.394a70		64 0e		stz $032e	                STZ DOS_STATUS
.394a72		28		plp		                PLP
.394a73		2b		pld		                PLD
.394a74		ab		plb		                PLB
.394a75		38		sec		                SEC
.394a76		6b		rtl		                RTL
.394a77						DOS_READFILE
.394a77		8b		phb		                PHB
.394a78		0b		phd		                PHD
.394a79		08		php		                PHP
.394a7a		48		pha		                PHA             ; begin setdbr macro
.394a7b		08		php		                PHP
.394a7c		e2 20		sep #$20	                SEP #$20        ; set A short
.394a7e		a9 00		lda #$00	                LDA #0
.394a80		48		pha		                PHA
.394a81		ab		plb		                PLB
.394a82		28		plp		                PLP
.394a83		68		pla		                PLA             ; end setdbr macro
.394a84		48		pha		                PHA             ; begin setdp macro
.394a85		08		php		                PHP
.394a86		c2 20		rep #$20	                REP #$20        ; set A long
.394a88		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394a8b		5b		tcd		                TCD
.394a8c		28		plp		                PLP
.394a8d		68		pla		                PLA             ; end setdp macro
.394a8e		c2 30		rep #$30	                REP #$30        ; set A&X long
.394a90		a5 1e		lda $033e	                LDA DOS_BUFF_PTR+2
.394a92		48		pha		                PHA
.394a93		a5 1c		lda $033c	                LDA DOS_BUFF_PTR
.394a95		48		pha		                PHA
.394a96		22 d2 49 39	jsl $3949d2	                JSL DOS_FINDFILE                    ; Attempt to find the file's directory entry
.394a9a		68		pla		                PLA
.394a9b		85 1c		sta $033c	                STA DOS_BUFF_PTR
.394a9d		68		pla		                PLA
.394a9e		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
.394aa0		90 0f		bcc $394ab1	                BCC pass_failure                    ; If found: try to load the cluster
.394aa2		22 ec 47 39	jsl $3947ec	load_cluster    JSL DOS_GETCLUSTER                  ; Get the first block of the cluster
.394aa6		90 09		bcc $394ab1	                BCC pass_failure                    ; If there's an error... pass it up the chain
.394aa8						ret_success
.394aa8		e2 20		sep #$20	                SEP #$20        ; set A short
.394aaa		64 0e		stz $032e	                STZ DOS_STATUS
.394aac		28		plp		                PLP
.394aad		2b		pld		                PLD
.394aae		ab		plb		                PLB
.394aaf		38		sec		                SEC
.394ab0		6b		rtl		                RTL
.394ab1		28		plp		pass_failure    PLP                                 ; Otherwise: pass any error up the chain
.394ab2		2b		pld		                PLD
.394ab3		ab		plb		                PLB
.394ab4		18		clc		                CLC
.394ab5		6b		rtl		                RTL
.394ab6						ENTRYFORCLUS12
.394ab6		8b		phb		                PHB
.394ab7		0b		phd		                PHD
.394ab8		08		php		                PHP
.394ab9		48		pha		                PHA             ; begin setdbr macro
.394aba		08		php		                PHP
.394abb		e2 20		sep #$20	                SEP #$20        ; set A short
.394abd		a9 00		lda #$00	                LDA #0
.394abf		48		pha		                PHA
.394ac0		ab		plb		                PLB
.394ac1		28		plp		                PLP
.394ac2		68		pla		                PLA             ; end setdbr macro
.394ac3		48		pha		                PHA             ; begin setdp macro
.394ac4		08		php		                PHP
.394ac5		c2 20		rep #$20	                REP #$20        ; set A long
.394ac7		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394aca		5b		tcd		                TCD
.394acb		28		plp		                PLP
.394acc		68		pla		                PLA             ; end setdp macro
.394acd		c2 30		rep #$30	                REP #$30        ; set A&X long
.394acf		a5 10		lda $0330	                LDA DOS_CLUS_ID                 ; DOS_TEMP := DOS_CLUS_ID * 3
.394ad1		0a		asl a		                ASL A
.394ad2		85 28		sta $0348	                STA DOS_TEMP
.394ad4		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.394ad6		2a		rol a		                ROL A
.394ad7		85 2a		sta $034a	                STA DOS_TEMP+2
.394ad9		18		clc		                CLC
.394ada		a5 10		lda $0330	                LDA DOS_CLUS_ID
.394adc		65 28		adc $0348	                ADC DOS_TEMP
.394ade		85 28		sta $0348	                STA DOS_TEMP
.394ae0		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.394ae2		65 2a		adc $034a	                ADC DOS_TEMP+2
.394ae4		85 2a		sta $034a	                STA DOS_TEMP+2
.394ae6		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := (DOS_CLUS_ID * 3) / 2
.394ae8		66 28		ror $0348	                ROR DOS_TEMP                    ; DOS_TEMP is now the offset to the cluster's entry in the FAT
.394aea		a5 28		lda $0348	                LDA DOS_TEMP                    ; X should be the offset within the FAT buffer
.394aec		29 ff 03	and #$03ff	                AND #$003FF
.394aef		aa		tax		                TAX
.394af0		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
.394af2		66 28		ror $0348	                ROR DOS_TEMP
.394af4		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
.394af6		66 28		ror $0348	                ROR DOS_TEMP
.394af8		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
.394afa		66 28		ror $0348	                ROR DOS_TEMP
.394afc		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
.394afe		66 28		ror $0348	                ROR DOS_TEMP
.394b00		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
.394b02		66 28		ror $0348	                ROR DOS_TEMP
.394b04		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
.394b06		66 28		ror $0348	                ROR DOS_TEMP
.394b08		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
.394b0a		66 28		ror $0348	                ROR DOS_TEMP
.394b0c		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
.394b0e		66 28		ror $0348	                ROR DOS_TEMP
.394b10		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
.394b12		66 28		ror $0348	                ROR DOS_TEMP
.394b14		18		clc		                CLC                             ; DOS_FAT_LBA should be the LBA of the first FAT sector we need
.394b15		af 14 a0 38	lda $38a014	                LDA FAT_BEGIN_LBA
.394b19		65 28		adc $0348	                ADC DOS_TEMP
.394b1b		85 24		sta $0344	                STA DOS_FAT_LBA
.394b1d		af 16 a0 38	lda $38a016	                LDA FAT_BEGIN_LBA+2
.394b21		65 2a		adc $034a	                ADC DOS_TEMP+2
.394b23		85 26		sta $0346	                STA DOS_FAT_LBA+2
.394b25		28		plp		                PLP
.394b26		2b		pld		                PLD
.394b27		ab		plb		                PLB
.394b28		6b		rtl		                RTL
.394b29						FATFORCLUSTER12
.394b29		8b		phb		                PHB
.394b2a		0b		phd		                PHD
.394b2b		08		php		                PHP
.394b2c		48		pha		                PHA             ; begin setdbr macro
.394b2d		08		php		                PHP
.394b2e		e2 20		sep #$20	                SEP #$20        ; set A short
.394b30		a9 00		lda #$00	                LDA #0
.394b32		48		pha		                PHA
.394b33		ab		plb		                PLB
.394b34		28		plp		                PLP
.394b35		68		pla		                PLA             ; end setdbr macro
.394b36		48		pha		                PHA             ; begin setdp macro
.394b37		08		php		                PHP
.394b38		c2 20		rep #$20	                REP #$20        ; set A long
.394b3a		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394b3d		5b		tcd		                TCD
.394b3e		28		plp		                PLP
.394b3f		68		pla		                PLA             ; end setdp macro
.394b40		c2 30		rep #$30	                REP #$30        ; set A&X long
.394b42		a2 00 00	ldx #$0000	                LDX #0
.394b45		a9 5a 5a	lda #$5a5a	                LDA #$5A5A
.394b48		8f 00 a5 38	sta $38a500	clr_loop        STA DOS_FAT_SECTORS
.394b4c		e8		inx		                INX
.394b4d		e8		inx		                INX
.394b4e		e0 00 04	cpx #$0400	                CPX #1024
.394b51		d0 f5		bne $394b48	                BNE clr_loop
.394b53		22 b6 4a 39	jsl $394ab6	                JSL ENTRYFORCLUS12              ; Calculate the LBA
.394b57		a5 24		lda $0344	                LDA DOS_FAT_LBA                 ; Point to the desired sector in the FAT
.394b59		85 02		sta $0322	                STA BIOS_LBA
.394b5b		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
.394b5d		85 04		sta $0324	                STA BIOS_LBA+2
.394b5f		a9 00 a5	lda #$a500	                LDA #<>DOS_FAT_SECTORS          ; Point to the first 512 bytes of the FAT buffer
.394b62		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394b64		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
.394b67		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.394b69		22 44 10 00	jsl $001044	                JSL GETBLOCK                    ; Attempt to load the first FAT sector
.394b6d		90 17		bcc $394b86	                BCC error
.394b6f		e6 02		inc $0322	                INC BIOS_LBA                    ; Move to the next sector
.394b71		a9 00 a7	lda #$a700	                LDA #<>DOS_FAT_SECTORS+512      ; And point to the second 512 bytes of teh FAT buffer
.394b74		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394b76		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
.394b79		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.394b7b		22 44 10 00	jsl $001044	                JSL GETBLOCK                    ; Attempt to load the first FAT sector
.394b7f		90 05		bcc $394b86	                BCC error
.394b81		28		plp		                PLP
.394b82		2b		pld		                PLD
.394b83		ab		plb		                PLB
.394b84		38		sec		                SEC
.394b85		6b		rtl		                RTL
.394b86						error
.394b86		e2 20		sep #$20	                SEP #$20        ; set A short
.394b88		a9 06		lda #$06	                LDA #DOS_ERR_FAT
.394b8a		85 0e		sta $032e	                STA DOS_STATUS
.394b8c		28		plp		                PLP
.394b8d		2b		pld		                PLD
.394b8e		ab		plb		                PLB
.394b8f		18		clc		                CLC
.394b90		6b		rtl		                RTL
.394b91						FATFORCLUSTER32
.394b91		8b		phb		                PHB
.394b92		0b		phd		                PHD
.394b93		48		pha		                PHA             ; begin setdbr macro
.394b94		08		php		                PHP
.394b95		e2 20		sep #$20	                SEP #$20        ; set A short
.394b97		a9 00		lda #$00	                LDA #0
.394b99		48		pha		                PHA
.394b9a		ab		plb		                PLB
.394b9b		28		plp		                PLP
.394b9c		68		pla		                PLA             ; end setdbr macro
.394b9d		48		pha		                PHA             ; begin setdp macro
.394b9e		08		php		                PHP
.394b9f		c2 20		rep #$20	                REP #$20        ; set A long
.394ba1		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394ba4		5b		tcd		                TCD
.394ba5		28		plp		                PLP
.394ba6		68		pla		                PLA             ; end setdp macro
.394ba7		c2 30		rep #$30	                REP #$30        ; set A&X long
.394ba9		a5 10		lda $0330	                LDA DOS_CLUS_ID
.394bab		85 24		sta $0344	                STA DOS_FAT_LBA
.394bad		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.394baf		85 26		sta $0346	                STA DOS_FAT_LBA+2
.394bb1		a2 07 00	ldx #$0007	                LDX #7
.394bb4		46 26		lsr $0346	div_loop        LSR DOS_FAT_LBA+2
.394bb6		66 24		ror $0344	                ROR DOS_FAT_LBA
.394bb8		ca		dex		                DEX
.394bb9		d0 f9		bne $394bb4	                BNE div_loop
.394bbb		18		clc		                CLC
.394bbc		a5 24		lda $0344	                LDA DOS_FAT_LBA
.394bbe		6f 14 a0 38	adc $38a014	                ADC FAT_BEGIN_LBA
.394bc2		85 24		sta $0344	                STA DOS_FAT_LBA
.394bc4		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
.394bc6		6f 16 a0 38	adc $38a016	                ADC FAT_BEGIN_LBA+2
.394bca		85 26		sta $0346	                STA DOS_FAT_LBA+2
.394bcc		a5 24		lda $0344	                LDA DOS_FAT_LBA                 ; We want to load the FAT sector
.394bce		85 02		sta $0322	                STA BIOS_LBA
.394bd0		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
.394bd2		85 04		sta $0324	                STA BIOS_LBA+2
.394bd4		a9 00 a5	lda #$a500	                LDA #<>DOS_FAT_SECTORS          ; We want to load the FAT sector in DOS_FAT_SECTORS
.394bd7		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394bd9		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
.394bdc		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.394bde		22 44 10 00	jsl $001044	                JSL GETBLOCK                    ; Load the FAT entry
.394be2		b0 06		bcs $394bea	                BCS find_entry
.394be4		e2 20		sep #$20	                SEP #$20        ; set A short
.394be6		a9 06		lda #$06	                LDA #DOS_ERR_FAT
.394be8		80 0e		bra $394bf8	                BRA ret_failure
.394bea						find_entry
.394bea		c2 20		rep #$20	                REP #$20        ; set A long
.394bec		a5 10		lda $0330	                LDA DOS_CLUS_ID
.394bee		0a		asl a		                ASL A
.394bef		0a		asl a		                ASL A                           ; * 4
.394bf0		29 ff 01	and #$01ff	                AND #$1FF                       ; DOS_CLUS_ID MOD 512
.394bf3		aa		tax		                TAX                             ; X should be the offset within the sector
.394bf4		2b		pld		ret_success     PLD
.394bf5		ab		plb		                PLB
.394bf6		38		sec		                SEC                             ; return success
.394bf7		6b		rtl		                RTL
.394bf8		2b		pld		ret_failure     PLD
.394bf9		ab		plb		                PLB
.394bfa		18		clc		                CLC                             ; Return failure
.394bfb		6b		rtl		                RTL
.394bfc						NEXTCLUSTER
.394bfc		08		php		                PHP
.394bfd		e2 20		sep #$20	                SEP #$20        ; set A short
.394bff		af 01 a0 38	lda $38a001	                LDA @l FILE_SYSTEM              ; Get the file system code
.394c03		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12            ; Is it FAT12?
.394c05		d0 08		bne $394c0f	                BNE fat32                       ; No: assume it's FAT32
.394c07		22 1d 4c 39	jsl $394c1d	fat12           JSL NEXTCLUSTER12               ; Lookup the next cluster from FAT12
.394c0b		90 0d		bcc $394c1a	                BCC pass_failure                ; If there was an error, pass it up the chain
.394c0d		80 06		bra $394c15	                BRA ret_success
.394c0f		22 85 4c 39	jsl $394c85	fat32           JSL NEXTCLUSTER32               ; Lookup the next cluster from FAT32
.394c13		90 05		bcc $394c1a	                BCC pass_failure                ; If there was an error, pass it up the chain
.394c15		64 0e		stz $032e	ret_success     STZ DOS_STATUS
.394c17		28		plp		                PLP
.394c18		38		sec		                SEC
.394c19		6b		rtl		                RTL
.394c1a		28		plp		pass_failure    PLP
.394c1b		18		clc		                CLC
.394c1c		6b		rtl		                RTL
.394c1d						NEXTCLUSTER12
.394c1d		8b		phb		                    PHB
.394c1e		0b		phd		                    PHD
.394c1f		08		php		                    PHP
.394c20		48		pha		                PHA             ; begin setdbr macro
.394c21		08		php		                PHP
.394c22		e2 20		sep #$20	                SEP #$20        ; set A short
.394c24		a9 00		lda #$00	                LDA #0
.394c26		48		pha		                PHA
.394c27		ab		plb		                PLB
.394c28		28		plp		                PLP
.394c29		68		pla		                PLA             ; end setdbr macro
.394c2a		48		pha		                PHA             ; begin setdp macro
.394c2b		08		php		                PHP
.394c2c		c2 20		rep #$20	                REP #$20        ; set A long
.394c2e		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394c31		5b		tcd		                TCD
.394c32		28		plp		                PLP
.394c33		68		pla		                PLA             ; end setdp macro
.394c34		c2 30		rep #$30	                REP #$30        ; set A&X long
.394c36		22 29 4b 39	jsl $394b29	                    JSL FATFORCLUSTER12             ; Attempt to load the FAT entries
.394c3a		b0 03		bcs $394c3f	                    BCS chk_clus_id
.394c3c		82 41 00	brl $394c80	                    BRL pass_failure
.394c3f		a5 10		lda $0330	chk_clus_id         LDA DOS_CLUS_ID                 ; Check the cluster ID...
.394c41		89 01 00	bit #$0001	                    BIT #1                          ; Is it odd?
.394c44		d0 0d		bne $394c53	                    BNE is_odd                      ; Yes: calculate the next cluster for odd
.394c46						is_even
.394c46		c2 20		rep #$20	                REP #$20        ; set A long
.394c48		bf 00 a5 38	lda $38a500,x	                    LDA DOS_FAT_SECTORS,X           ; DOS_CLUS_ID := DOS_FAT_SECTORS[X] & $0FFF
.394c4c		29 ff 0f	and #$0fff	                    AND #$0FFF
.394c4f		85 28		sta $0348	                    STA DOS_TEMP
.394c51		80 0c		bra $394c5f	                    BRA check_id
.394c53						is_odd
.394c53		c2 20		rep #$20	                REP #$20        ; set A long
.394c55		bf 00 a5 38	lda $38a500,x	                    LDA DOS_FAT_SECTORS,X           ; DOS_CLUS_ID := DOS_FAT_SECTORS[X] >> 4
.394c59		4a		lsr a		                    LSR A
.394c5a		4a		lsr a		                    LSR A
.394c5b		4a		lsr a		                    LSR A
.394c5c		4a		lsr a		                    LSR A
.394c5d		85 28		sta $0348	                    STA DOS_TEMP
.394c5f						check_id
.394c5f		c2 20		rep #$20	                REP #$20        ; set A long
.394c61		a5 28		lda $0348	                    LDA DOS_TEMP                    ; Check the new cluster ID we got
.394c63		29 f0 0f	and #$0ff0	                    AND #$0FF0                      ; Is it in the range $0FF0 -- $0FFF?
.394c66		c9 f0 0f	cmp #$0ff0	                    CMP #$0FF0
.394c69		f0 0f		beq $394c7a	                    BEQ no_more                     ; Yes: return that we've reached the end of the chain
.394c6b		a5 28		lda $0348	                    LDA DOS_TEMP                    ; Restore the "current" cluster ID
.394c6d		85 10		sta $0330	                    STA DOS_CLUS_ID
.394c6f		64 12		stz $0332	                    STZ DOS_CLUS_ID+2
.394c71						ret_success
.394c71		e2 20		sep #$20	                SEP #$20        ; set A short
.394c73		64 0e		stz $032e	                    STZ DOS_STATUS
.394c75		28		plp		                    PLP
.394c76		2b		pld		                    PLD
.394c77		ab		plb		                    PLB
.394c78		38		sec		                    SEC
.394c79		6b		rtl		                    RTL
.394c7a						no_more
.394c7a		e2 20		sep #$20	                SEP #$20        ; set A short
.394c7c		a9 0a		lda #$0a	                    LDA #DOS_ERR_NOCLUSTER
.394c7e		85 0e		sta $032e	                    STA DOS_STATUS
.394c80		28		plp		pass_failure        PLP
.394c81		2b		pld		                    PLD
.394c82		ab		plb		                    PLB
.394c83		18		clc		                    CLC
.394c84		6b		rtl		                    RTL
.394c85						NEXTCLUSTER32
.394c85		8b		phb		                PHB
.394c86		0b		phd		                PHD
.394c87		08		php		                PHP
.394c88		48		pha		                PHA             ; begin setdbr macro
.394c89		08		php		                PHP
.394c8a		e2 20		sep #$20	                SEP #$20        ; set A short
.394c8c		a9 00		lda #$00	                LDA #0
.394c8e		48		pha		                PHA
.394c8f		ab		plb		                PLB
.394c90		28		plp		                PLP
.394c91		68		pla		                PLA             ; end setdbr macro
.394c92		48		pha		                PHA             ; begin setdp macro
.394c93		08		php		                PHP
.394c94		c2 20		rep #$20	                REP #$20        ; set A long
.394c96		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394c99		5b		tcd		                TCD
.394c9a		28		plp		                PLP
.394c9b		68		pla		                PLA             ; end setdp macro
.394c9c		c2 30		rep #$30	                REP #$30        ; set A&X long
.394c9e		22 91 4b 39	jsl $394b91	                JSL FATFORCLUSTER32             ; Get the FAT entry for this cluster
.394ca2		90 53		bcc $394cf7	                BCC ret_failure                 ; If it did not work, return the error
.394ca4		e2 20		sep #$20	                SEP #$20        ; set A short
.394ca6		bf 00 a5 38	lda $38a500,x	                LDA @l DOS_FAT_SECTORS,X        ; Get the entry and copy it to DOS_TEMP
.394caa		85 28		sta $0348	                STA DOS_TEMP
.394cac		bf 01 a5 38	lda $38a501,x	                LDA @l DOS_FAT_SECTORS+1,X
.394cb0		85 29		sta $0349	                STA DOS_TEMP+1
.394cb2		bf 02 a5 38	lda $38a502,x	                LDA @l DOS_FAT_SECTORS+2,X
.394cb6		85 2a		sta $034a	                STA DOS_TEMP+2
.394cb8		bf 03 a5 38	lda $38a503,x	                LDA @l DOS_FAT_SECTORS+3,X
.394cbc		85 2b		sta $034b	                STA DOS_TEMP+3
.394cbe		a5 28		lda $0348	xxxx            LDA DOS_TEMP                    ; Is DOS_TEMP = $FFFFFFFF?
.394cc0		c9 ff		cmp #$ff	                CMP #$FF
.394cc2		d0 18		bne $394cdc	                BNE found_next
.394cc4		a5 29		lda $0349	                LDA DOS_TEMP+1
.394cc6		c9 ff		cmp #$ff	                CMP #$FF
.394cc8		d0 12		bne $394cdc	                BNE found_next
.394cca		a5 2a		lda $034a	                LDA DOS_TEMP+2
.394ccc		c9 ff		cmp #$ff	                CMP #$FF
.394cce		d0 0c		bne $394cdc	                BNE found_next
.394cd0		a5 2b		lda $034b	                LDA DOS_TEMP+3
.394cd2		c9 0f		cmp #$0f	                CMP #$0F
.394cd4		d0 06		bne $394cdc	                BNE found_next                  ; No: return this cluster as the next
.394cd6		e2 20		sep #$20	                SEP #$20        ; set A short
.394cd8		a9 0a		lda #$0a	                LDA #DOS_ERR_NOCLUSTER          ; Yes: return that there are no more clusters
.394cda		80 1b		bra $394cf7	                BRA ret_failure
.394cdc						found_next
.394cdc		e2 20		sep #$20	                SEP #$20        ; set A short
.394cde		a5 28		lda $0348	                LDA DOS_TEMP                    ; No: return DOS_TEMP as the new DOS_CLUS_ID
.394ce0		85 10		sta $0330	                STA DOS_CLUS_ID
.394ce2		a5 29		lda $0349	                LDA DOS_TEMP+1
.394ce4		85 11		sta $0331	                STA DOS_CLUS_ID+1
.394ce6		a5 2a		lda $034a	                LDA DOS_TEMP+2
.394ce8		85 12		sta $0332	                STA DOS_CLUS_ID+2
.394cea		a5 2b		lda $034b	                LDA DOS_TEMP+3
.394cec		85 13		sta $0333	                STA DOS_CLUS_ID+3
.394cee						ret_success
.394cee		e2 20		sep #$20	                SEP #$20        ; set A short
.394cf0		64 0e		stz $032e	                STZ DOS_STATUS                  ; Record success
.394cf2		28		plp		                PLP
.394cf3		2b		pld		                PLD
.394cf4		ab		plb		                PLB
.394cf5		38		sec		                SEC
.394cf6		6b		rtl		                RTL
.394cf7						ret_failure
.394cf7		e2 20		sep #$20	                SEP #$20        ; set A short
.394cf9		85 0e		sta $032e	                STA DOS_STATUS                  ; Record the error condition
.394cfb		28		plp		                PLP
.394cfc		2b		pld		                PLD
.394cfd		ab		plb		                PLB
.394cfe		18		clc		                CLC
.394cff		6b		rtl		                RTL
.394d00						DOS_READNEXT
.394d00		08		php		                PHP
.394d01		c2 30		rep #$30	                REP #$30        ; set A&X long
.394d03		22 fc 4b 39	jsl $394bfc	                JSL NEXTCLUSTER                 ; Attempt to find the next cluster in the FAT
.394d07		90 09		bcc $394d12	                BCC pass_failure                ; If nothing found: pass the failure up the chain
.394d09		22 ec 47 39	jsl $3947ec	                JSL DOS_GETCLUSTER              ; Otherwise: attempt to read the cluster
.394d0d		90 03		bcc $394d12	                BCC pass_failure                ; If nothing read: pass the failure up the chain
.394d0f		28		plp		ret_success     PLP
.394d10		38		sec		                SEC
.394d11		6b		rtl		                RTL
.394d12		28		plp		pass_failure    PLP
.394d13		18		clc		                CLC
.394d14		6b		rtl		                RTL
.394d15						DOS_FREECLUS
.394d15		08		php		                PHP
.394d16		48		pha		                PHA             ; begin setdp macro
.394d17		08		php		                PHP
.394d18		c2 20		rep #$20	                REP #$20        ; set A long
.394d1a		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394d1d		5b		tcd		                TCD
.394d1e		28		plp		                PLP
.394d1f		68		pla		                PLA             ; end setdp macro
.394d20		e2 20		sep #$20	                SEP #$20        ; set A short
.394d22		af 01 a0 38	lda $38a001	                LDA @l FILE_SYSTEM              ; Get the file system code
.394d26		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12            ; Is it FAT12?
.394d28		d0 08		bne $394d32	                BNE fat32                       ; No: assume it's FAT32
.394d2a		22 a6 4d 39	jsl $394da6	fat12           JSL DOS_FREECLUS12              ; Find the next free cluster from FAT12
.394d2e		90 0d		bcc $394d3d	                BCC pass_failure                ; If there was an error, pass it up the chain
.394d30		80 06		bra $394d38	                BRA ret_success
.394d32		22 7e 4e 39	jsl $394e7e	fat32           JSL DOS_FREECLUS32              ; Find the next free cluster from FAT32
.394d36		90 05		bcc $394d3d	                BCC pass_failure                ; If there was an error, pass it up the chain
.394d38		64 0e		stz $032e	ret_success     STZ DOS_STATUS
.394d3a		28		plp		                PLP
.394d3b		38		sec		                SEC
.394d3c		6b		rtl		                RTL
.394d3d		28		plp		pass_failure    PLP
.394d3e		18		clc		                CLC
.394d3f		6b		rtl		                RTL
.394d40						FDC_READ2FAT12
.394d40		8b		phb		                    PHB
.394d41		0b		phd		                    PHD
.394d42		08		php		                    PHP
.394d43		48		pha		                PHA             ; begin setdbr macro
.394d44		08		php		                PHP
.394d45		e2 20		sep #$20	                SEP #$20        ; set A short
.394d47		a9 00		lda #$00	                LDA #0
.394d49		48		pha		                PHA
.394d4a		ab		plb		                PLB
.394d4b		28		plp		                PLP
.394d4c		68		pla		                PLA             ; end setdbr macro
.394d4d		48		pha		                PHA             ; begin setdp macro
.394d4e		08		php		                PHP
.394d4f		c2 20		rep #$20	                REP #$20        ; set A long
.394d51		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394d54		5b		tcd		                TCD
.394d55		28		plp		                PLP
.394d56		68		pla		                PLA             ; end setdp macro
.394d57		c2 30		rep #$30	                REP #$30        ; set A&X long
.394d59		a9 00 a5	lda #$a500	                    LDA #<>DOS_FAT_SECTORS          ; Set the location to store the sector
.394d5c		85 06		sta $0326	                    STA BIOS_BUFF_PTR
.394d5e		a9 38 00	lda #$0038	                    LDA #`DOS_FAT_SECTORS
.394d61		85 08		sta $0328	                    STA BIOS_BUFF_PTR+2
.394d63		a5 24		lda $0344	                    LDA DOS_FAT_LBA
.394d65		85 02		sta $0322	                    STA BIOS_LBA
.394d67		a5 26		lda $0346	                    LDA DOS_FAT_LBA+2
.394d69		85 04		sta $0324	                    STA BIOS_LBA+2
.394d6b		22 44 10 00	jsl $001044	                    JSL GETBLOCK                    ; Read the first sector
.394d6f		b0 07		bcs $394d78	                    BCS inc_sect2                   ; If success: start getting the second sector
.394d71		e2 20		sep #$20	                SEP #$20        ; set A short
.394d73		a9 06		lda #$06	                    LDA #DOS_ERR_FAT
.394d75		82 1c 00	brl $394d94	                    BRL ret_failure
.394d78						inc_sect2
.394d78		c2 20		rep #$20	                REP #$20        ; set A long
.394d7a		e6 02		inc $0322	                    INC BIOS_LBA                    ; Move to the next sector
.394d7c		d0 02		bne $394d80	                    BNE inc_buff_ptr
.394d7e		e6 04		inc $0324	                    INC BIOS_LBA+2
.394d80		a9 00 a7	lda #$a700	inc_buff_ptr        LDA #<>(DOS_FAT_SECTORS+DOS_SECTOR_SIZE)
.394d83		85 06		sta $0326	                    STA BIOS_BUFF_PTR
.394d85		a9 38 00	lda #$0038	                    LDA #`(DOS_FAT_SECTORS+DOS_SECTOR_SIZE)
.394d88		85 08		sta $0328	                    STA BIOS_BUFF_PTR+2
.394d8a		22 44 10 00	jsl $001044	                    JSL GETBLOCK                    ; Read the second sector
.394d8e		b0 0d		bcs $394d9d	                    BCS ret_success                 ; If success, return success
.394d90		e2 20		sep #$20	                SEP #$20        ; set A short
.394d92		a9 06		lda #$06	                    LDA #DOS_ERR_FAT
.394d94						ret_failure
.394d94		e2 20		sep #$20	                SEP #$20        ; set A short
.394d96		85 00		sta $0320	                    STA BIOS_STATUS
.394d98		28		plp		                    PLP
.394d99		2b		pld		                    PLD
.394d9a		ab		plb		                    PLB
.394d9b		18		clc		                    CLC
.394d9c		6b		rtl		                    RTL
.394d9d						ret_success
.394d9d		e2 20		sep #$20	                SEP #$20        ; set A short
.394d9f		64 00		stz $0320	                    STZ BIOS_STATUS
.394da1		28		plp		                    PLP
.394da2		2b		pld		                    PLD
.394da3		ab		plb		                    PLB
.394da4		38		sec		                    SEC
.394da5		6b		rtl		                    RTL
.394da6						DOS_FREECLUS12
.394da6		da		phx		                PHX
.394da7		8b		phb		                PHB
.394da8		0b		phd		                PHD
.394da9		08		php		                PHP
.394daa		48		pha		                PHA             ; begin setdbr macro
.394dab		08		php		                PHP
.394dac		e2 20		sep #$20	                SEP #$20        ; set A short
.394dae		a9 00		lda #$00	                LDA #0
.394db0		48		pha		                PHA
.394db1		ab		plb		                PLB
.394db2		28		plp		                PLP
.394db3		68		pla		                PLA             ; end setdbr macro
.394db4		48		pha		                PHA             ; begin setdp macro
.394db5		08		php		                PHP
.394db6		c2 20		rep #$20	                REP #$20        ; set A long
.394db8		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394dbb		5b		tcd		                TCD
.394dbc		28		plp		                PLP
.394dbd		68		pla		                PLA             ; end setdp macro
.394dbe		c2 30		rep #$30	                REP #$30        ; set A&X long
.394dc0		a9 02 00	lda #$0002	                LDA #2                          ; Cluster ID is 2 to start with
.394dc3		85 10		sta $0330	                STA DOS_CLUS_ID
.394dc5		a9 00 00	lda #$0000	                LDA #0
.394dc8		85 12		sta $0332	                STA DOS_CLUS_ID+2
.394dca		22 b6 4a 39	jsl $394ab6	                JSL ENTRYFORCLUS12              ; Calculate the LBA and buffer offset for the cluster
.394dce		22 40 4d 39	jsl $394d40	                JSL FDC_READ2FAT12              ; Read the first two sectors of the FAT
.394dd2		b0 07		bcs $394ddb	                BCS start_of_fat                ; If success, move X to the start of the FAT
.394dd4		e2 20		sep #$20	                SEP #$20        ; set A short
.394dd6		a9 06		lda #$06	                LDA #DOS_ERR_FAT
.394dd8		82 99 00	brl $394e74	                BRL ret_failure
.394ddb						start_of_fat
.394ddb		c2 30		rep #$30	                REP #$30        ; set A&X long
.394ddd		a5 10		lda $0330	chk_cluster     LDA DOS_CLUS_ID                 ; Check to see if cluster number is even or odd
.394ddf		89 01 00	bit #$0001	                BIT #1
.394de2		d0 09		bne $394ded	                BNE is_odd
.394de4		bf 00 a5 38	lda $38a500,x	is_even         LDA DOS_FAT_SECTORS,X           ; Get the cluster status for an even numbered cluster
.394de8		29 ff 0f	and #$0fff	                AND #$0FFF
.394deb		80 08		bra $394df5	                BRA chk_available
.394ded		bf 00 a5 38	lda $38a500,x	is_odd          LDA DOS_FAT_SECTORS,X           ; Get the cluster status for an odd numbered cluster
.394df1		4a		lsr a		                LSR A
.394df2		4a		lsr a		                LSR A
.394df3		4a		lsr a		                LSR A
.394df4		4a		lsr a		                LSR A
.394df5						chk_available
.394df5		85 28		sta $0348	                STA DOS_TEMP
.394df7		c9 00 00	cmp #$0000	                CMP #0                          ; Is it available?
.394dfa		f0 03		beq $394dff	                BEQ chk_found
.394dfc		82 39 00	brl $394e38	                BRL next_cluster                ; No: advance to the next cluster
.394dff		8a		txa		chk_found       TXA
.394e00		85 2a		sta $034a	                STA DOS_TEMP+2
.394e02		a5 10		lda $0330	                LDA DOS_CLUS_ID                 ; Check to see if cluster number is even or odd
.394e04		89 01 00	bit #$0001	                BIT #1
.394e07		d0 0d		bne $394e16	                BNE is_odd2
.394e09						is_even2
.394e09		bf 00 a5 38	lda $38a500,x	                LDA DOS_FAT_SECTORS,X           ; Reserve the cluster in the FAT, even offset case
.394e0d		09 ff 0f	ora #$0fff	                ORA #$0FFF
.394e10		9f 00 a5 38	sta $38a500,x	                STA DOS_FAT_SECTORS,X
.394e14		80 0b		bra $394e21	                BRA write_fat
.394e16						is_odd2
.394e16		bf 00 a5 38	lda $38a500,x	                LDA DOS_FAT_SECTORS,X           ; Reserve the cluster in the FAT, odd offset case
.394e1a		09 f0 ff	ora #$fff0	                ORA #$FFF0
.394e1d		9f 00 a5 38	sta $38a500,x	                STA DOS_FAT_SECTORS,X
.394e21		22 48 4f 39	jsl $394f48	write_fat       JSL WRITEFAT12                  ; Write the two FAT sectors back to disk
.394e25		b0 07		bcs $394e2e	                BCS ret_success                 ; If success: return success
.394e27		e2 20		sep #$20	                SEP #$20        ; set A short
.394e29		a9 14		lda #$14	                LDA #DOS_ERR_FATUPDATE          ; Flag an error trying to write the FAT back
.394e2b		82 46 00	brl $394e74	                BRL ret_failure
.394e2e						ret_success
.394e2e		e2 20		sep #$20	                SEP #$20        ; set A short
.394e30		64 0e		stz $032e	                STZ DOS_STATUS
.394e32		28		plp		                PLP
.394e33		2b		pld		                PLD
.394e34		ab		plb		                PLB
.394e35		fa		plx		                PLX
.394e36		38		sec		                SEC
.394e37		6b		rtl		                RTL
.394e38						next_cluster
.394e38		e6 10		inc $0330	                INC DOS_CLUS_ID                 ; And advance the cluster ID
.394e3a		d0 02		bne $394e3e	                BNE calc_entry
.394e3c		e6 12		inc $0332	                INC DOS_CLUS_ID+2
.394e3e		22 b6 4a 39	jsl $394ab6	calc_entry      JSL ENTRYFORCLUS12              ; Calculate the LBA and offset into the buffer for the cluster
.394e42		e0 00 00	cpx #$0000	                CPX #0                          ; Did we wrap around?
.394e45		f0 03		beq $394e4a	                BEQ chk_end_of_fat
.394e47		82 93 ff	brl $394ddd	                BRL chk_cluster                 ; No: go back and check it too
.394e4a						chk_end_of_fat
.394e4a		a5 24		lda $0344	                LDA DOS_FAT_LBA                 ; Are we at the end of the FAT?
.394e4c		cf 18 a0 38	cmp $38a018	                CMP FAT2_BEGIN_LBA              ; NOTE: we use the start sector of the second FAT as our sentinel
.394e50		d0 0f		bne $394e61	                BNE next_2
.394e52		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
.394e54		cf 1a a0 38	cmp $38a01a	                CMP FAT2_BEGIN_LBA+2
.394e58		d0 07		bne $394e61	                BNE next_2                      ; No: get the next to sectors
.394e5a		e2 20		sep #$20	                SEP #$20        ; set A short
.394e5c		a9 12		lda #$12	                LDA #DOS_ERR_MEDIAFULL          ; Yes: return media full
.394e5e		82 13 00	brl $394e74	                BRL ret_failure
.394e61						next_2
.394e61		22 40 4d 39	jsl $394d40	                JSL FDC_READ2FAT12              ; Read the next two sectors of the FAT
.394e65		90 06		bcc $394e6d	                BCC fat_fail                    ; If failed: return error
.394e67		a2 00 00	ldx #$0000	                LDX #0                          ; If success: Start scanning at the beginning of the sectors
.394e6a		82 70 ff	brl $394ddd	                BRL chk_cluster                 ; And start checking from there
.394e6d						fat_fail
.394e6d		e2 20		sep #$20	                SEP #$20        ; set A short
.394e6f		a9 06		lda #$06	                LDA #DOS_ERR_FAT
.394e71		82 00 00	brl $394e74	                BRL ret_failure
.394e74						ret_failure
.394e74		e2 20		sep #$20	                SEP #$20        ; set A short
.394e76		85 0e		sta $032e	                STA DOS_STATUS
.394e78		28		plp		                PLP
.394e79		2b		pld		                PLD
.394e7a		ab		plb		                PLB
.394e7b		fa		plx		                PLX
.394e7c		18		clc		                CLC
.394e7d		6b		rtl		                RTL
.394e7e						DOS_FREECLUS32
.394e7e		8b		phb		                PHB
.394e7f		0b		phd		                PHD
.394e80		08		php		                PHP
.394e81		48		pha		                PHA             ; begin setdbr macro
.394e82		08		php		                PHP
.394e83		e2 20		sep #$20	                SEP #$20        ; set A short
.394e85		a9 00		lda #$00	                LDA #0
.394e87		48		pha		                PHA
.394e88		ab		plb		                PLB
.394e89		28		plp		                PLP
.394e8a		68		pla		                PLA             ; end setdbr macro
.394e8b		48		pha		                PHA             ; begin setdp macro
.394e8c		08		php		                PHP
.394e8d		c2 20		rep #$20	                REP #$20        ; set A long
.394e8f		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394e92		5b		tcd		                TCD
.394e93		28		plp		                PLP
.394e94		68		pla		                PLA             ; end setdp macro
.394e95		c2 30		rep #$30	                REP #$30        ; set A&X long
.394e97		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR               ; Set the location to store the sector
.394e9a		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394e9c		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
.394e9f		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.394ea1		af 14 a0 38	lda $38a014	                LDA FAT_BEGIN_LBA               ; Set the LBA to that of the first FAT sector
.394ea5		85 02		sta $0322	                STA BIOS_LBA
.394ea7		af 16 a0 38	lda $38a016	                LDA FAT_BEGIN_LBA+2
.394eab		85 04		sta $0324	                STA BIOS_LBA+2
.394ead		22 44 10 00	jsl $001044	                JSL GETBLOCK                    ; Load the sector into memory
.394eb1		b0 07		bcs $394eba	                BCS initial_entry               ; If OK: set the initial entry to check
.394eb3		e2 20		sep #$20	                SEP #$20        ; set A short
.394eb5		a9 06		lda #$06	                LDA #DOS_ERR_FAT                ; Return a NOFAT error
.394eb7		82 6b 00	brl $394f25	                BRL ret_failure
.394eba						initial_entry
.394eba		c2 20		rep #$20	                REP #$20        ; set A long
.394ebc		a9 02 00	lda #$0002	                LDA #2                          ; Set DOS_CLUS_ID to 2
.394ebf		85 10		sta $0330	                STA DOS_CLUS_ID
.394ec1		a9 00 00	lda #$0000	                LDA #0
.394ec4		85 12		sta $0332	                STA DOS_CLUS_ID+2
.394ec6		a2 08 00	ldx #$0008	                LDX #8                          ; Set the offset to DOS_CLUS_ID * 4
.394ec9		bf 00 a3 38	lda $38a300,x	chk_entry       LDA DOS_SECTOR,X                ; Is the cluster entry == $00000000?
.394ecd		d0 06		bne $394ed5	                BNE next_entry                  ; No: move to the next entry
.394ecf		bf 02 a3 38	lda $38a302,x	                LDA DOS_SECTOR+2,X
.394ed3		f0 36		beq $394f0b	                BEQ found_free                  ; Yes: go to allocate and return it
.394ed5		e6 10		inc $0330	next_entry      INC DOS_CLUS_ID                 ; Move to the next cluster
.394ed7		d0 02		bne $394edb	                BNE inc_ptr
.394ed9		e6 12		inc $0332	                INC DOS_CLUS_ID+2
.394edb		e8		inx		inc_ptr         INX                             ; Update the index to the entry
.394edc		e8		inx		                INX
.394edd		e8		inx		                INX
.394ede		e8		inx		                INX
.394edf		e0 00 02	cpx #$0200	                CPX #DOS_SECTOR_SIZE            ; Are we outside the sector?
.394ee2		90 e5		bcc $394ec9	                BLT chk_entry                   ; No: check this entry
.394ee4		e6 02		inc $0322	                INC BIOS_LBA                    ; Point to the next sector in the FAT
.394ee6		d0 18		bne $394f00	                BNE get_block
.394ee8		e6 04		inc $0324	                INC BIOS_LBA+2
.394eea		a5 04		lda $0324	                LDA BIOS_LBA+2
.394eec		cf 1a a0 38	cmp $38a01a	                CMP FAT2_BEGIN_LBA+2
.394ef0		90 0e		bcc $394f00	                BLT get_block
.394ef2		a5 02		lda $0322	                LDA BIOS_LBA
.394ef4		cf 18 a0 38	cmp $38a018	                CMP FAT2_BEGIN_LBA
.394ef8		90 06		bcc $394f00	                BLT get_block
.394efa		e2 20		sep #$20	                SEP #$20        ; set A short
.394efc		a9 12		lda #$12	                LDA #DOS_ERR_MEDIAFULL          ; No: throw a media full error
.394efe		80 25		bra $394f25	                BRA ret_failure
.394f00		22 44 10 00	jsl $001044	get_block       JSL GETBLOCK                    ; Attempt to read the block
.394f04		90 1b		bcc $394f21	                BCC ret_fat_error               ; If error: throw a FAT error
.394f06		a2 00 00	ldx #$0000	set_ptr         LDX #0                          ; Set index pointer to the first entry
.394f09		80 be		bra $394ec9	                BRA chk_entry                   ; Check this entry
.394f0b						found_free
.394f0b		c2 20		rep #$20	                REP #$20        ; set A long
.394f0d		a9 ff ff	lda #$ffff	                LDA #<>FAT_LAST_CLUSTER         ; Set the entry to $0FFFFFFF to make it the last entry in its chain
.394f10		9f 00 a3 38	sta $38a300,x	                STA DOS_SECTOR,X
.394f14		a9 ff 0f	lda #$0fff	                LDA #(FAT_LAST_CLUSTER >> 16)
.394f17		9f 02 a3 38	sta $38a302,x	                STA DOS_SECTOR+2,X
.394f1b		22 24 10 00	jsl $001024	                JSL PUTBLOCK                    ; Write the sector back to the block device
.394f1f		b0 0d		bcs $394f2e	                BCS ret_success                 ; If OK: return success
.394f21						ret_fat_error
.394f21		e2 20		sep #$20	                SEP #$20        ; set A short
.394f23		a9 06		lda #$06	                LDA #DOS_ERR_FAT                ; Otherwise: return NOFAT error
.394f25						ret_failure
.394f25		e2 20		sep #$20	                SEP #$20        ; set A short
.394f27		85 0e		sta $032e	                STA DOS_STATUS
.394f29		28		plp		                PLP
.394f2a		2b		pld		                PLD
.394f2b		ab		plb		                PLB
.394f2c		18		clc		                CLC
.394f2d		6b		rtl		                RTL
.394f2e						ret_success
.394f2e		e2 20		sep #$20	                SEP #$20        ; set A short
.394f30		64 0e		stz $032e	                STZ DOS_STATUS
.394f32		28		plp		                PLP
.394f33		2b		pld		                PLD
.394f34		ab		plb		                PLB
.394f35		38		sec		                SEC
.394f36		6b		rtl		                RTL
.394f37						DELCLUSTER
.394f37		e2 20		sep #$20	                SEP #$20        ; set A short
.394f39		af 01 a0 38	lda $38a001	                LDA @l FILE_SYSTEM              ; Get the file system code
.394f3d		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12            ; Is it FAT12?
.394f3f		d0 04		bne $394f45	                BNE fat32                       ; No: assume it's FAT32
.394f41		5c 8f 4f 39	jmp $394f8f	fat12           JML DELCLUSTER12
.394f45		4c dd 4f	jmp $394fdd	fat32           JMP DELCLUSTER32
.394f48						WRITEFAT12
.394f48		8b		phb		                PHB
.394f49		0b		phd		                PHD
.394f4a		48		pha		                PHA             ; begin setdbr macro
.394f4b		08		php		                PHP
.394f4c		e2 20		sep #$20	                SEP #$20        ; set A short
.394f4e		a9 00		lda #$00	                LDA #0
.394f50		48		pha		                PHA
.394f51		ab		plb		                PLB
.394f52		28		plp		                PLP
.394f53		68		pla		                PLA             ; end setdbr macro
.394f54		48		pha		                PHA             ; begin setdp macro
.394f55		08		php		                PHP
.394f56		c2 20		rep #$20	                REP #$20        ; set A long
.394f58		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394f5b		5b		tcd		                TCD
.394f5c		28		plp		                PLP
.394f5d		68		pla		                PLA             ; end setdp macro
.394f5e		c2 30		rep #$30	                REP #$30        ; set A&X long
.394f60		a9 00 a5	lda #$a500	                LDA #<>DOS_FAT_SECTORS          ; Point to the first FAT sector in memory
.394f63		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394f65		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
.394f68		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.394f6a		a5 24		lda $0344	                LDA DOS_FAT_LBA                 ; Set the LBA to that of the first sector's
.394f6c		85 02		sta $0322	                STA BIOS_LBA
.394f6e		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
.394f70		85 04		sta $0324	                STA BIOS_LBA+2
.394f72		22 24 10 00	jsl $001024	                JSL PUTBLOCK                    ; Write the first sector back to the block device
.394f76		90 14		bcc $394f8c	                BCC done
.394f78		a9 00 a7	lda #$a700	                LDA #<>(DOS_FAT_SECTORS+DOS_SECTOR_SIZE)
.394f7b		85 06		sta $0326	                STA BIOS_BUFF_PTR
.394f7d		a9 38 00	lda #$0038	                LDA #`(DOS_FAT_SECTORS+DOS_SECTOR_SIZE)
.394f80		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
.394f82		e6 02		inc $0322	                INC BIOS_LBA                    ; Point to the next sector in the FAT
.394f84		d0 02		bne $394f88	                BNE put_second
.394f86		e6 04		inc $0324	                INC BIOS_LBA+2
.394f88		22 24 10 00	jsl $001024	put_second      JSL PUTBLOCK                    ; Write the second sector back to the block device
.394f8c		2b		pld		done            PLD
.394f8d		ab		plb		                PLB
.394f8e		6b		rtl		                RTL
.394f8f						DELCLUSTER12
.394f8f		8b		phb		                PHB
.394f90		0b		phd		                PHD
.394f91		08		php		                PHP
.394f92		48		pha		                PHA             ; begin setdbr macro
.394f93		08		php		                PHP
.394f94		e2 20		sep #$20	                SEP #$20        ; set A short
.394f96		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.394f98		48		pha		                PHA
.394f99		ab		plb		                PLB
.394f9a		28		plp		                PLP
.394f9b		68		pla		                PLA             ; end setdbr macro
.394f9c		48		pha		                PHA             ; begin setdp macro
.394f9d		08		php		                PHP
.394f9e		c2 20		rep #$20	                REP #$20        ; set A long
.394fa0		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394fa3		5b		tcd		                TCD
.394fa4		28		plp		                PLP
.394fa5		68		pla		                PLA             ; end setdp macro
.394fa6		c2 30		rep #$30	                REP #$30        ; set A&X long
.394fa8		22 29 4b 39	jsl $394b29	                JSL FATFORCLUSTER12
.394fac		8a		txa		                TXA                             ; Check to see if the index is odd or even
.394fad		89 01 00	bit #$0001	                BIT #1
.394fb0		d0 08		bne $394fba	                BNE is_odd
.394fb2		bd 00 a5	lda $38a500,x	is_even         LDA DOS_FAT_SECTORS,X           ; Get the two bytes from the FAT
.394fb5		29 00 f0	and #$f000	                AND #$F000                      ; Mask out the lower 12 bits
.394fb8		80 06		bra $394fc0	                BRA save_update
.394fba		bd 00 a5	lda $38a500,x	is_odd          LDA DOS_FAT_SECTORS,X           ; Get the two bytes from the FAT
.394fbd		29 0f 00	and #$000f	                AND #$000F                      ; Mask out the upper 12 bits
.394fc0		9d 00 a5	sta $38a500,x	save_update     STA DOS_FAT_SECTORS,X           ; And write it back
.394fc3		22 48 4f 39	jsl $394f48	                JSL WRITEFAT12                  ; Write the two FAT12 sectors back to the drive
.394fc7		b0 0b		bcs $394fd4	                BCS ret_success
.394fc9						ret_failure
.394fc9		e2 20		sep #$20	                SEP #$20        ; set A short
.394fcb		a9 06		lda #$06	                LDA #DOS_ERR_FAT
.394fcd		85 0e		sta $032e	                STA DOS_STATUS
.394fcf		28		plp		                PLP
.394fd0		2b		pld		                PLD
.394fd1		ab		plb		                PLB
.394fd2		18		clc		                CLC
.394fd3		6b		rtl		                RTL
.394fd4						ret_success
.394fd4		e2 20		sep #$20	                SEP #$20        ; set A short
.394fd6		64 0e		stz $032e	                STZ DOS_STATUS
.394fd8		28		plp		                PLP
.394fd9		2b		pld		                PLD
.394fda		ab		plb		                PLB
.394fdb		38		sec		                SEC
.394fdc		6b		rtl		                RTL
.394fdd						DELCLUSTER32
.394fdd		8b		phb		                PHB
.394fde		0b		phd		                PHD
.394fdf		08		php		                PHP
.394fe0		c2 30		rep #$30	                REP #$30        ; set A&X long
.394fe2		48		pha		                PHA             ; begin setdbr macro
.394fe3		08		php		                PHP
.394fe4		e2 20		sep #$20	                SEP #$20        ; set A short
.394fe6		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.394fe8		48		pha		                PHA
.394fe9		ab		plb		                PLB
.394fea		28		plp		                PLP
.394feb		68		pla		                PLA             ; end setdbr macro
.394fec		48		pha		                PHA             ; begin setdp macro
.394fed		08		php		                PHP
.394fee		c2 20		rep #$20	                REP #$20        ; set A long
.394ff0		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.394ff3		5b		tcd		                TCD
.394ff4		28		plp		                PLP
.394ff5		68		pla		                PLA             ; end setdp macro
.394ff6		22 91 4b 39	jsl $394b91	                JSL FATFORCLUSTER32
.394ffa		a9 00 00	lda #$0000	                LDA #0
.394ffd		9d 00 a5	sta $38a500,x	                STA DOS_FAT_SECTORS,X           ; Set the cluster entry to 0
.395000		9d 02 a5	sta $38a502,x	                STA DOS_FAT_SECTORS+2,X
.395003		22 24 10 00	jsl $001024	                JSL PUTBLOCK                    ; Write the sector back to the block device
.395007		b0 0b		bcs $395014	                BCS ret_success
.395009						ret_failure
.395009		e2 20		sep #$20	                SEP #$20        ; set A short
.39500b		a9 06		lda #$06	                LDA #DOS_ERR_FAT
.39500d		85 0e		sta $032e	                STA DOS_STATUS
.39500f		28		plp		                PLP
.395010		2b		pld		                PLD
.395011		ab		plb		                PLB
.395012		18		clc		                CLC
.395013		6b		rtl		                RTL
.395014						ret_success
.395014		e2 20		sep #$20	                SEP #$20        ; set A short
.395016		64 0e		stz $032e	                STZ DOS_STATUS
.395018		28		plp		                PLP
.395019		2b		pld		                PLD
.39501a		ab		plb		                PLB
.39501b		38		sec		                SEC
.39501c		6b		rtl		                RTL
.39501d						DOS_APPENDCLUS
.39501d		8b		phb		                PHB
.39501e		0b		phd		                PHD
.39501f		08		php		                PHP
.395020		48		pha		                PHA             ; begin setdbr macro
.395021		08		php		                PHP
.395022		e2 20		sep #$20	                SEP #$20        ; set A short
.395024		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395026		48		pha		                PHA
.395027		ab		plb		                PLB
.395028		28		plp		                PLP
.395029		68		pla		                PLA             ; end setdbr macro
.39502a		48		pha		                PHA             ; begin setdp macro
.39502b		08		php		                PHP
.39502c		c2 20		rep #$20	                REP #$20        ; set A long
.39502e		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395031		5b		tcd		                TCD
.395032		28		plp		                PLP
.395033		68		pla		                PLA             ; end setdp macro
.395034		c2 30		rep #$30	                REP #$30        ; set A&X long
.395036		a5 12		lda $0332	                LDA DOS_CLUS_ID+2               ; Save the cluster number for later
.395038		48		pha		                PHA
.395039		a5 10		lda $0330	                LDA DOS_CLUS_ID
.39503b		48		pha		                PHA
.39503c		22 15 4d 39	jsl $394d15	                JSL DOS_FREECLUS                ; Find a free cluster on the block device
.395040		b0 09		bcs $39504b	                BCS save_cluster                ; If we got a cluster, write the data to it
.395042		68		pla		fail_cleanup    PLA                             ; Restore the cluster of the file
.395043		85 10		sta $0330	                STA DOS_CLUS_ID
.395045		68		pla		                PLA
.395046		85 12		sta $0332	                STA DOS_CLUS_ID+2
.395048		82 7d 00	brl $3950c8	                BRL pass_failure                ; Pass the failure back up the chain
.39504b		a5 10		lda $0330	save_cluster    LDA DOS_CLUS_ID
.39504d		8d 36 a0	sta $38a036	                STA DOS_NEW_CLUSTER
.395050		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.395052		8d 38 a0	sta $38a038	                STA DOS_NEW_CLUSTER+2
.395055		22 29 48 39	jsl $394829	                JSL DOS_PUTCLUSTER              ; Write the data to the free cluster
.395059		90 e7		bcc $395042	                BCC fail_cleanup                ; If failure: clean up stack and pass the failure up
.39505b		68		pla		                PLA                             ; Restore the cluster of the file
.39505c		85 10		sta $0330	                STA DOS_CLUS_ID
.39505e		68		pla		                PLA
.39505f		85 12		sta $0332	                STA DOS_CLUS_ID+2
.395061		22 fc 4b 39	jsl $394bfc	walk_loop       JSL NEXTCLUSTER                 ; Try to get the next cluster in the chain
.395065		b0 fa		bcs $395061	                BCS walk_loop                   ; If found a cluster, keep walking the chain
.395067		e2 20		sep #$20	                SEP #$20        ; set A short
.395069		af 01 a0 38	lda $38a001	                LDA @l FILE_SYSTEM              ; Get the file system code
.39506d		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12            ; Is it FAT12?
.39506f		d0 3d		bne $3950ae	                BNE fat32                       ; No: assume it's FAT32
.395071						fat12
.395071		c2 20		rep #$20	                REP #$20        ; set A long
.395073		22 b6 4a 39	jsl $394ab6	                JSL ENTRYFORCLUS12              ; Make sure we have the right offset for the cluster
.395077		a5 10		lda $0330	                LDA DOS_CLUS_ID                 ; Check to see if the last cluster ID is even or odd
.395079		89 01 00	bit #$0001	                BIT #1
.39507c		d0 11		bne $39508f	                BNE is_odd
.39507e		ad 36 a0	lda $38a036	is_even         LDA DOS_NEW_CLUSTER             ; Handle the even case (change the lower 12 bits)
.395081		29 ff 0f	and #$0fff	                AND #$0FFF
.395084		8d 36 a0	sta $38a036	                STA DOS_NEW_CLUSTER
.395087		bd 00 a5	lda $38a500,x	                LDA DOS_FAT_SECTORS,X
.39508a		29 00 f0	and #$f000	                AND #$F000
.39508d		80 10		bra $39509f	                BRA update_fat12
.39508f		ad 36 a0	lda $38a036	is_odd          LDA DOS_NEW_CLUSTER             ; Handle the odd case (change the upper 12 bits)
.395092		0a		asl a		                ASL A
.395093		0a		asl a		                ASL A
.395094		0a		asl a		                ASL A
.395095		0a		asl a		                ASL A
.395096		8d 36 a0	sta $38a036	                STA DOS_NEW_CLUSTER
.395099		bd 00 a5	lda $38a500,x	                LDA DOS_FAT_SECTORS,X
.39509c		29 0f 00	and #$000f	                AND #$000F
.39509f		0d 36 a0	ora $38a036	update_fat12    ORA DOS_NEW_CLUSTER
.3950a2		9d 00 a5	sta $38a500,x	                STA DOS_FAT_SECTORS,X
.3950a5		22 48 4f 39	jsl $394f48	                JSL WRITEFAT12                  ; Write the two FAT12 sectors back to the drive
.3950a9		b0 22		bcs $3950cd	                BCS ret_success
.3950ab		82 1a 00	brl $3950c8	                BRL pass_failure
.3950ae						fat32
.3950ae		c2 20		rep #$20	                REP #$20        ; set A long
.3950b0		ad 36 a0	lda $38a036	                LDA DOS_NEW_CLUSTER             ; Write the ID of the new cluster to the end of the chain
.3950b3		9d 00 a5	sta $38a500,x	                STA DOS_FAT_SECTORS,X
.3950b6		ad 38 a0	lda $38a038	                LDA DOS_NEW_CLUSTER+2
.3950b9		9d 02 a5	sta $38a502,x	                STA DOS_FAT_SECTORS+2,X
.3950bc		22 24 10 00	jsl $001024	                JSL PUTBLOCK                    ; Write the FAT sector back (assumes BIOS_LBA and BIOS_BUFF_PTR haven't changed)
.3950c0		b0 0b		bcs $3950cd	                BCS ret_success
.3950c2		e2 20		sep #$20	                SEP #$20        ; set A short
.3950c4		a9 06		lda #$06	                LDA #DOS_ERR_FAT                ; Problem working with the FAT
.3950c6		85 0e		sta $032e	                STA DOS_STATUS
.3950c8		28		plp		pass_failure    PLP
.3950c9		2b		pld		                PLD
.3950ca		ab		plb		                PLB
.3950cb		18		clc		                CLC
.3950cc		6b		rtl		                RTL
.3950cd						ret_success
.3950cd		e2 20		sep #$20	                SEP #$20        ; set A short
.3950cf		64 0e		stz $032e	                STZ DOS_STATUS
.3950d1		28		plp		                PLP
.3950d2		2b		pld		                PLD
.3950d3		ab		plb		                PLB
.3950d4		38		sec		                SEC
.3950d5		6b		rtl		                RTL
.3950d6						BCD2BIN
.3950d6		8b		phb		                PHB
.3950d7		0b		phd		                PHD
.3950d8		08		php		                PHP
.3950d9		48		pha		                PHA             ; begin setdbr macro
.3950da		08		php		                PHP
.3950db		e2 20		sep #$20	                SEP #$20        ; set A short
.3950dd		a9 00		lda #$00	                LDA #0
.3950df		48		pha		                PHA
.3950e0		ab		plb		                PLB
.3950e1		28		plp		                PLP
.3950e2		68		pla		                PLA             ; end setdbr macro
.3950e3		48		pha		                PHA             ; begin setdp macro
.3950e4		08		php		                PHP
.3950e5		c2 20		rep #$20	                REP #$20        ; set A long
.3950e7		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3950ea		5b		tcd		                TCD
.3950eb		28		plp		                PLP
.3950ec		68		pla		                PLA             ; end setdp macro
.3950ed		c2 30		rep #$30	                REP #$30        ; set A&X long
.3950ef		85 28		sta $0348	                STA DOS_TEMP
.3950f1		29 0f 00	and #$000f	                AND #$000F
.3950f4		85 2a		sta $034a	                STA DOS_TEMP+2
.3950f6		a5 28		lda $0348	                LDA DOS_TEMP
.3950f8		4a		lsr a		                LSR A
.3950f9		4a		lsr a		                LSR A
.3950fa		4a		lsr a		                LSR A
.3950fb		4a		lsr a		                LSR A
.3950fc		85 28		sta $0348	                STA DOS_TEMP
.3950fe		29 0f 00	and #$000f	                AND #$000F
.395101		8f 00 01 00	sta $000100	                STA @l UNSIGNED_MULT_A_LO
.395105		a9 0a 00	lda #$000a	                LDA #10
.395108		8f 02 01 00	sta $000102	                STA @l UNSIGNED_MULT_B_LO
.39510c		af 04 01 00	lda $000104	                LDA @l UNSIGNED_MULT_AL_LO
.395110		18		clc		                CLC
.395111		65 2a		adc $034a	                ADC DOS_TEMP+2
.395113		85 2a		sta $034a	                STA DOS_TEMP+2
.395115		a5 28		lda $0348	                LDA DOS_TEMP
.395117		4a		lsr a		                LSR A
.395118		4a		lsr a		                LSR A
.395119		4a		lsr a		                LSR A
.39511a		4a		lsr a		                LSR A
.39511b		85 28		sta $0348	                STA DOS_TEMP
.39511d		29 0f 00	and #$000f	                AND #$000F
.395120		8f 00 01 00	sta $000100	                STA @l UNSIGNED_MULT_A_LO
.395124		a9 64 00	lda #$0064	                LDA #100
.395127		8f 02 01 00	sta $000102	                STA @l UNSIGNED_MULT_B_LO
.39512b		af 04 01 00	lda $000104	                LDA @l UNSIGNED_MULT_AL_LO
.39512f		18		clc		                CLC
.395130		65 2a		adc $034a	                ADC DOS_TEMP+2
.395132		85 2a		sta $034a	                STA DOS_TEMP+2
.395134		a5 28		lda $0348	                LDA DOS_TEMP
.395136		4a		lsr a		                LSR A
.395137		4a		lsr a		                LSR A
.395138		4a		lsr a		                LSR A
.395139		4a		lsr a		                LSR A
.39513a		29 0f 00	and #$000f	                AND #$000F
.39513d		8f 00 01 00	sta $000100	                STA @l UNSIGNED_MULT_A_LO
.395141		a9 e8 03	lda #$03e8	                LDA #1000
.395144		8f 02 01 00	sta $000102	                STA @l UNSIGNED_MULT_B_LO
.395148		af 04 01 00	lda $000104	                LDA @l UNSIGNED_MULT_AL_LO
.39514c		18		clc		                CLC
.39514d		65 2a		adc $034a	                ADC DOS_TEMP+2
.39514f		28		plp		                PLP
.395150		2b		pld		                PLD
.395151		ab		plb		                PLB
.395152		6b		rtl		                RTL
.395153						DOS_RTCCREATE
.395153		8b		phb		                PHB
.395154		0b		phd		                PHD
.395155		08		php		                PHP
.395156		48		pha		                PHA             ; begin setdbr macro
.395157		08		php		                PHP
.395158		e2 20		sep #$20	                SEP #$20        ; set A short
.39515a		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.39515c		48		pha		                PHA
.39515d		ab		plb		                PLB
.39515e		28		plp		                PLP
.39515f		68		pla		                PLA             ; end setdbr macro
.395160		48		pha		                PHA             ; begin setdp macro
.395161		08		php		                PHP
.395162		c2 20		rep #$20	                REP #$20        ; set A long
.395164		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395167		5b		tcd		                TCD
.395168		28		plp		                PLP
.395169		68		pla		                PLA             ; end setdp macro
.39516a		c2 10		rep #$10	                REP #$10        ; set X long
.39516c		e2 20		sep #$20	                SEP #$20        ; set A short
.39516e		af 0e 08 af	lda $af080e	                LDA @l RTC_CTRL             ; Turn off the updates to the clock
.395172		09 08		ora #$08	                ORA #%00001000
.395174		8f 0e 08 af	sta $af080e	                STA @l RTC_CTRL
.395178		af 0f 08 af	lda $af080f	                LDA @l RTC_CENTURY
.39517c		85 29		sta $0349	                STA DOS_TEMP+1
.39517e		af 0a 08 af	lda $af080a	                LDA @l RTC_YEAR             ; Get the year
.395182		85 28		sta $0348	                STA DOS_TEMP
.395184		c2 20		rep #$20	                REP #$20        ; set A long
.395186		a5 28		lda $0348	                LDA DOS_TEMP
.395188		22 d6 50 39	jsl $3950d6	                JSL BCD2BIN                 ; Convert it to binary
.39518c		85 28		sta $0348	                STA DOS_TEMP
.39518e		38		sec		                SEC                         ; Year is relative to 1980
.39518f		e9 bc 07	sbc #$07bc	                SBC #1980
.395192		c2 20		rep #$20	                REP #$20        ; set A long
.395194		0a		asl a		                ASL A
.395195		0a		asl a		                ASL A
.395196		0a		asl a		                ASL A
.395197		0a		asl a		                ASL A
.395198		0a		asl a		                ASL A
.395199		0a		asl a		                ASL A
.39519a		0a		asl a		                ASL A
.39519b		0a		asl a		                ASL A
.39519c		0a		asl a		                ASL A
.39519d		29 00 fe	and #$fe00	                AND #$FE00
.3951a0		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE   ; And save it to the creation date field
.3951a3		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3951a5		e2 20		sep #$20	                SEP #$20        ; set A short
.3951a7		af 09 08 af	lda $af0809	                LDA @l RTC_MONTH            ; Get the month
.3951ab		c2 20		rep #$20	                REP #$20        ; set A long
.3951ad		29 ff 00	and #$00ff	                AND #$00FF
.3951b0		22 d6 50 39	jsl $3950d6	                JSL BCD2BIN                 ; Convert it to binary
.3951b4		29 ff 00	and #$00ff	                AND #$00FF                  ; Move the year to bits 15 - 9
.3951b7		0a		asl a		                ASL A
.3951b8		0a		asl a		                ASL A
.3951b9		0a		asl a		                ASL A
.3951ba		0a		asl a		                ASL A
.3951bb		0a		asl a		                ASL A
.3951bc		29 e0 01	and #$01e0	                AND #$01E0                  ; Make sure only the month is covered
.3951bf		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE   ; And save it to the creation date field
.3951c2		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
.3951c4		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3951c6		e2 20		sep #$20	                SEP #$20        ; set A short
.3951c8		af 06 08 af	lda $af0806	                LDA @l RTC_DAY              ; Get the day
.3951cc		c2 20		rep #$20	                REP #$20        ; set A long
.3951ce		29 ff 00	and #$00ff	                AND #$00FF
.3951d1		22 d6 50 39	jsl $3950d6	                JSL BCD2BIN                 ; Convert it to binary
.3951d5		29 1f 00	and #$001f	                AND #$001F                  ; Make sure only the day is covered
.3951d8		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE   ; And save it to the creation date field
.3951db		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
.3951dd		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3951df		e2 20		sep #$20	                SEP #$20        ; set A short
.3951e1		af 04 08 af	lda $af0804	                LDA @l RTC_HRS              ; Get the hour
.3951e5		29 1f		and #$1f	                AND #$1F                    ; Trim AM/PM bit
.3951e7		c2 20		rep #$20	                REP #$20        ; set A long
.3951e9		29 ff 00	and #$00ff	                AND #$00FF
.3951ec		22 d6 50 39	jsl $3950d6	                JSL BCD2BIN                 ; Convert it to binary
.3951f0		c2 20		rep #$20	                REP #$20        ; set A long
.3951f2		0a		asl a		                ASL A
.3951f3		0a		asl a		                ASL A
.3951f4		0a		asl a		                ASL A
.3951f5		0a		asl a		                ASL A
.3951f6		0a		asl a		                ASL A
.3951f7		0a		asl a		                ASL A
.3951f8		0a		asl a		                ASL A
.3951f9		0a		asl a		                ASL A
.3951fa		0a		asl a		                ASL A
.3951fb		0a		asl a		                ASL A
.3951fc		0a		asl a		                ASL A
.3951fd		29 00 f8	and #$f800	                AND #$F800
.395200		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME   ; And save it to the creation time field
.395203		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395205		e2 20		sep #$20	                SEP #$20        ; set A short
.395207		af 02 08 af	lda $af0802	                LDA @l RTC_MIN              ; Get the minute
.39520b		c2 20		rep #$20	                REP #$20        ; set A long
.39520d		29 ff 00	and #$00ff	                AND #$00FF
.395210		22 d6 50 39	jsl $3950d6	                JSL BCD2BIN                 ; Convert it to binary
.395214		c2 20		rep #$20	                REP #$20        ; set A long
.395216		0a		asl a		                ASL A
.395217		0a		asl a		                ASL A
.395218		0a		asl a		                ASL A
.395219		0a		asl a		                ASL A
.39521a		0a		asl a		                ASL A
.39521b		29 e0 07	and #$07e0	                AND #$07E0
.39521e		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME   ; And save it to the creation time field
.395221		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
.395223		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395225		e2 20		sep #$20	                SEP #$20        ; set A short
.395227		af 00 08 af	lda $af0800	                LDA @l RTC_SEC              ; Get the second
.39522b		c2 20		rep #$20	                REP #$20        ; set A long
.39522d		29 ff 00	and #$00ff	                AND #$00FF
.395230		22 d6 50 39	jsl $3950d6	                JSL BCD2BIN                 ; Convert it to binary
.395234		c2 20		rep #$20	                REP #$20        ; set A long
.395236		29 1f 00	and #$001f	                AND #$001F
.395239		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME   ; And save it to the creation time field
.39523c		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
.39523e		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395240		af 0e 08 af	lda $af080e	                LDA @l RTC_CTRL             ; Turn on the updates again
.395244		29 f7 00	and #$00f7	                AND #%11110111
.395247		8f 0e 08 af	sta $af080e	                STA @l RTC_CTRL
.39524b		28		plp		                PLP
.39524c		2b		pld		                PLD
.39524d		ab		plb		                PLB
.39524e		6b		rtl		                RTL
.39524f						DOS_CREATE
.39524f		8b		phb		                PHB
.395250		0b		phd		                PHD
.395251		08		php		                PHP
.395252		48		pha		                PHA             ; begin setdbr macro
.395253		08		php		                PHP
.395254		e2 20		sep #$20	                SEP #$20        ; set A short
.395256		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395258		48		pha		                PHA
.395259		ab		plb		                PLB
.39525a		28		plp		                PLP
.39525b		68		pla		                PLA             ; end setdbr macro
.39525c		48		pha		                PHA             ; begin setdp macro
.39525d		08		php		                PHP
.39525e		c2 20		rep #$20	                REP #$20        ; set A long
.395260		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395263		5b		tcd		                TCD
.395264		28		plp		                PLP
.395265		68		pla		                PLA             ; end setdp macro
.395266		c2 30		rep #$30	                REP #$30        ; set A&X long
.395268		a0 02 00	ldy #$0002	                LDY #FILEDESC.PATH              ; DOS_TEMP := DOS_FD_PTR->PATH
.39526b		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.39526d		85 28		sta $0348	                STA DOS_TEMP
.39526f		c8		iny		                INY
.395270		c8		iny		                INY
.395271		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395273		85 2a		sta $034a	                STA DOS_TEMP+2
.395275		e2 20		sep #$20	                SEP #$20        ; set A short
.395277		a0 00 00	ldy #$0000	                LDY #0
.39527a		a2 00 00	ldx #$0000	                LDX #0
.39527d		b7 28		lda [$0348],y	path_loop       LDA [DOS_TEMP],Y                ; Get a byte of the path
.39527f		95 e0		sta $0400,x	                STA DOS_PATH_BUFF,X             ; ... save it to the path buffer
.395281		f0 04		beq $395287	                BEQ find_file                   ; If it's NULL, we're done
.395283		e8		inx		                INX
.395284		c8		iny		                INY
.395285		80 f6		bra $39527d	                BRA path_loop
.395287		22 3a 49 39	jsl $39493a	find_file       JSL DOS_PARSE_PATH
.39528b		22 d2 49 39	jsl $3949d2	                JSL DOS_FINDFILE
.39528f		90 07		bcc $395298	                BCC set_device
.395291		e2 20		sep #$20	                SEP #$20        ; set A short
.395293		a9 0b		lda #$0b	                LDA #DOS_ERR_FILEEXISTS
.395295		82 d2 00	brl $39536a	                BRL ret_failure
.395298						set_device
.395298		e2 20		sep #$20	                SEP #$20        ; set A short
.39529a		a0 01 00	ldy #$0001	                LDY #FILEDESC.DEV               ; Set the device in the file descriptor
.39529d		a5 01		lda $0321	                LDA BIOS_DEV
.39529f		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3952a1						validate_name
.3952a1		22 15 4d 39	jsl $394d15	                JSL DOS_FREECLUS
.3952a5		b0 03		bcs $3952aa	                BCS save_data
.3952a7		82 c4 00	brl $39536e	                BRL pass_failure
.3952aa						save_data
.3952aa		c2 20		rep #$20	                REP #$20        ; set A long
.3952ac		a0 0a 00	ldy #$000a	                LDY #FILEDESC.FIRST_CLUSTER
.3952af		a5 10		lda $0330	                LDA DOS_CLUS_ID             ; DOS_FD_PTR->FIRST_CLUSTER := DOS_CLUS_ID
.3952b1		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3952b3		c8		iny		                INY
.3952b4		c8		iny		                INY
.3952b5		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.3952b7		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3952b9		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER        ; DOS_BUFF_PTR := DOS_FD_PTR->BUFFER
.3952bc		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3952be		85 1c		sta $033c	                STA DOS_BUFF_PTR
.3952c0		c8		iny		                INY
.3952c1		c8		iny		                INY
.3952c2		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3952c4		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
.3952c6		22 29 48 39	jsl $394829	                JSL DOS_PUTCLUSTER
.3952ca		b0 00		bcs $3952cc	                BCS find_dir
.3952cc						find_dir
.3952cc		c2 20		rep #$20	                REP #$20        ; set A long
.3952ce		22 64 43 39	jsl $394364	                JSL DOS_DIRFINDFREE
.3952d2		b0 1a		bcs $3952ee	                BCS set_entry
.3952d4		c2 20		rep #$20	                REP #$20        ; set A long
.3952d6		a0 0a 00	ldy #$000a	                LDY #FILEDESC.FIRST_CLUSTER     ; Failed to get the directory entry...
.3952d9		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y              ; DOS_CLUS_ID := DOS_FD_PTR->FIRST_CLUSTER
.3952db		85 10		sta $0330	                STA DOS_CLUS_ID
.3952dd		c8		iny		                INY
.3952de		c8		iny		                INY
.3952df		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3952e1		85 12		sta $0332	                STA DOS_CLUS_ID+2
.3952e3		22 dd 4f 39	jsl $394fdd	                JSL DELCLUSTER32                ; Delete the cluster
.3952e7		e2 20		sep #$20	                SEP #$20        ; set A short
.3952e9		a9 08		lda #$08	                LDA #DOS_ERR_NODIR              ; Return that we couldn't read the directory
.3952eb		82 7c 00	brl $39536a	                BRL ret_failure
.3952ee						set_entry
.3952ee		e2 20		sep #$20	                SEP #$20        ; set A short
.3952f0		a0 00 00	ldy #$0000	                LDY #0
.3952f3		a9 00		lda #$00	                LDA #0                          ; NULL
.3952f5		97 18		sta [$0338],y	copy_dir_loop   STA [DOS_DIR_PTR],Y             ; Save it to the directory cluster
.3952f7		c8		iny		                INY
.3952f8		c0 20 00	cpy #$0020	                CPY #SIZE(DIRENTRY)
.3952fb		d0 f8		bne $3952f5	                BNE copy_dir_loop
.3952fd		a0 00 00	ldy #$0000	                LDY #0
.395300		b9 3a a0	lda $38a03a,y	name_loop       LDA DOS_SHORT_NAME,Y            ; Copy the name over
.395303		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.395305		c8		iny		                INY
.395306		c0 0b 00	cpy #$000b	                CPY #11
.395309		d0 f5		bne $395300	                BNE name_loop
.39530b		c2 20		rep #$20	                REP #$20        ; set A long
.39530d		a0 0a 00	ldy #$000a	                LDY #FILEDESC.FIRST_CLUSTER     ; DOS_DIR_PTR->CLUSTER_L := DOS_FD_PTR->FIRST_CLUSTER[15..0]
.395310		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395312		a0 1a 00	ldy #$001a	                LDY #DIRENTRY.CLUSTER_L
.395315		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.395317		a0 0c 00	ldy #$000c	                LDY #FILEDESC.FIRST_CLUSTER+2   ; DOS_DIR_PTR->CLUSTER_H := DOS_FD_PTR->FIRST_CLUSTER[31..16]
.39531a		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.39531c		a0 14 00	ldy #$0014	                LDY #DIRENTRY.CLUSTER_H
.39531f		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.395321		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE              ; DOS_DIR_PTR->SIZE := DOS_FD_PTR->SIZE
.395324		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395326		a0 1c 00	ldy #$001c	                LDY #DIRENTRY.SIZE
.395329		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.39532b		a0 14 00	ldy #$0014	                LDY #FILEDESC.SIZE+2
.39532e		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395330		a0 1e 00	ldy #$001e	                LDY #DIRENTRY.SIZE+2
.395333		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.395335		a9 00 00	lda #$0000	                LDA #0                          ; Force create date-time to 0
.395338		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE       ; TODO: restore the RTC integration when that is working better.
.39533b		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.39533d		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME
.395340		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395342		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE       ; DOS_DIR_PTR->CREATE_DATE := DOS_FD_PTR->CREATE_DATE
.395345		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395347		a0 10 00	ldy #$0010	                LDY #DIRENTRY.CREATE_DATE
.39534a		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.39534c		a0 18 00	ldy #$0018	                LDY #DIRENTRY.MODIFIED_DATE     ; And DOS_DIR_PTR->MODIFIED_DATE
.39534f		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.395351		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME       ; DOS_DIR_PTR->CREATE_TIME := DOS_FD_PTR->CREATE_TIME
.395354		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395356		a0 0e 00	ldy #$000e	                LDY #DIRENTRY.CREATE_TIME
.395359		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.39535b		a0 16 00	ldy #$0016	                LDY #DIRENTRY.MODIFIED_TIME     ; And DOS_DIR_PTR->MODIFIED_TIME
.39535e		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.395360		c2 20		rep #$20	                REP #$20        ; set A long
.395362		22 22 44 39	jsl $394422	                JSL DOS_DIRWRITE
.395366		b0 0b		bcs $395373	                BCS ret_success
.395368		80 04		bra $39536e	                BRA pass_failure
.39536a						ret_failure
.39536a		e2 20		sep #$20	                SEP #$20        ; set A short
.39536c		85 0e		sta $032e	                STA DOS_STATUS
.39536e		28		plp		pass_failure    PLP
.39536f		2b		pld		                PLD
.395370		ab		plb		                PLB
.395371		18		clc		                CLC
.395372		6b		rtl		                RTL
.395373						ret_success
.395373		e2 20		sep #$20	                SEP #$20        ; set A short
.395375		64 0e		stz $032e	                STZ DOS_STATUS
.395377		28		plp		                PLP
.395378		2b		pld		                PLD
.395379		ab		plb		                PLB
.39537a		38		sec		                SEC
.39537b		6b		rtl		                RTL
.39537c						DOS_COPYPATH
.39537c		da		phx		                PHX
.39537d		5a		phy		                PHY
.39537e		8b		phb		                PHB
.39537f		0b		phd		                PHD
.395380		08		php		                PHP
.395381		48		pha		                PHA             ; begin setdbr macro
.395382		08		php		                PHP
.395383		e2 20		sep #$20	                SEP #$20        ; set A short
.395385		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395387		48		pha		                PHA
.395388		ab		plb		                PLB
.395389		28		plp		                PLP
.39538a		68		pla		                PLA             ; end setdbr macro
.39538b		48		pha		                PHA             ; begin setdp macro
.39538c		08		php		                PHP
.39538d		c2 20		rep #$20	                REP #$20        ; set A long
.39538f		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395392		5b		tcd		                TCD
.395393		28		plp		                PLP
.395394		68		pla		                PLA             ; end setdp macro
.395395		c2 30		rep #$30	                REP #$30        ; set A&X long
.395397		a9 00 00	lda #$0000	                LDA #0                  ; Set the DOS_PATH_BUFF to all zeros
.39539a		a2 00 00	ldx #$0000	                LDX #0
.39539d		95 e0		sta $0400,x	clr_loop        STA DOS_PATH_BUFF,X
.39539f		e8		inx		                INX
.3953a0		e8		inx		                INX
.3953a1		e0 00 01	cpx #$0100	                CPX #256
.3953a4		d0 f7		bne $39539d	                BNE clr_loop
.3953a6		a5 20		lda $0340	                LDA DOS_FD_PTR          ; Is the DOS_FD_PTR null?
.3953a8		d0 04		bne $3953ae	                BNE get_path            ; No: attempt to fetch the path
.3953aa		a5 22		lda $0342	                LDA DOS_FD_PTR+2
.3953ac		f0 27		beq $3953d5	                BEQ done                ; Yes: return an empty buffer
.3953ae		a0 02 00	ldy #$0002	get_path        LDY #FILEDESC.PATH      ; Get the path buffer
.3953b1		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3953b3		85 28		sta $0348	                STA DOS_TEMP
.3953b5		c8		iny		                INY
.3953b6		c8		iny		                INY
.3953b7		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3953b9		85 2a		sta $034a	                STA DOS_TEMP+2
.3953bb		a5 28		lda $0348	                LDA DOS_TEMP            ; Is the path pointer NULL?
.3953bd		d0 04		bne $3953c3	                BNE start_copy          ; No: start copying it
.3953bf		a5 2a		lda $034a	                LDA DOS_TEMP+2
.3953c1		f0 12		beq $3953d5	                BEQ done                ; Yes: return an empty buffer
.3953c3						start_copy
.3953c3		e2 20		sep #$20	                SEP #$20        ; set A short
.3953c5		a2 00 00	ldx #$0000	                LDX #0
.3953c8		a0 00 00	ldy #$0000	                LDY #0
.3953cb		b7 28		lda [$0348],y	loop            LDA [DOS_TEMP],Y
.3953cd		95 e0		sta $0400,x	                STA DOS_PATH_BUFF,X
.3953cf		f0 04		beq $3953d5	                BEQ done
.3953d1		e8		inx		                INX
.3953d2		c8		iny		                INY
.3953d3		d0 f6		bne $3953cb	                BNE loop
.3953d5		28		plp		done            PLP
.3953d6		2b		pld		                PLD
.3953d7		ab		plb		                PLB
.3953d8		7a		ply		                PLY
.3953d9		fa		plx		                PLX
.3953da		6b		rtl		                RTL

;******  Return to file: src\sdos.asm

.3953db						DOS_TEST
.3953db		8b		phb		                PHB
.3953dc		0b		phd		                PHD
.3953dd		08		php		                PHP
.3953de		48		pha		                PHA             ; begin setdbr macro
.3953df		08		php		                PHP
.3953e0		e2 20		sep #$20	                SEP #$20        ; set A short
.3953e2		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.3953e4		48		pha		                PHA
.3953e5		ab		plb		                PLB
.3953e6		28		plp		                PLP
.3953e7		68		pla		                PLA             ; end setdbr macro
.3953e8		48		pha		                PHA             ; begin setdp macro
.3953e9		08		php		                PHP
.3953ea		c2 20		rep #$20	                REP #$20        ; set A long
.3953ec		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3953ef		5b		tcd		                TCD
.3953f0		28		plp		                PLP
.3953f1		68		pla		                PLA             ; end setdp macro
.3953f2		c2 30		rep #$30	                REP #$30        ; set A&X long
.3953f4		a9 1a 54	lda #$541a	                LDA #<>src_file
.3953f7		8f 64 03 00	sta $000364	                STA @l DOS_STR1_PTR
.3953fb		a9 39 00	lda #$0039	                LDA #`src_file
.3953fe		8f 66 03 00	sta $000366	                STA @l DOS_STR1_PTR+2
.395402		a9 27 54	lda #$5427	                LDA #<>dst_file
.395405		8f 68 03 00	sta $000368	                STA @l DOS_STR2_PTR
.395409		a9 39 00	lda #$0039	                LDA #`dst_file
.39540c		8f 6a 03 00	sta $00036a	                STA @l DOS_STR2_PTR+2
.395410		22 bb 5a 39	jsl $395abb	                JSL IF_COPY
.395414		b0 00		bcs $395416	                BCS done
.395416		28		plp		done            PLP
.395417		2b		pld		                PLD
.395418		ab		plb		                PLB
.395419		6b		rtl		                RTL
>39541a		40 73 3a 68 65 6c 6c 6f		src_file        .null "@s:hello.bas"
>395422		2e 62 61 73 00
>395427		40 73 3a 68 65 6c 6c 6f		dst_file        .null "@s:hello2.bas"
>39542f		32 2e 62 61 73 00
.395435						IF_OPEN
.395435		da		phx		                PHX
.395436		5a		phy		                PHY
.395437		0b		phd		                PHD
.395438		8b		phb		                PHB
.395439		08		php		                PHP
.39543a		48		pha		                PHA             ; begin setdbr macro
.39543b		08		php		                PHP
.39543c		e2 20		sep #$20	                SEP #$20        ; set A short
.39543e		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395440		48		pha		                PHA
.395441		ab		plb		                PLB
.395442		28		plp		                PLP
.395443		68		pla		                PLA             ; end setdbr macro
.395444		48		pha		                PHA             ; begin setdp macro
.395445		08		php		                PHP
.395446		c2 20		rep #$20	                REP #$20        ; set A long
.395448		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39544b		5b		tcd		                TCD
.39544c		28		plp		                PLP
.39544d		68		pla		                PLA             ; end setdp macro
.39544e		e2 20		sep #$20	                SEP #$20        ; set A short
.395450		a0 00 00	ldy #$0000	                LDY #FILEDESC.STATUS            ; Get the status to make sure a open is ok
.395453		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395455		89 38		bit #$38	                BIT #FD_STAT_OPEN
.395457		f0 05		beq $39545e	                BEQ ok_to_open
.395459		a9 0f		lda #$0f	                LDA #DOS_ERR_OPEN               ; If already open: throw an error
.39545b		82 1c 05	brl $39597a	                BRL IF_FAILURE
.39545e		22 7c 53 39	jsl $39537c	ok_to_open      JSL DOS_COPYPATH                ; Copy the path to the path buffer
.395462		22 d2 49 39	jsl $3949d2	                JSL DOS_FINDFILE                ; Attempt to find the file
.395466		b0 03		bcs $39546b	                BCS is_found                    ; If OK: we found the file
.395468		82 13 05	brl $39597e	                BRL IF_PASSFAILURE              ; Otherwise: pass the failure up the chain
.39546b						is_found
.39546b		e2 20		sep #$20	                SEP #$20        ; set A short
.39546d		a0 01 00	ldy #$0001	                LDY #FILEDESC.DEV               ; Set the device in the file descriptor
.395470		a5 01		lda $0321	                LDA BIOS_DEV
.395472		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395474		c2 20		rep #$20	                REP #$20        ; set A long
.395476		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER            ; Set the buffer point to the one provided in the file
.395479		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.39547b		85 1c		sta $033c	                STA DOS_BUFF_PTR
.39547d		c8		iny		                INY
.39547e		c8		iny		                INY
.39547f		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395481		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
.395483		22 ec 47 39	jsl $3947ec	                JSL DOS_GETCLUSTER              ; Attempt to load the cluster
.395487		b0 03		bcs $39548c	                BCS read_cluster
.395489		82 f2 04	brl $39597e	                BRL IF_PASSFAILURE
.39548c		a0 0a 00	ldy #$000a	read_cluster    LDY #FILEDESC.FIRST_CLUSTER     ; Set the first cluster in the file descriptor
.39548f		a5 10		lda $0330	                LDA DOS_CLUS_ID
.395491		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395493		c8		iny		                INY
.395494		c8		iny		                INY
.395495		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.395497		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395499		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; Set the current cluster in the file descriptor
.39549c		a5 10		lda $0330	                LDA DOS_CLUS_ID
.39549e		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3954a0		c8		iny		                INY
.3954a1		c8		iny		                INY
.3954a2		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.3954a4		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3954a6		a0 1c 00	ldy #$001c	                LDY #DIRENTRY.SIZE              ; Copy the filesize from the directory entry to the file descriptor
.3954a9		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
.3954ab		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE
.3954ae		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3954b0		a0 1e 00	ldy #$001e	                LDY #DIRENTRY.SIZE+2
.3954b3		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
.3954b5		a0 14 00	ldy #$0014	                LDY #FILEDESC.SIZE+2
.3954b8		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3954ba		e2 20		sep #$20	                SEP #$20        ; set A short
.3954bc		a0 00 00	ldy #$0000	                LDY #FILEDESC.STATUS            ; Mark file as open and readable
.3954bf		a9 39		lda #$39	                LDA #FD_STAT_OPEN | FD_STAT_READ
.3954c1		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
.3954c3		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3954c5		82 bd 04	brl $395985	                BRL IF_SUCCESS
.3954c8						IF_CREATE
.3954c8		da		phx		                PHX
.3954c9		5a		phy		                PHY
.3954ca		0b		phd		                PHD
.3954cb		8b		phb		                PHB
.3954cc		08		php		                PHP
.3954cd		48		pha		                PHA             ; begin setdbr macro
.3954ce		08		php		                PHP
.3954cf		e2 20		sep #$20	                SEP #$20        ; set A short
.3954d1		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.3954d3		48		pha		                PHA
.3954d4		ab		plb		                PLB
.3954d5		28		plp		                PLP
.3954d6		68		pla		                PLA             ; end setdbr macro
.3954d7		48		pha		                PHA             ; begin setdp macro
.3954d8		08		php		                PHP
.3954d9		c2 20		rep #$20	                REP #$20        ; set A long
.3954db		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3954de		5b		tcd		                TCD
.3954df		28		plp		                PLP
.3954e0		68		pla		                PLA             ; end setdp macro
.3954e1		22 4f 52 39	jsl $39524f	                JSL DOS_CREATE                  ; Attempt to create the file
.3954e5		90 18		bcc $3954ff	                BCC pass_failure                ; If it fails: pass the failure up the chain
.3954e7		c2 30		rep #$30	                REP #$30        ; set A&X long
.3954e9		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; Sets the current cluster to 0 to make sure the next write appends
.3954ec		a9 00 00	lda #$0000	                LDA #0
.3954ef		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3954f1		c8		iny		                INY
.3954f2		c8		iny		                INY
.3954f3		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.3954f5		e2 20		sep #$20	                SEP #$20        ; set A short
.3954f7		a0 00 00	ldy #$0000	                LDY #FILEDESC.STATUS
.3954fa		a9 3a		lda #$3a	                LDA #FD_STAT_OPEN | FD_STAT_WRITE   ; Set the file to open and APPEND only
.3954fc		82 86 04	brl $395985	                BRL IF_SUCCESS
.3954ff		82 78 04	brl $39597a	pass_failure    BRL IF_FAILURE
.395502						IF_CLOSE
.395502		da		phx		                PHX
.395503		5a		phy		                PHY
.395504		0b		phd		                PHD
.395505		8b		phb		                PHB
.395506		08		php		                PHP
.395507		48		pha		                PHA             ; begin setdbr macro
.395508		08		php		                PHP
.395509		e2 20		sep #$20	                SEP #$20        ; set A short
.39550b		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.39550d		48		pha		                PHA
.39550e		ab		plb		                PLB
.39550f		28		plp		                PLP
.395510		68		pla		                PLA             ; end setdbr macro
.395511		48		pha		                PHA             ; begin setdp macro
.395512		08		php		                PHP
.395513		c2 20		rep #$20	                REP #$20        ; set A long
.395515		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395518		5b		tcd		                TCD
.395519		28		plp		                PLP
.39551a		68		pla		                PLA             ; end setdp macro
.39551b		e2 20		sep #$20	                SEP #$20        ; set A short
.39551d		a0 00 00	ldy #$0000	                LDY #FILEDESC.STATUS            ; Check to see if we were writing the file
.395520		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395522		89 02		bit #$02	                BIT #FD_STAT_WRITE
.395524		f0 09		beq $39552f	                BEQ set_flag                    ; No, just mark it closed
.395526		22 9b 55 39	jsl $39559b	                JSL IF_WRITE                    ; Attempt to write the cluster
.39552a		b0 03		bcs $39552f	                BCS set_flag
.39552c		82 4f 04	brl $39597e	                BRL IF_PASSFAILURE              ; If there was a problem, pass it up the chain
.39552f		22 71 5a 39	jsl $395a71	set_flag        JSL IF_FREEFD                   ; Free the file descriptor as well
.395533		82 4f 04	brl $395985	                BRL IF_SUCCESS
.395536						IF_READ
.395536		da		phx		                PHX
.395537		5a		phy		                PHY
.395538		0b		phd		                PHD
.395539		8b		phb		                PHB
.39553a		08		php		                PHP
.39553b		48		pha		                PHA             ; begin setdbr macro
.39553c		08		php		                PHP
.39553d		e2 20		sep #$20	                SEP #$20        ; set A short
.39553f		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395541		48		pha		                PHA
.395542		ab		plb		                PLB
.395543		28		plp		                PLP
.395544		68		pla		                PLA             ; end setdbr macro
.395545		48		pha		                PHA             ; begin setdp macro
.395546		08		php		                PHP
.395547		c2 20		rep #$20	                REP #$20        ; set A long
.395549		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39554c		5b		tcd		                TCD
.39554d		28		plp		                PLP
.39554e		68		pla		                PLA             ; end setdp macro
.39554f		c2 10		rep #$10	                REP #$10        ; set X long
.395551		e2 20		sep #$20	                SEP #$20        ; set A short
.395553						get_dev
.395553		e2 20		sep #$20	                SEP #$20        ; set A short
.395555		a0 01 00	ldy #$0001	                LDY #FILEDESC.DEV               ; Get the device number from the file descriptor
.395558		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.39555a		85 01		sta $0321	                STA BIOS_DEV
.39555c		22 54 45 39	jsl $394554	                JSL DOS_MOUNT                   ; Make sure the device is mounted (if needed)
.395560		c2 20		rep #$20	                REP #$20        ; set A long
.395562		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; Get the file's current cluster
.395565		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395567		85 10		sta $0330	                STA DOS_CLUS_ID
.395569		c8		iny		                INY
.39556a		c8		iny		                INY
.39556b		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.39556d		85 12		sta $0332	                STA DOS_CLUS_ID+2
.39556f		22 fc 4b 39	jsl $394bfc	                JSL NEXTCLUSTER                 ; Find the next cluster of the file
.395573		90 13		bcc $395588	                BCC pass_failure                ; If not OK: pass the failure up the chain
.395575		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER            ; Get the pointer to the file's cluster buffer
.395578		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.39557a		85 1c		sta $033c	                STA DOS_BUFF_PTR
.39557c		c8		iny		                INY
.39557d		c8		iny		                INY
.39557e		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395580		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
.395582		22 ec 47 39	jsl $3947ec	                JSL DOS_GETCLUSTER              ; Get the cluster
.395586		b0 03		bcs $39558b	                BCS ret_success                 ; If ok: return success
.395588						pass_failure
.395588		82 f3 03	brl $39597e	                BRL IF_PASSFAILURE              ; Otherwise: bubble up the failure
.39558b		a0 06 00	ldy #$0006	ret_success     LDY #FILEDESC.CLUSTER           ; Save the new cluster as the file's current cluster
.39558e		a5 10		lda $0330	                LDA DOS_CLUS_ID
.395590		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395592		c8		iny		                INY
.395593		c8		iny		                INY
.395594		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.395596		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395598		82 ea 03	brl $395985	                BRL IF_SUCCESS
.39559b						IF_WRITE
.39559b		da		phx		                PHX
.39559c		5a		phy		                PHY
.39559d		0b		phd		                PHD
.39559e		8b		phb		                PHB
.39559f		08		php		                PHP
.3955a0		48		pha		                PHA             ; begin setdbr macro
.3955a1		08		php		                PHP
.3955a2		e2 20		sep #$20	                SEP #$20        ; set A short
.3955a4		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.3955a6		48		pha		                PHA
.3955a7		ab		plb		                PLB
.3955a8		28		plp		                PLP
.3955a9		68		pla		                PLA             ; end setdbr macro
.3955aa		48		pha		                PHA             ; begin setdp macro
.3955ab		08		php		                PHP
.3955ac		c2 20		rep #$20	                REP #$20        ; set A long
.3955ae		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3955b1		5b		tcd		                TCD
.3955b2		28		plp		                PLP
.3955b3		68		pla		                PLA             ; end setdp macro
.3955b4		c2 10		rep #$10	                REP #$10        ; set X long
.3955b6		e2 20		sep #$20	                SEP #$20        ; set A short
.3955b8		a0 01 00	ldy #$0001	get_dev         LDY #FILEDESC.DEV               ; Get the device number from the file descriptor
.3955bb		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3955bd		85 01		sta $0321	                STA BIOS_DEV
.3955bf		22 54 45 39	jsl $394554	                JSL DOS_MOUNT                   ; Make sure the device is mounted (if needed)
.3955c3		c2 20		rep #$20	                REP #$20        ; set A long
.3955c5		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER            ; Get the pointer to the file's cluster buffer
.3955c8		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3955ca		85 1c		sta $033c	                STA DOS_BUFF_PTR
.3955cc		c8		iny		                INY
.3955cd		c8		iny		                INY
.3955ce		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3955d0		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
.3955d2		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; Get the file's current cluster
.3955d5		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3955d7		85 10		sta $0330	                STA DOS_CLUS_ID
.3955d9		c8		iny		                INY
.3955da		c8		iny		                INY
.3955db		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3955dd		85 12		sta $0332	                STA DOS_CLUS_ID+2
.3955df		d0 1a		bne $3955fb	                BNE rewrite_cluster             ; If the cluster ID <> 0, overwrite it
.3955e1		a5 10		lda $0330	                LDA DOS_CLUS_ID
.3955e3		d0 16		bne $3955fb	                BNE rewrite_cluster
.3955e5		a0 0a 00	ldy #$000a	                LDY #FILEDESC.FIRST_CLUSTER     ; Get the file's first cluster
.3955e8		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3955ea		85 10		sta $0330	                STA DOS_CLUS_ID
.3955ec		c8		iny		                INY
.3955ed		c8		iny		                INY
.3955ee		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3955f0		85 12		sta $0332	                STA DOS_CLUS_ID+2
.3955f2		22 1d 50 39	jsl $39501d	                JSL DOS_APPENDCLUS              ; Append the cluster
.3955f6		b0 0c		bcs $395604	                BCS ret_success                 ; If OK: return success
.3955f8		82 83 03	brl $39597e	                BRL IF_PASSFAILURE              ; Otherwise: bubble up the failure
.3955fb		22 29 48 39	jsl $394829	rewrite_cluster JSL DOS_PUTCLUSTER              ; Over-write the cluster
.3955ff		b0 03		bcs $395604	                BCS ret_success                 ; If ok: return success
.395601		82 7a 03	brl $39597e	pass_failure    BRL IF_PASSFAILURE              ; Otherwise: bubble up the failure
.395604		82 7e 03	brl $395985	ret_success     BRL IF_SUCCESS
.395607						IF_DIROPEN
.395607		da		phx		                PHX
.395608		5a		phy		                PHY
.395609		0b		phd		                PHD
.39560a		8b		phb		                PHB
.39560b		08		php		                PHP
.39560c		48		pha		                PHA             ; begin setdbr macro
.39560d		08		php		                PHP
.39560e		e2 20		sep #$20	                SEP #$20        ; set A short
.395610		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395612		48		pha		                PHA
.395613		ab		plb		                PLB
.395614		28		plp		                PLP
.395615		68		pla		                PLA             ; end setdbr macro
.395616		48		pha		                PHA             ; begin setdp macro
.395617		08		php		                PHP
.395618		c2 20		rep #$20	                REP #$20        ; set A long
.39561a		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39561d		5b		tcd		                TCD
.39561e		28		plp		                PLP
.39561f		68		pla		                PLA             ; end setdp macro
.395620		c2 30		rep #$30	                REP #$30        ; set A&X long
.395622		22 7c 53 39	jsl $39537c	                JSL DOS_COPYPATH            ; Copy the path from the file descriptor to the path buffer
.395626		22 3a 49 39	jsl $39493a	                JSL DOS_PARSE_PATH          ; Parse the path
.39562a		22 54 45 39	jsl $394554	                JSL DOS_MOUNT               ; Make sure we've mounted the SDC.
.39562e		b0 03		bcs $395633	                BCS get_root_dir            ; If successful: get the root directory
.395630		82 4b 03	brl $39597e	                BRL IF_PASSFAILURE          ; Otherwise: pass the error up the chain
.395633						get_root_dir
.395633		c2 30		rep #$30	                REP #$30        ; set A&X long
.395635		22 09 42 39	jsl $394209	                JSL DOS_DIROPEN
.395639		b0 03		bcs $39563e	                BCS success
.39563b		82 40 03	brl $39597e	                BRL IF_PASSFAILURE
.39563e		82 44 03	brl $395985	success         BRL IF_SUCCESS
.395641						IF_DIRNEXT
.395641		5c a3 42 39	jmp $3942a3	                JML DOS_DIRNEXT
.395645						IF_DELETE
.395645		da		phx		                PHX
.395646		5a		phy		                PHY
.395647		0b		phd		                PHD
.395648		8b		phb		                PHB
.395649		08		php		                PHP
.39564a		48		pha		                PHA             ; begin setdbr macro
.39564b		08		php		                PHP
.39564c		e2 20		sep #$20	                SEP #$20        ; set A short
.39564e		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395650		48		pha		                PHA
.395651		ab		plb		                PLB
.395652		28		plp		                PLP
.395653		68		pla		                PLA             ; end setdbr macro
.395654		48		pha		                PHA             ; begin setdp macro
.395655		08		php		                PHP
.395656		c2 20		rep #$20	                REP #$20        ; set A long
.395658		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39565b		5b		tcd		                TCD
.39565c		28		plp		                PLP
.39565d		68		pla		                PLA             ; end setdp macro
.39565e		c2 30		rep #$30	                REP #$30        ; set A&X long
.395660		22 d2 49 39	jsl $3949d2	                JSL DOS_FINDFILE
.395664		b0 03		bcs $395669	                BCS get_first_clus
.395666		82 15 03	brl $39597e	                BRL IF_PASSFAILURE
.395669						get_first_clus
.395669		a0 1a 00	ldy #$001a	                LDY #DIRENTRY.CLUSTER_L
.39566c		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
.39566e		85 10		sta $0330	                STA DOS_CLUS_ID
.395670		a0 14 00	ldy #$0014	                LDY #DIRENTRY.CLUSTER_H
.395673		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
.395675		85 12		sta $0332	                STA DOS_CLUS_ID+2
.395677		a5 10		lda $0330	                LDA DOS_CLUS_ID
.395679		8d 2a a0	sta $38a02a	                STA DOS_CURR_CLUS
.39567c		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.39567e		8d 2c a0	sta $38a02c	                STA DOS_CURR_CLUS+2
.395681		22 fc 4b 39	jsl $394bfc	del_loop        JSL NEXTCLUSTER
.395685		90 2f		bcc $3956b6	                BCC del_one
.395687		a5 10		lda $0330	                LDA DOS_CLUS_ID
.395689		8d 2e a0	sta $38a02e	                STA DOS_NEXT_CLUS
.39568c		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
.39568e		8d 30 a0	sta $38a030	                STA DOS_NEXT_CLUS+2
.395691		ad 2a a0	lda $38a02a	                LDA DOS_CURR_CLUS
.395694		85 10		sta $0330	                STA DOS_CLUS_ID
.395696		ad 2c a0	lda $38a02c	                LDA DOS_CURR_CLUS+2
.395699		85 12		sta $0332	                STA DOS_CLUS_ID+2
.39569b		22 dd 4f 39	jsl $394fdd	                JSL DELCLUSTER32
.39569f		b0 03		bcs $3956a4	                BCS go_next
.3956a1		82 da 02	brl $39597e	                BRL IF_PASSFAILURE
.3956a4						go_next
.3956a4		ad 2e a0	lda $38a02e	                LDA DOS_NEXT_CLUS
.3956a7		85 10		sta $0330	                STA DOS_CLUS_ID
.3956a9		8d 2a a0	sta $38a02a	                STA DOS_CURR_CLUS
.3956ac		ad 30 a0	lda $38a030	                LDA DOS_NEXT_CLUS+2
.3956af		85 12		sta $0332	                STA DOS_CLUS_ID+2
.3956b1		8d 2c a0	sta $38a02c	                STA DOS_CURR_CLUS+2
.3956b4		80 cb		bra $395681	                BRA del_loop
.3956b6						del_one
.3956b6		ad 2a a0	lda $38a02a	                LDA DOS_CURR_CLUS
.3956b9		85 10		sta $0330	                STA DOS_CLUS_ID
.3956bb		ad 2c a0	lda $38a02c	                LDA DOS_CURR_CLUS+2
.3956be		85 12		sta $0332	                STA DOS_CLUS_ID+2
.3956c0		22 37 4f 39	jsl $394f37	                JSL DELCLUSTER
.3956c4		b0 03		bcs $3956c9	                BCS free_dir_entry
.3956c6		82 b5 02	brl $39597e	                BRL IF_PASSFAILURE
.3956c9						free_dir_entry
.3956c9		e2 20		sep #$20	                SEP #$20        ; set A short
.3956cb		a0 00 00	ldy #$0000	                LDY #DIRENTRY.SHORTNAME         ; Flag the directory entry as deleted
.3956ce		a9 e5		lda #$e5	                LDA #DOS_DIR_ENT_UNUSED
.3956d0		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
.3956d2		22 22 44 39	jsl $394422	                JSL DOS_DIRWRITE                ; Write the directory entry back
.3956d6		b0 03		bcs $3956db	                BCS ret_success
.3956d8		82 a3 02	brl $39597e	                BRL IF_PASSFAILURE
.3956db		82 a7 02	brl $395985	ret_success     BRL IF_SUCCESS
.3956de						IF_DIRREAD
.3956de		da		phx		                PHX
.3956df		5a		phy		                PHY
.3956e0		0b		phd		                PHD
.3956e1		8b		phb		                PHB
.3956e2		08		php		                PHP
.3956e3		48		pha		                PHA             ; begin setdbr macro
.3956e4		08		php		                PHP
.3956e5		e2 20		sep #$20	                SEP #$20        ; set A short
.3956e7		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.3956e9		48		pha		                PHA
.3956ea		ab		plb		                PLB
.3956eb		28		plp		                PLP
.3956ec		68		pla		                PLA             ; end setdbr macro
.3956ed		48		pha		                PHA             ; begin setdp macro
.3956ee		08		php		                PHP
.3956ef		c2 20		rep #$20	                REP #$20        ; set A long
.3956f1		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3956f4		5b		tcd		                TCD
.3956f5		28		plp		                PLP
.3956f6		68		pla		                PLA             ; end setdp macro
.3956f7		c2 30		rep #$30	                REP #$30        ; set A&X long
.3956f9		22 d2 49 39	jsl $3949d2	                JSL DOS_FINDFILE
.3956fd		b0 03		bcs $395702	                BCS success
.3956ff		82 78 02	brl $39597a	                BRL IF_FAILURE
.395702		82 80 02	brl $395985	success         BRL IF_SUCCESS
.395705						IF_DIRWRITE
.395705		5c 22 44 39	jmp $394422	                JML DOS_DIRWRITE
.395709						IF_LOAD
.395709		da		phx		                PHX
.39570a		5a		phy		                PHY
.39570b		0b		phd		                PHD
.39570c		8b		phb		                PHB
.39570d		08		php		                PHP
.39570e		48		pha		                PHA             ; begin setdbr macro
.39570f		08		php		                PHP
.395710		e2 20		sep #$20	                SEP #$20        ; set A short
.395712		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395714		48		pha		                PHA
.395715		ab		plb		                PLB
.395716		28		plp		                PLP
.395717		68		pla		                PLA             ; end setdbr macro
.395718		48		pha		                PHA             ; begin setdp macro
.395719		08		php		                PHP
.39571a		c2 20		rep #$20	                REP #$20        ; set A long
.39571c		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39571f		5b		tcd		                TCD
.395720		28		plp		                PLP
.395721		68		pla		                PLA             ; end setdp macro
.395722		c2 30		rep #$30	                REP #$30        ; set A&X long
.395724		22 35 54 39	jsl $395435	                JSL IF_OPEN
.395728		b0 03		bcs $39572d	                BCS setup                   ; If success: start setting things up
.39572a		82 51 02	brl $39597e	                BRL IF_PASSFAILURE          ; Otherwise: pass the failure up the chain
.39572d						setup
.39572d		c2 20		rep #$20	                REP #$20        ; set A long
.39572f		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE          ; Record the size of the file in DOS_FILE_SIZE
.395732		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395734		85 2c		sta $034c	                STA DOS_FILE_SIZE
.395736		c8		iny		                INY
.395737		c8		iny		                INY
.395738		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.39573a		85 2e		sta $034e	                STA DOS_FILE_SIZE+2
.39573c		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER        ; Set up the source pointer
.39573f		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395741		85 30		sta $0350	                STA DOS_SRC_PTR
.395743		c8		iny		                INY
.395744		c8		iny		                INY
.395745		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395747		85 32		sta $0352	                STA DOS_SRC_PTR+2
.395749		a5 36		lda $0356	                LDA DOS_DST_PTR+2           ; Is there a destination address in RAM?
.39574b		c9 40 00	cmp #$0040	                CMP #$0040
.39574e		b0 04		bcs $395754	                BGE load_by_type            ; No: try to load it by type
.395750		5c 2f 58 39	jmp $39582f	                JML IF_LOADRAW              ; Otherwise, load it to the supplied destination
.395754		a0 08 00	ldy #$0008	load_by_type    LDY #8                      ; Point to the first extension byte
.395757		a2 00 00	ldx #$0000	                LDX #0                      ; and the first byte of the table
.39575a						type_loop
.39575a		e2 20		sep #$20	                SEP #$20        ; set A short
.39575c		bf a0 57 39	lda $3957a0,x	                LDA LOAD_TYPE_TABLE,X       ; Get 1st extension character of the entry
.395760		f0 37		beq $395799	                BEQ no_match                ; If NULL... we didn't get a match
.395762		d9 3a a0	cmp $38a03a,y	                CMP DOS_SHORT_NAME,Y        ; Get the character of the extension
.395765		d0 28		bne $39578f	                BNE next_entry              ; If they don't match, try the next entry
.395767		bf a1 57 39	lda $3957a1,x	                LDA LOAD_TYPE_TABLE+1,X     ; Get 2nd extension character of the entry
.39576b		d9 3b a0	cmp $38a03b,y	                CMP DOS_SHORT_NAME+1,Y      ; Get the 2nd character of the extension
.39576e		d0 1f		bne $39578f	                BNE next_entry              ; If they don't match, try the next entry
.395770		bf a2 57 39	lda $3957a2,x	                LDA LOAD_TYPE_TABLE+2,X     ; Get 3rd extension character of the entry
.395774		d9 3c a0	cmp $38a03c,y	                CMP DOS_SHORT_NAME+2,Y      ; Get the 3rd character of the extension
.395777		d0 16		bne $39578f	                BNE next_entry              ; If they don't match, try the next entry
.395779		c2 20		rep #$20	                REP #$20        ; set A long
.39577b		bf a3 57 39	lda $3957a3,x	                LDA LOAD_TYPE_TABLE+3,X     ; Get the low word of the address
.39577f		85 28		sta $0348	                STA DOS_TEMP                ; Save it to the jump vector
.395781		e2 20		sep #$20	                SEP #$20        ; set A short
.395783		bf a5 57 39	lda $3957a5,x	                LDA LOAD_TYPE_TABLE+5,X     ; Get the high byte of the address
.395787		85 2a		sta $034a	                STA DOS_TEMP+2              ; Save it to the jump vector
.395789		a2 00 00	ldx #$0000	                LDX #0
.39578c		dc 48 03	jmp [$0348]	                JML [DOS_TEMP]              ; Jump to the loading routine
.39578f						next_entry
.39578f		c2 30		rep #$30	                REP #$30        ; set A&X long
.395791		8a		txa		                TXA
.395792		18		clc		                CLC
.395793		69 06 00	adc #$0006	                ADC #6
.395796		aa		tax		                TAX
.395797		80 c1		bra $39575a	                BRA type_loop               ; And check it against the file
.395799						no_match
.395799		e2 20		sep #$20	                SEP #$20        ; set A short
.39579b		a9 11		lda #$11	                LDA #DOS_ERR_NOEXEC         ; Return an not-executable error
.39579d		82 da 01	brl $39597a	                BRL IF_FAILURE
>3957a0		50 47 58			LOAD_TYPE_TABLE .text "PGX"                 ; "PGX" --> IF_LOADPGX
>3957a3		a7 57				                .word <>IF_LOADPGX
>3957a5		39				                .byte `IF_LOADPGX
>3957a6		00				                .byte 0
.3957a7						IF_LOADPGX
.3957a7		c2 10		rep #$10	                REP #$10        ; set X long
.3957a9		e2 20		sep #$20	                SEP #$20        ; set A short
.3957ab		a0 00 00	ldy #$0000	                LDY #0
.3957ae		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y                 ; Check for "PGX" signature
.3957b0		c9 50		cmp #$50	                CMP #'P'
.3957b2		d0 15		bne $3957c9	                BNE fail_sig                        ; If not found, fail
.3957b4		c8		iny		                INY
.3957b5		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
.3957b7		c9 47		cmp #$47	                CMP #'G'
.3957b9		d0 0e		bne $3957c9	                BNE fail_sig
.3957bb		c8		iny		                INY
.3957bc		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
.3957be		c9 58		cmp #$58	                CMP #'X'
.3957c0		d0 07		bne $3957c9	                BNE fail_sig
.3957c2		c8		iny		                INY                                 ; Check for CPU and version code ($01 for 65816)
.3957c3		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
.3957c5		c9 01		cmp #$01	                CMP #$01
.3957c7		f0 17		beq $3957e0	                BEQ get_dest                        ; All passes: go to get the destination address
.3957c9		a9 10		lda #$10	fail_sig        LDA #DOS_ERR_PGXSIG                 ; Fail with a PGXSIG error code
.3957cb		22 7a 59 39	jsl $39597a	                JSL IF_FAILURE
.3957cf						adjust_size
.3957cf		c2 20		rep #$20	                REP #$20        ; set A long
.3957d1		38		sec		                SEC                                 ; Subtract the 8 bytes of the header from the file size
.3957d2		a5 2c		lda $034c	                LDA DOS_FILE_SIZE
.3957d4		e9 08 00	sbc #$0008	                SBC #8
.3957d7		85 2c		sta $034c	                STA DOS_FILE_SIZE
.3957d9		a5 2e		lda $034e	                LDA DOS_FILE_SIZE+2
.3957db		e9 00 00	sbc #$0000	                SBC #0
.3957de		85 2e		sta $034e	                STA DOS_FILE_SIZE+2
.3957e0						get_dest
.3957e0		c2 20		rep #$20	                REP #$20        ; set A long
.3957e2		c8		iny		                INY
.3957e3		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y                 ; Get low word of destination address
.3957e5		85 34		sta $0354	                STA DOS_DST_PTR                     ; And save it to the destination pointer
.3957e7		85 3c		sta $035c	                STA DOS_RUN_PTR                     ; And save it to the RUN pointer
.3957e9		c8		iny		                INY
.3957ea		c8		iny		                INY
.3957eb		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y                 ; Get high word of destination address
.3957ed		85 36		sta $0356	                STA DOS_DST_PTR+2
.3957ef		85 3e		sta $035e	                STA DOS_RUN_PTR+2
.3957f1		c8		iny		                INY                                 ; Point to the first data byte
.3957f2		c8		iny		                INY
.3957f3						copy_loop
.3957f3		e2 20		sep #$20	                SEP #$20        ; set A short
.3957f5		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y                 ; Read a byte from the file
.3957f7		87 34		sta [$0354]	                STA [DOS_DST_PTR]                   ; Write it to the destination
.3957f9		c2 20		rep #$20	                REP #$20        ; set A long
.3957fb		e6 34		inc $0354	                INC DOS_DST_PTR                     ; Move to the next destination location
.3957fd		d0 02		bne $395801	                BNE dec_file_size
.3957ff		e6 36		inc $0356	                INC DOS_DST_PTR+2
.395801		38		sec		dec_file_size   SEC                                 ; Count down the number of bytes to read
.395802		a5 2c		lda $034c	                LDA DOS_FILE_SIZE
.395804		e9 01 00	sbc #$0001	                SBC #1
.395807		85 2c		sta $034c	                STA DOS_FILE_SIZE
.395809		a5 2e		lda $034e	                LDA DOS_FILE_SIZE+2
.39580b		e9 00 00	sbc #$0000	                SBC #0
.39580e		85 2e		sta $034e	                STA DOS_FILE_SIZE+2
.395810		a5 2c		lda $034c	                LDA DOS_FILE_SIZE                   ; Are we at the end of the file?
.395812		d0 04		bne $395818	                BNE next_byte
.395814		a5 2e		lda $034e	                LDA DOS_FILE_SIZE+2
.395816		f0 14		beq $39582c	                BEQ done                            ; Yes: we're done
.395818		c8		iny		next_byte       INY                                 ; Otherwise, move to the next source location
.395819		cc 0e a0	cpy $38a00e	                CPY CLUSTER_SIZE                    ; Are we at the end of the cluster?
.39581c		d0 d5		bne $3957f3	                BNE copy_loop                       ; No: keep copying
.39581e		22 00 4d 39	jsl $394d00	                JSL DOS_READNEXT                    ; Yes: Load the next cluster
.395822		b0 03		bcs $395827	                BCS next_cluster
.395824		82 57 01	brl $39597e	                BRL IF_PASSFAILURE                  ; If failed: pass that up the chain
.395827		a0 00 00	ldy #$0000	next_cluster    LDY #0
.39582a		80 c7		bra $3957f3	                BRA copy_loop                       ; Go back to copying
.39582c		82 56 01	brl $395985	done            BRL IF_SUCCESS
.39582f						IF_LOADRAW
.39582f		c2 30		rep #$30	                REP #$30        ; set A&X long
.395831		a0 00 00	ldy #$0000	copy_cluster    LDY #0
.395834						copy_loop
.395834		e2 20		sep #$20	                SEP #$20        ; set A short
.395836		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y         ; Copy byte from cluster to destination
.395838		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
.39583a		c2 20		rep #$20	                REP #$20        ; set A long
.39583c		38		sec		                SEC                         ; Count down the number of bytes left
.39583d		a5 2c		lda $034c	                LDA DOS_FILE_SIZE
.39583f		e9 01 00	sbc #$0001	                SBC #1
.395842		85 2c		sta $034c	                STA DOS_FILE_SIZE
.395844		a5 2e		lda $034e	                LDA DOS_FILE_SIZE+2
.395846		e9 00 00	sbc #$0000	                SBC #0
.395849		85 2e		sta $034e	                STA DOS_FILE_SIZE+2
.39584b		d0 04		bne $395851	                BNE continue
.39584d		a5 2c		lda $034c	                LDA DOS_FILE_SIZE
.39584f		f0 1b		beq $39586c	                BEQ close_file              ; If not: we're done
.395851		c8		iny		continue        INY
.395852		cc 0e a0	cpy $38a00e	                CPY CLUSTER_SIZE            ; Are we done with the cluster?
.395855		d0 dd		bne $395834	                BNE copy_loop               ; No: keep processing the bytes
.395857		18		clc		                CLC                         ; Advance the destination pointer to the next chunk of memory
.395858		a5 34		lda $0354	                LDA DOS_DST_PTR
.39585a		6d 0e a0	adc $38a00e	                ADC CLUSTER_SIZE
.39585d		85 34		sta $0354	                STA DOS_DST_PTR
.39585f		a5 36		lda $0356	                LDA DOS_DST_PTR+2
.395861		69 00 00	adc #$0000	                ADC #0
.395864		85 36		sta $0356	                STA DOS_DST_PTR+2
.395866		22 36 55 39	jsl $395536	                JSL IF_READ                 ; Yes: load the next cluster
.39586a		b0 c5		bcs $395831	                BCS copy_cluster            ; And start copying it
.39586c						close_file
.39586c		82 16 01	brl $395985	ret_success     BRL IF_SUCCESS
.39586f						IF_NULLBUFFER
.39586f		5a		phy		                PHY
.395870		8b		phb		                PHB
.395871		0b		phd		                PHD
.395872		08		php		                PHP
.395873		48		pha		                PHA             ; begin setdbr macro
.395874		08		php		                PHP
.395875		e2 20		sep #$20	                SEP #$20        ; set A short
.395877		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395879		48		pha		                PHA
.39587a		ab		plb		                PLB
.39587b		28		plp		                PLP
.39587c		68		pla		                PLA             ; end setdbr macro
.39587d		48		pha		                PHA             ; begin setdp macro
.39587e		08		php		                PHP
.39587f		c2 20		rep #$20	                REP #$20        ; set A long
.395881		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395884		5b		tcd		                TCD
.395885		28		plp		                PLP
.395886		68		pla		                PLA             ; end setdp macro
.395887		c2 30		rep #$30	                REP #$30        ; set A&X long
.395889		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER
.39588c		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.39588e		85 28		sta $0348	                STA DOS_TEMP
.395890		c8		iny		                INY
.395891		c8		iny		                INY
.395892		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395894		85 2a		sta $034a	                STA DOS_TEMP+2
.395896		a0 00 00	ldy #$0000	                LDY #0
.395899		a9 00 00	lda #$0000	                LDA #0
.39589c		97 28		sta [$0348],y	loop            STA [DOS_TEMP],Y
.39589e		c8		iny		                INY
.39589f		c8		iny		                INY
.3958a0		c0 00 02	cpy #$0200	                CPY #DOS_SECTOR_SIZE
.3958a3		d0 f7		bne $39589c	                BNE loop
.3958a5		28		plp		                PLP
.3958a6		2b		pld		                PLD
.3958a7		ab		plb		                PLB
.3958a8		7a		ply		                PLY
.3958a9		6b		rtl		                RTL
.3958aa						IF_COPY2BUFF
.3958aa		5a		phy		                PHY
.3958ab		8b		phb		                PHB
.3958ac		0b		phd		                PHD
.3958ad		08		php		                PHP
.3958ae		48		pha		                PHA             ; begin setdbr macro
.3958af		08		php		                PHP
.3958b0		e2 20		sep #$20	                SEP #$20        ; set A short
.3958b2		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.3958b4		48		pha		                PHA
.3958b5		ab		plb		                PLB
.3958b6		28		plp		                PLP
.3958b7		68		pla		                PLA             ; end setdbr macro
.3958b8		48		pha		                PHA             ; begin setdp macro
.3958b9		08		php		                PHP
.3958ba		c2 20		rep #$20	                REP #$20        ; set A long
.3958bc		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3958bf		5b		tcd		                TCD
.3958c0		28		plp		                PLP
.3958c1		68		pla		                PLA             ; end setdp macro
.3958c2		c2 30		rep #$30	                REP #$30        ; set A&X long
.3958c4		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER
.3958c7		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3958c9		85 28		sta $0348	                STA DOS_TEMP
.3958cb		c8		iny		                INY
.3958cc		c8		iny		                INY
.3958cd		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.3958cf		85 2a		sta $034a	                STA DOS_TEMP+2
.3958d1		a0 00 00	ldy #$0000	                LDY #0
.3958d4						copy_loop
.3958d4		e2 20		sep #$20	                SEP #$20        ; set A short
.3958d6		a7 30		lda [$0350]	                LDA [DOS_SRC_PTR]           ; Copy a byte
.3958d8		97 28		sta [$0348],y	                STA [DOS_TEMP],Y
.3958da		c2 20		rep #$20	                REP #$20        ; set A long
.3958dc		e6 30		inc $0350	                INC DOS_SRC_PTR             ; Advance the source pointer
.3958de		d0 02		bne $3958e2	                BNE adv_dest
.3958e0		e6 32		inc $0352	                INC DOS_SRC_PTR+2
.3958e2		c8		iny		adv_dest        INY                         ; Count it
.3958e3		c0 00 02	cpy #$0200	                CPY #DOS_SECTOR_SIZE        ; Have we reached the limit?
.3958e6		f0 0c		beq $3958f4	                BEQ done                    ; Yes: we're done
.3958e8		a5 30		lda $0350	                LDA DOS_SRC_PTR             ; Check if we copied the last byte
.3958ea		c5 38		cmp $0358	                CMP DOS_END_PTR
.3958ec		d0 e6		bne $3958d4	                BNE copy_loop               ; No: keep copying
.3958ee		a5 32		lda $0352	                LDA DOS_SRC_PTR+2
.3958f0		c5 3a		cmp $035a	                CMP DOS_END_PTR+2
.3958f2		d0 e0		bne $3958d4	                BNE copy_loop
.3958f4		28		plp		done            PLP
.3958f5		2b		pld		                PLD
.3958f6		ab		plb		                PLB
.3958f7		7a		ply		                PLY
.3958f8		6b		rtl		                RTL
.3958f9						IF_SAVE
.3958f9		da		phx		                PHX
.3958fa		5a		phy		                PHY
.3958fb		0b		phd		                PHD
.3958fc		8b		phb		                PHB
.3958fd		08		php		                PHP
.3958fe		48		pha		                PHA             ; begin setdbr macro
.3958ff		08		php		                PHP
.395900		e2 20		sep #$20	                SEP #$20        ; set A short
.395902		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395904		48		pha		                PHA
.395905		ab		plb		                PLB
.395906		28		plp		                PLP
.395907		68		pla		                PLA             ; end setdbr macro
.395908		48		pha		                PHA             ; begin setdp macro
.395909		08		php		                PHP
.39590a		c2 20		rep #$20	                REP #$20        ; set A long
.39590c		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.39590f		5b		tcd		                TCD
.395910		28		plp		                PLP
.395911		68		pla		                PLA             ; end setdp macro
.395912		c2 30		rep #$30	                REP #$30        ; set A&X long
.395914		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE      ; DOS_FD_PTR->SIZE := DOS_END_PTR - DOS_SRC_PTR
.395917		38		sec		                SEC
.395918		a5 38		lda $0358	                LDA DOS_END_PTR
.39591a		e5 30		sbc $0350	                SBC DOS_SRC_PTR
.39591c		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.39591e		c8		iny		                INY
.39591f		c8		iny		                INY
.395920		a5 3a		lda $035a	                LDA DOS_END_PTR+2
.395922		e5 32		sbc $0352	                SBC DOS_SRC_PTR+2
.395924		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395926		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE      ; DOS_FD_PTR->SIZE++
.395929		18		clc		                CLC
.39592a		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.39592c		69 01 00	adc #$0001	                ADC #1
.39592f		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395931		90 09		bcc $39593c	                BCC first_block
.395933		c8		iny		                INY
.395934		c8		iny		                INY
.395935		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
.395937		69 00 00	adc #$0000	                ADC #0
.39593a		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.39593c		22 6f 58 39	jsl $39586f	first_block     JSL IF_NULLBUFFER       ; Fill FD buffer with NULL
.395940		22 aa 58 39	jsl $3958aa	                JSL IF_COPY2BUFF        ; Copy first (at most) 512 bytes of data to FD buffer
.395944		22 c8 54 39	jsl $3954c8	                JSL IF_CREATE           ; Create file.
.395948		b0 03		bcs $39594d	                BCS check_for_end
.39594a		82 31 00	brl $39597e	                BRL IF_PASSFAILURE      ; If we couldn't create the file, pass the failure up
.39594d		a5 30		lda $0350	check_for_end   LDA DOS_SRC_PTR         ; Check if we copied the last byte
.39594f		c5 38		cmp $0358	                CMP DOS_END_PTR
.395951		d0 06		bne $395959	                BNE next_block
.395953		a5 32		lda $0352	                LDA DOS_SRC_PTR+2
.395955		c5 3a		cmp $035a	                CMP DOS_END_PTR+2
.395957		f0 1d		beq $395976	                BEQ done                ; Yes: we're done
.395959		22 6f 58 39	jsl $39586f	next_block      JSL IF_NULLBUFFER       ; Fill FD buffer with NULL
.39595d		22 aa 58 39	jsl $3958aa	                JSL IF_COPY2BUFF        ; Copy next (at most) 512 bytes of data to FD buffer
.395961		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER   ; Make sure the CLUSTER is 0 to force an append
.395964		a9 00 00	lda #$0000	                LDA #0
.395967		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395969		c8		iny		                INY
.39596a		c8		iny		                INY
.39596b		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.39596d		22 9b 55 39	jsl $39559b	                JSL IF_WRITE            ; Append to the file
.395971		b0 da		bcs $39594d	                BCS check_for_end       ; And try again
.395973		82 08 00	brl $39597e	                BRL IF_PASSFAILURE      ; If we couldn't update the file, pass the failure up
.395976		5c 85 59 39	jmp $395985	done            JML IF_SUCCESS
.39597a						IF_FAILURE
.39597a		e2 20		sep #$20	                SEP #$20        ; set A short
.39597c		85 0e		sta $032e	                STA DOS_STATUS
.39597e		28		plp		IF_PASSFAILURE  PLP
.39597f		18		clc		                CLC
.395980		ab		plb		                PLB
.395981		2b		pld		                PLD
.395982		7a		ply		                PLY
.395983		fa		plx		                PLX
.395984		6b		rtl		                RTL
.395985						IF_SUCCESS
.395985		e2 20		sep #$20	                SEP #$20        ; set A short
.395987		64 00		stz $0320	                STZ BIOS_STATUS
.395989		64 0e		stz $032e	                STZ DOS_STATUS
.39598b		28		plp		                PLP
.39598c		38		sec		                SEC
.39598d		ab		plb		                PLB
.39598e		2b		pld		                PLD
.39598f		7a		ply		                PLY
.395990		fa		plx		                PLX
.395991		6b		rtl		                RTL
.395992						IF_RUN
.395992		da		phx		                PHX
.395993		5a		phy		                PHY
.395994		0b		phd		                PHD
.395995		8b		phb		                PHB
.395996		08		php		                PHP
.395997		48		pha		                PHA             ; begin setdbr macro
.395998		08		php		                PHP
.395999		e2 20		sep #$20	                SEP #$20        ; set A short
.39599b		a9 00		lda #$00	                LDA #0
.39599d		48		pha		                PHA
.39599e		ab		plb		                PLB
.39599f		28		plp		                PLP
.3959a0		68		pla		                PLA             ; end setdbr macro
.3959a1		48		pha		                PHA             ; begin setdp macro
.3959a2		08		php		                PHP
.3959a3		c2 20		rep #$20	                REP #$20        ; set A long
.3959a5		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.3959a8		5b		tcd		                TCD
.3959a9		28		plp		                PLP
.3959aa		68		pla		                PLA             ; end setdp macro
.3959ab		e2 20		sep #$20	                SEP #$20        ; set A short
.3959ad		c2 10		rep #$10	                REP #$10        ; set X long
.3959af		a9 00		lda #$00	                LDA #0                                  ; Zero out the file descriptor
.3959b1		a2 00 00	ldx #$0000	                LDX #0
.3959b4		9f 00 ad 38	sta $38ad00,x	clr_fd_loop     STA @l DOS_SPARE_FD,X
.3959b8		e8		inx		                INX
.3959b9		e0 20 00	cpx #$0020	                CPX #SIZE(FILEDESC)
.3959bc		d0 f6		bne $3959b4	                BNE clr_fd_loop
.3959be		c2 20		rep #$20	                REP #$20        ; set A long
.3959c0		a9 00 ab	lda #$ab00	                LDA #<>DOS_SPARE_SECTOR                 ; Set the buffer for the file descriptor
.3959c3		8f 0e ad 38	sta $38ad0e	                STA @l DOS_SPARE_FD+FILEDESC.BUFFER
.3959c7		a9 38 00	lda #$0038	                LDA #`DOS_SPARE_SECTOR
.3959ca		8f 10 ad 38	sta $38ad10	                STA @l DOS_SPARE_FD+FILEDESC.BUFFER+2
.3959ce		a5 40		lda $0360	                LDA DOS_RUN_PARAM                        ; Set the path for the file descriptor
.3959d0		8f 02 ad 38	sta $38ad02	                STA @l DOS_SPARE_FD+FILEDESC.PATH
.3959d4		a5 42		lda $0362	                LDA DOS_RUN_PARAM+2
.3959d6		8f 04 ad 38	sta $38ad04	                STA @l DOS_SPARE_FD+FILEDESC.PATH+2
.3959da		a9 00 00	lda #$0000	                LDA #0                                  ; Clear the run pointer
.3959dd		85 3c		sta $035c	                STA DOS_RUN_PTR                         ; This is used to check that we loaded an executable binary
.3959df		85 3e		sta $035e	                STA DOS_RUN_PTR+2
.3959e1		a9 00 ad	lda #$ad00	                LDA #<>DOS_SPARE_FD
.3959e4		85 20		sta $0340	                STA DOS_FD_PTR
.3959e6		a9 38 00	lda #$0038	                LDA #`DOS_SPARE_FD
.3959e9		85 22		sta $0342	                STA DOS_FD_PTR+2
.3959eb		a9 ff ff	lda #$ffff	                LDA #$FFFF                              ; We want to load to the address provided by the file
.3959ee		8f 54 03 00	sta $000354	                STA @l DOS_DST_PTR
.3959f2		8f 56 03 00	sta $000356	                STA @l DOS_DST_PTR+2
.3959f6		22 18 11 00	jsl $001118	                JSL F_LOAD                              ; Try to load the file
.3959fa		b0 14		bcs $395a10	                BCS try_execute
.3959fc		82 7f ff	brl $39597e	                BRL IF_PASSFAILURE                      ; On error: pass failure up the chain
.3959ff						chk_execute
.3959ff		c2 20		rep #$20	                REP #$20        ; set A long
.395a01		a5 3c		lda $035c	                LDA DOS_RUN_PTR                         ; Check to see if we got a startup address back
.395a03		d0 0b		bne $395a10	                BNE try_execute                         ; If so: call it
.395a05		a5 3e		lda $035e	                LDA DOS_RUN_PTR+2
.395a07		d0 07		bne $395a10	                BNE try_execute
.395a09		e2 20		sep #$20	                SEP #$20        ; set A short
.395a0b		a9 11		lda #$11	                LDA #DOS_ERR_NOEXEC                     ; If not: return an error that it's not executable
.395a0d		82 6a ff	brl $39597a	                BRL IF_FAILURE
.395a10						try_execute
.395a10		e2 20		sep #$20	                SEP #$20        ; set A short
.395a12		a9 5c		lda #$5c	                LDA #$5C                                ; Write a JML opcode
.395a14		85 3b		sta $035b	                STA DOS_RUN_PTR-1
.395a16		22 5b 03 00	jsl $00035b	                JSL DOS_RUN_PTR-1                       ; And call to it
.395a1a		82 68 ff	brl $395985	                BRL IF_SUCCESS                          ; Return success
.395a1d						IF_ALLOCFD
.395a1d		da		phx		                PHX
.395a1e		5a		phy		                PHY
.395a1f		0b		phd		                PHD
.395a20		8b		phb		                PHB
.395a21		08		php		                PHP
.395a22		48		pha		                PHA             ; begin setdbr macro
.395a23		08		php		                PHP
.395a24		e2 20		sep #$20	                SEP #$20        ; set A short
.395a26		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395a28		48		pha		                PHA
.395a29		ab		plb		                PLB
.395a2a		28		plp		                PLP
.395a2b		68		pla		                PLA             ; end setdbr macro
.395a2c		48		pha		                PHA             ; begin setdp macro
.395a2d		08		php		                PHP
.395a2e		c2 20		rep #$20	                REP #$20        ; set A long
.395a30		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395a33		5b		tcd		                TCD
.395a34		28		plp		                PLP
.395a35		68		pla		                PLA             ; end setdp macro
.395a36		c2 10		rep #$10	                REP #$10        ; set X long
.395a38		a2 00 00	ldx #$0000	                LDX #0                              ; Point to the first file descriptor
.395a3b						chk_fd
.395a3b		e2 20		sep #$20	                SEP #$20        ; set A short
.395a3d		bd 20 ad	lda $38ad20,x	                LDA @w DOS_FILE_DESCS,X             ; Check the file descriptor's status
.395a40		89 10		bit #$10	                BIT #FD_STAT_ALLOC                  ; Is the file descriptor allocated?
.395a42		f0 14		beq $395a58	                BEQ found                           ; No: flag and return the found descriptor
.395a44						next_fd
.395a44		c2 20		rep #$20	                REP #$20        ; set A long
.395a46		8a		txa		                TXA                                 ; Yes: Move to the next file descriptor
.395a47		18		clc		                CLC
.395a48		69 20 00	adc #$0020	                ADC #SIZE(FILEDESC)
.395a4b		aa		tax		                TAX
.395a4c		e0 00 01	cpx #$0100	                CPX #SIZE(FILEDESC) * DOS_FD_MAX    ; Are we out of file descriptors?
.395a4f		90 ea		bcc $395a3b	                BLT chk_fd                          ; No: check this new file descriptor
.395a51		e2 20		sep #$20	                SEP #$20        ; set A short
.395a53		a9 16		lda #$16	                LDA #DOS_ERR_NOFD                   ; Yes: Return failure (no file descriptors available)
.395a55		82 22 ff	brl $39597a	                BRL IF_FAILURE
.395a58		09 10		ora #$10	found           ORA #FD_STAT_ALLOC                  ; No: Set the ALLOC bit
.395a5a		9d 20 ad	sta $38ad20,x	                STA @w DOS_FILE_DESCS,X             ; And store it in the file descriptor's status
.395a5d		c2 20		rep #$20	                REP #$20        ; set A long
.395a5f		8a		txa		                TXA
.395a60		18		clc		                CLC
.395a61		69 20 ad	adc #$ad20	                ADC #<>DOS_FILE_DESCS
.395a64		85 20		sta $0340	                STA @b DOS_FD_PTR
.395a66		a9 38 00	lda #$0038	                LDA #`DOS_FILE_DESCS
.395a69		69 00 00	adc #$0000	                ADC #0
.395a6c		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395a6e		82 14 ff	brl $395985	                BRL IF_SUCCESS                      ; Return this file descriptor
.395a71						IF_FREEFD
.395a71		da		phx		                PHX
.395a72		5a		phy		                PHY
.395a73		0b		phd		                PHD
.395a74		8b		phb		                PHB
.395a75		08		php		                PHP
.395a76		48		pha		                PHA             ; begin setdbr macro
.395a77		08		php		                PHP
.395a78		e2 20		sep #$20	                SEP #$20        ; set A short
.395a7a		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
.395a7c		48		pha		                PHA
.395a7d		ab		plb		                PLB
.395a7e		28		plp		                PLP
.395a7f		68		pla		                PLA             ; end setdbr macro
.395a80		48		pha		                PHA             ; begin setdp macro
.395a81		08		php		                PHP
.395a82		c2 20		rep #$20	                REP #$20        ; set A long
.395a84		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395a87		5b		tcd		                TCD
.395a88		28		plp		                PLP
.395a89		68		pla		                PLA             ; end setdp macro
.395a8a		e2 20		sep #$20	                SEP #$20        ; set A short
.395a8c		c2 10		rep #$10	                REP #$10        ; set X long
.395a8e		a9 00		lda #$00	                LDA #0
.395a90		87 20		sta [$0340]	                STA [DOS_FD_PTR]
.395a92		82 f0 fe	brl $395985	                BRL IF_SUCCESS
.395a95						DOS_SRC2DST
.395a95		da		phx		                PHX
.395a96		5a		phy		                PHY
.395a97		0b		phd		                PHD
.395a98		8b		phb		                PHB
.395a99		08		php		                PHP
.395a9a		48		pha		                PHA             ; begin setdp macro
.395a9b		08		php		                PHP
.395a9c		c2 20		rep #$20	                REP #$20        ; set A long
.395a9e		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395aa1		5b		tcd		                TCD
.395aa2		28		plp		                PLP
.395aa3		68		pla		                PLA             ; end setdp macro
.395aa4		c2 30		rep #$30	                REP #$30        ; set A&X long
.395aa6		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER
.395aa9		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
.395aab		aa		tax		                TAX                                     ; X := source buffer address
.395aac		b7 34		lda [$0354],y	                LDA [DOS_DST_PTR],Y
.395aae		a8		tay		                TAY                                     ; Y := destination buffer address
.395aaf		a9 00 02	lda #$0200	                LDA #DOS_SECTOR_SIZE                    ; A := the size of the buffers
.395ab2		54 38 38	mvn $38,$38	                MVN #`DOS_FILE_BUFFS,#`DOS_FILE_BUFFS   ; Copy the sector data
.395ab5		28		plp		                PLP
.395ab6		ab		plb		                PLB
.395ab7		2b		pld		                PLD
.395ab8		7a		ply		                PLY
.395ab9		fa		plx		                PLX
.395aba		6b		rtl		                RTL
.395abb						IF_COPY
.395abb		da		phx		                PHX
.395abc		5a		phy		                PHY
.395abd		0b		phd		                PHD
.395abe		8b		phb		                PHB
.395abf		08		php		                PHP
.395ac0		48		pha		                PHA             ; begin setdbr macro
.395ac1		08		php		                PHP
.395ac2		e2 20		sep #$20	                SEP #$20        ; set A short
.395ac4		a9 00		lda #$00	                LDA #0
.395ac6		48		pha		                PHA
.395ac7		ab		plb		                PLB
.395ac8		28		plp		                PLP
.395ac9		68		pla		                PLA             ; end setdbr macro
.395aca		48		pha		                PHA             ; begin setdp macro
.395acb		08		php		                PHP
.395acc		c2 20		rep #$20	                REP #$20        ; set A long
.395ace		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395ad1		5b		tcd		                TCD
.395ad2		28		plp		                PLP
.395ad3		68		pla		                PLA             ; end setdp macro
.395ad4		22 1d 5a 39	jsl $395a1d	                JSL IF_ALLOCFD                  ; Allocate an FD for the source
.395ad8		b0 03		bcs $395add	                BCS set_src_path
.395ada		82 a1 fe	brl $39597e	                BRL IF_PASSFAILURE              ; If failed: pass the failure up the chain
.395add						set_src_path
.395add		c2 30		rep #$30	                REP #$30        ; set A&X long
.395adf		a0 02 00	ldy #$0002	                LDY #FILEDESC.PATH              ; Set the source path
.395ae2		a5 44		lda $0364	                LDA @b DOS_STR1_PTR
.395ae4		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395ae6		c8		iny		                INY
.395ae7		c8		iny		                INY
.395ae8		a5 46		lda $0366	                LDA @b DOS_STR1_PTR+2
.395aea		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
.395aec						alloc_dest
.395aec		c2 30		rep #$30	                REP #$30        ; set A&X long
.395aee		a5 20		lda $0340	                LDA @b DOS_FD_PTR               ; set DOS_SRC_PTR to the file descriptor pointer
.395af0		85 30		sta $0350	                STA @b DOS_SRC_PTR
.395af2		a5 22		lda $0342	                LDA @b DOS_FD_PTR+2
.395af4		85 32		sta $0352	                STA @b DOS_SRC_PTR+2
.395af6		22 1d 5a 39	jsl $395a1d	                JSL IF_ALLOCFD                  ; Allocate an FD for the destination
.395afa		b0 0f		bcs $395b0b	                BCS set_paths                   ; If everything is ok... start setting the paths
.395afc		a5 30		lda $0350	err_free_src_fd LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
.395afe		85 20		sta $0340	                STA @b DOS_FD_PTR
.395b00		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
.395b02		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395b04		22 71 5a 39	jsl $395a71	                JSL IF_FREEFD                   ; And free it
.395b08		82 73 fe	brl $39597e	                BRL IF_PASSFAILURE              ; Pass the failure up the chain
.395b0b						set_paths
.395b0b		c2 30		rep #$30	                REP #$30        ; set A&X long
.395b0d		a5 20		lda $0340	                LDA @b DOS_FD_PTR               ; Set DOS_DST_PTR to the file descriptor pointer for the destination
.395b0f		85 34		sta $0354	                STA @b DOS_DST_PTR
.395b11		a5 22		lda $0342	                LDA @b DOS_FD_PTR+2
.395b13		85 36		sta $0356	                STA @b DOS_DST_PTR+2
.395b15		a0 02 00	ldy #$0002	                LDY #FILEDESC.PATH              ; Set the destination path
.395b18		a5 48		lda $0368	                LDA @b DOS_STR2_PTR
.395b1a		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
.395b1c		c8		iny		                INY
.395b1d		c8		iny		                INY
.395b1e		a5 4a		lda $036a	                LDA @b DOS_STR2_PTR+2
.395b20		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
.395b22		a5 30		lda $0350	                LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
.395b24		85 20		sta $0340	                STA @b DOS_FD_PTR
.395b26		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
.395b28		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395b2a		22 f0 10 00	jsl $0010f0	                JSL F_OPEN                      ; Try to open the file
.395b2e		b0 0f		bcs $395b3f	                BCS src_open                    ; If success, work with the openned file
.395b30		a5 34		lda $0354	err_free_dst_fd LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
.395b32		85 20		sta $0340	                STA @b DOS_FD_PTR
.395b34		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
.395b36		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395b38		22 71 5a 39	jsl $395a71	                JSL IF_FREEFD                   ; And free it
.395b3c		82 bd ff	brl $395afc	                BRL err_free_src_fd             ; Free the source file descriptor
.395b3f		a0 12 00	ldy #$0012	src_open        LDY #FILEDESC.SIZE              ; destination file size := source file size
.395b42		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
.395b44		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
.395b46		c8		iny		                INY
.395b47		c8		iny		                INY
.395b48		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
.395b4a		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
.395b4c		22 95 5a 39	jsl $395a95	                JSL DOS_SRC2DST                 ; Copy the first sector's worth of data
.395b50		a5 34		lda $0354	                LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
.395b52		85 20		sta $0340	                STA @b DOS_FD_PTR
.395b54		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
.395b56		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395b58		22 f4 10 00	jsl $0010f4	                JSL F_CREATE                    ; Attempt to create the file
.395b5c		b0 0f		bcs $395b6d	                BCS read_next                   ; If sucessful, try to get the next cluster
.395b5e		a5 30		lda $0350	err_src_close   LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
.395b60		85 20		sta $0340	                STA @b DOS_FD_PTR
.395b62		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
.395b64		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395b66		22 f8 10 00	jsl $0010f8	                JSL F_CLOSE                     ; Close the source file (maybe not really necessary)
.395b6a		82 c3 ff	brl $395b30	                BRL err_free_dst_fd             ; Free the file descriptors and return an error
.395b6d						read_next
.395b6d		a5 30		lda $0350	                LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
.395b6f		85 20		sta $0340	                STA @b DOS_FD_PTR
.395b71		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
.395b73		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395b75		22 00 11 00	jsl $001100	                JSL F_READ                      ; Attempt to read the next sector of the source
.395b79		b0 19		bcs $395b94	                BCS copy2dest                   ; If successful, copy the sector
.395b7b		e2 20		sep #$20	                SEP #$20        ; set A short
.395b7d		a5 0e		lda $032e	                LDA @b DOS_STATUS
.395b7f		c9 0a		cmp #$0a	                CMP #DOS_ERR_NOCLUSTER          ; Are there no more clusters in the source file?
.395b81		f0 32		beq $395bb5	                BEQ file_copied                 ; Yes: we're done copying
.395b83						err_dest_close
.395b83		c2 20		rep #$20	                REP #$20        ; set A long
.395b85		a5 34		lda $0354	                LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
.395b87		85 20		sta $0340	                STA @b DOS_FD_PTR
.395b89		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
.395b8b		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395b8d		22 f8 10 00	jsl $0010f8	                JSL F_CLOSE                     ; Attempt to close the destination
.395b91		82 ca ff	brl $395b5e	                BRL err_src_close               ; Close the source and throw an error
.395b94						copy2dest
.395b94		22 95 5a 39	jsl $395a95	                JSL DOS_SRC2DST                 ; Copy the source sector to the destination sector
.395b98		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; destination sector cluster ID := 0 to append
.395b9b		a9 00 00	lda #$0000	                LDA #0
.395b9e		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
.395ba0		c8		iny		                INY
.395ba1		c8		iny		                INY
.395ba2		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
.395ba4		a5 34		lda $0354	                LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
.395ba6		85 20		sta $0340	                STA @b DOS_FD_PTR
.395ba8		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
.395baa		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395bac		22 fc 10 00	jsl $0010fc	                JSL F_WRITE                     ; Attempt to write the destionation sector to the disk
.395bb0		90 d1		bcc $395b83	                BCC err_dest_close              ; If error: close all files and throw the error
.395bb2		82 b8 ff	brl $395b6d	                BRL read_next                   ; Otherwise: repeat the loop
.395bb5						file_copied
.395bb5		c2 20		rep #$20	                REP #$20        ; set A long
.395bb7		a5 34		lda $0354	                LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
.395bb9		85 20		sta $0340	                STA @b DOS_FD_PTR
.395bbb		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
.395bbd		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395bbf		22 f8 10 00	jsl $0010f8	                JSL F_CLOSE                     ; Close the destination
.395bc3		a5 30		lda $0350	                LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
.395bc5		85 20		sta $0340	                STA @b DOS_FD_PTR
.395bc7		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
.395bc9		85 22		sta $0342	                STA @b DOS_FD_PTR+2
.395bcb		22 f8 10 00	jsl $0010f8	                JSL F_CLOSE                     ; Close the source
.395bcf		82 b3 fd	brl $395985	                BRL IF_SUCCESS

;******  Return to file: src\kernel.asm


;******  Processing file: src\uart.asm

=$af13f8					UART1_BASE = $AF13F8        ; Base address for UART 1 (COM1)
=$af12f8					UART2_BASE = $AF12F8        ; Base address for UART 2 (COM2)
=$00						UART_TRHB = $00             ; Transmit/Receive Hold Buffer
=$00						UART_DLL = UART_TRHB        ; Divisor Latch Low Byte
=$01						UART_DLH = $01              ; Divisor Latch High Byte
=$01						UART_IER = UART_DLH         ; Interupt Enable Register
=$02						UART_FCR = $02              ; FIFO Control Register
=$02						UART_IIR = UART_FCR         ; Interupt Indentification Register
=$03						UART_LCR = $03              ; Line Control Register
=$04						UART_MCR = $04              ; Modem Control REgister
=$05						UART_LSR = $05              ; Line Status Register
=$06						UART_MSR = $06              ; Modem Status Register
=$07						UART_SR = $07               ; Scratch Register
=$20						UINT_LOW_POWER = $20        ; Enable Low Power Mode (16750)
=$10						UINT_SLEEP_MODE = $10       ; Enable Sleep Mode (16750)
=$08						UINT_MODEM_STATUS = $08     ; Enable Modem Status Interrupt
=$04						UINT_LINE_STATUS = $04      ; Enable Receiver Line Status Interupt
=$02						UINT_THR_EMPTY = $02        ; Enable Transmit Holding Register Empty interrupt
=$01						UINT_DATA_AVAIL = $01       ; Enable Recieve Data Available interupt
=$80						IIR_FIFO_ENABLED = $80      ; FIFO is enabled
=$40						IIR_FIFO_NONFUNC = $40      ; FIFO is not functioning
=$20						IIR_FIFO_64BYTE = $20       ; 64 byte FIFO enabled (16750)
=$00						IIR_MODEM_STATUS = $00      ; Modem Status Interrupt
=$02						IIR_THR_EMPTY = $02         ; Transmit Holding Register Empty Interrupt
=$04						IIR_DATA_AVAIL = $04        ; Data Available Interrupt
=$06						IIR_LINE_STATUS = $06       ; Line Status Interrupt
=$0c						IIR_TIMEOUT = $0C           ; Time-out Interrupt (16550 and later)
=$01						IIR_INTERRUPT_PENDING = $01 ; Interrupt Pending Flag
=$80						LCR_DLB = $80               ; Divisor Latch Access Bit
=$60						LCR_SBE = $60               ; Set Break Enable
=$00						LCR_PARITY_NONE = $00       ; Parity: None
=$08						LCR_PARITY_ODD = $08        ; Parity: Odd
=$18						LCR_PARITY_EVEN = $18       ; Parity: Even
=$28						LCR_PARITY_MARK = $28       ; Parity: Mark
=$38						LCR_PARITY_SPACE = $38      ; Parity: Space
=$00						LCR_STOPBIT_1 = $00         ; One Stop Bit
=$04						LCR_STOPBIT_2 = $04         ; 1.5 or 2 Stop Bits
=$00						LCR_DATABITS_5 = $00        ; Data Bits: 5
=$01						LCR_DATABITS_6 = $01        ; Data Bits: 6
=$02						LCR_DATABITS_7 = $02        ; Data Bits: 7
=$03						LCR_DATABITS_8 = $03        ; Data Bits: 8
=$80						LSR_ERR_RECIEVE = $80       ; Error in Received FIFO
=$40						LSR_XMIT_DONE = $40         ; All data has been transmitted
=$20						LSR_XMIT_EMPTY = $20        ; Empty transmit holding register
=$10						LSR_BREAK_INT = $10         ; Break interrupt
=$08						LSR_ERR_FRAME = $08         ; Framing error
=$04						LSR_ERR_PARITY = $04        ; Parity error
=$02						LSR_ERR_OVERRUN = $02       ; Overrun error
=$01						LSR_DATA_AVAIL = $01        ; Data is ready in the receive buffer
=384						UART_300 = 384              ; Code for 300 bps
=96						UART_1200 = 96              ; Code for 1200 bps
=48						UART_2400 = 48              ; Code for 2400 bps
=24						UART_4800 = 24              ; Code for 4800 bps
=12						UART_9600 = 12              ; Code for 9600 bps
=6						UART_19200 = 6              ; Code for 19200 bps
=3						UART_38400 = 3              ; Code for 28400 bps
=2						UART_57600 = 2              ; Code for 57600 bps
=1						UART_115200 = 1             ; Code for 115200 bps
.395bd2						UART_SELECT
.395bd2		08		php		            PHP
.395bd3		c2 20		rep #$20	                REP #$20        ; set A long
.395bd5		c9 02 00	cmp #$0002	            CMP #2
.395bd8		f0 07		beq $395be1	            BEQ is_COM2
.395bda		c2 20		rep #$20	                REP #$20        ; set A long
.395bdc		a9 f8 13	lda #$13f8	            LDA #<>UART1_BASE
.395bdf		80 05		bra $395be6	            BRA setaddr
.395be1						is_COM2
.395be1		c2 20		rep #$20	                REP #$20        ; set A long
.395be3		a9 f8 12	lda #$12f8	            LDA #<>UART2_BASE
.395be6		8f 00 07 00	sta $000700	setaddr     STA @lCURRUART
.395bea		e2 20		sep #$20	                SEP #$20        ; set A short
.395bec		a9 af		lda #$af	            LDA #`UART1_BASE
.395bee		8f 02 07 00	sta $000702	            STA @lCURRUART+2
.395bf2		28		plp		            PLP
.395bf3		6b		rtl		            RTL
.395bf4						UART_SETBPS
.395bf4		08		php		            PHP
.395bf5		0b		phd		            PHD
.395bf6		48		pha		                PHA             ; begin setdp macro
.395bf7		08		php		                PHP
.395bf8		c2 20		rep #$20	                REP #$20        ; set A long
.395bfa		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
.395bfd		5b		tcd		                TCD
.395bfe		28		plp		                PLP
.395bff		68		pla		                PLA             ; end setdp macro
.395c00		c2 30		rep #$30	                REP #$30        ; set A&X long
.395c02		48		pha		            PHA
.395c03		e2 20		sep #$20	                SEP #$20        ; set A short
.395c05		a0 03 00	ldy #$0003	            LDY #UART_LCR       ; Enable divisor latch
.395c08		b7 00		lda [$0700],y	            LDA [CURRUART],Y
.395c0a		09 80		ora #$80	            ORA #LCR_DLB
.395c0c		97 00		sta [$0700],y	            STA [CURRUART],Y
.395c0e		c2 20		rep #$20	                REP #$20        ; set A long
.395c10		68		pla		            PLA
.395c11		a0 00 00	ldy #$0000	            LDY #UART_DLL
.395c14		97 00		sta [$0700],y	            STA [CURRUART],Y    ; Save the divisor to the UART
.395c16		e2 20		sep #$20	                SEP #$20        ; set A short
.395c18		a0 03 00	ldy #$0003	            LDY #UART_LCR       ; Disable divisor latch
.395c1b		b7 00		lda [$0700],y	            LDA [CURRUART],Y
.395c1d		49 80		eor #$80	            EOR #LCR_DLB
.395c1f		97 00		sta [$0700],y	            STA [CURRUART],Y
.395c21		2b		pld		            PLD
.395c22		28		plp		            PLP
.395c23		6b		rtl		            RTL
.395c24						UART_SETLCR
.395c24		08		php		            PHP
.395c25		0b		phd		            PHD
.395c26		48		pha		                PHA             ; begin setdp macro
.395c27		08		php		                PHP
.395c28		c2 20		rep #$20	                REP #$20        ; set A long
.395c2a		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
.395c2d		5b		tcd		                TCD
.395c2e		28		plp		                PLP
.395c2f		68		pla		                PLA             ; end setdp macro
.395c30		e2 20		sep #$20	                SEP #$20        ; set A short
.395c32		c2 10		rep #$10	                REP #$10        ; set X long
.395c34		29 7f		and #$7f	            AND #$7F            ; We don't want to alter divisor latch
.395c36		a0 03 00	ldy #$0003	            LDY #UART_LCR
.395c39		97 00		sta [$0700],y	            STA [CURRUART],Y
.395c3b		2b		pld		            PLD
.395c3c		28		plp		            PLP
.395c3d		6b		rtl		            RTL
.395c3e						UART_INIT
.395c3e		08		php		            PHP
.395c3f		0b		phd		            PHD
.395c40		c2 30		rep #$30	                REP #$30        ; set A&X long
.395c42		48		pha		                PHA             ; begin setdp macro
.395c43		08		php		                PHP
.395c44		c2 20		rep #$20	                REP #$20        ; set A long
.395c46		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
.395c49		5b		tcd		                TCD
.395c4a		28		plp		                PLP
.395c4b		68		pla		                PLA             ; end setdp macro
.395c4c		a9 01 00	lda #$0001	            LDA #UART_115200
.395c4f		22 f4 5b 39	jsl $395bf4	            JSL UART_SETBPS
.395c53		e2 20		sep #$20	                SEP #$20        ; set A short
.395c55		a9 03		lda #$03	            LDA #LCR_PARITY_NONE | LCR_STOPBIT_1 | LCR_DATABITS_8
.395c57		22 24 5c 39	jsl $395c24	            JSL UART_SETLCR
.395c5b		a9 e1		lda #$e1	            LDA #%11100001
.395c5d		a0 02 00	ldy #$0002	            LDY #UART_FCR
.395c60		97 00		sta [$0700],y	            STA [CURRUART],Y
.395c62		2b		pld		            PLD
.395c63		28		plp		            PLP
.395c64		6b		rtl		            RTL
.395c65						UART_HASBYT
.395c65		08		php		            PHP
.395c66		0b		phd		            PHD
.395c67		c2 30		rep #$30	                REP #$30        ; set A&X long
.395c69		48		pha		                PHA             ; begin setdp macro
.395c6a		08		php		                PHP
.395c6b		c2 20		rep #$20	                REP #$20        ; set A long
.395c6d		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
.395c70		5b		tcd		                TCD
.395c71		28		plp		                PLP
.395c72		68		pla		                PLA             ; end setdp macro
.395c73		e2 20		sep #$20	                SEP #$20        ; set A short
.395c75		a0 05 00	ldy #$0005	            LDY #UART_LSR           ; Check the receive FIFO
.395c78		b7 00		lda [$0700],y	wait_putc   LDA [CURRUART],Y
.395c7a		29 01		and #$01	            AND #LSR_DATA_AVAIL
.395c7c		d0 04		bne $395c82	            BNE ret_true            ; If flag is set, return true
.395c7e		2b		pld		ret_false   PLD                     ; Return false
.395c7f		28		plp		            PLP
.395c80		18		clc		            CLC
.395c81		6b		rtl		            RTL
.395c82		2b		pld		ret_true    PLD                     ; Return true
.395c83		28		plp		            PLP
.395c84		38		sec		            SEC
.395c85		6b		rtl		            RTL
.395c86						UART_GETC
.395c86		08		php		            PHP
.395c87		0b		phd		            PHD
.395c88		c2 30		rep #$30	                REP #$30        ; set A&X long
.395c8a		48		pha		                PHA             ; begin setdp macro
.395c8b		08		php		                PHP
.395c8c		c2 20		rep #$20	                REP #$20        ; set A long
.395c8e		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
.395c91		5b		tcd		                TCD
.395c92		28		plp		                PLP
.395c93		68		pla		                PLA             ; end setdp macro
.395c94		e2 20		sep #$20	                SEP #$20        ; set A short
.395c96		a0 05 00	ldy #$0005	            LDY #UART_LSR           ; Check the receive FIFO
.395c99		b7 00		lda [$0700],y	wait_getc   LDA [CURRUART],Y
.395c9b		29 01		and #$01	            AND #LSR_DATA_AVAIL
.395c9d		f0 fa		beq $395c99	            BEQ wait_getc           ; If the flag is clear, wait
.395c9f		a0 00 00	ldy #$0000	            LDY #UART_TRHB          ; Get the byte from the receive FIFO
.395ca2		b7 00		lda [$0700],y	            LDA [CURRUART],Y
.395ca4		2b		pld		            PLD
.395ca5		28		plp		            PLP
.395ca6		6b		rtl		            RTL
.395ca7						UART_PUTC
.395ca7		08		php		            PHP
.395ca8		0b		phd		            PHD
.395ca9		c2 30		rep #$30	                REP #$30        ; set A&X long
.395cab		48		pha		                PHA             ; begin setdp macro
.395cac		08		php		                PHP
.395cad		c2 20		rep #$20	                REP #$20        ; set A long
.395caf		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
.395cb2		5b		tcd		                TCD
.395cb3		28		plp		                PLP
.395cb4		68		pla		                PLA             ; end setdp macro
.395cb5		e2 20		sep #$20	                SEP #$20        ; set A short
.395cb7		48		pha		            PHA                     ; Wait for the transmit FIFO to free up
.395cb8		a0 05 00	ldy #$0005	            LDY #UART_LSR
.395cbb		b7 00		lda [$0700],y	wait_putc   LDA [CURRUART],Y
.395cbd		29 20		and #$20	            AND #LSR_XMIT_EMPTY
.395cbf		f0 fa		beq $395cbb	            BEQ wait_putc
.395cc1		68		pla		            PLA
.395cc2		a0 00 00	ldy #$0000	            LDY #UART_TRHB
.395cc5		97 00		sta [$0700],y	            STA [CURRUART],Y
.395cc7		2b		pld		            PLD
.395cc8		28		plp		            PLP
.395cc9		6b		rtl		            RTL
.395cca						UART_PUTS
.395cca		08		php		            PHP
.395ccb		e2 20		sep #$20	                SEP #$20        ; set A short
.395ccd		bd 00 00	lda $0000,x	put_loop    LDA #0,B,X
.395cd0		f0 07		beq $395cd9	            BEQ done
.395cd2		22 a7 5c 39	jsl $395ca7	            JSL UART_PUTC
.395cd6		e8		inx		            INX
.395cd7		80 f4		bra $395ccd	            BRA put_loop
.395cd9		28		plp		done        PLP
.395cda		6b		rtl		            RTL

;******  Return to file: src\kernel.asm


;******  Processing file: src\joystick.asm

.395cdb						JOYSTICK_SET_NES_MODE
.395cdb		e2 20		sep #$20	                SEP #$20        ; set A short
.395cdd		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
.395ce1		29 fb		and #$fb	          AND #~NES_SNES_JOY  ; 0 = NES (8 bit shift)
.395ce3		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
.395ce7		6b		rtl		          RTL
.395ce8						JOYSTICK_SET_SNES_MODE
.395ce8		e2 20		sep #$20	                SEP #$20        ; set A short
.395cea		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
.395cee		29 fb		and #$fb	          AND #~NES_SNES_JOY
.395cf0		09 04		ora #$04	          ORA #NES_SNES_JOY   ; 1 = SNES (12 Bit Shift)
.395cf2		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
.395cf6		6b		rtl		          RTL
.395cf7						JOYSTICK_ENABLE_NES_SNES_PORT0
.395cf7		e2 20		sep #$20	                SEP #$20        ; set A short
.395cf9		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
.395cfd		29 fe		and #$fe	          AND #~NES_SNES_EN0
.395cff		09 01		ora #$01	          ORA #NES_SNES_EN0
.395d01		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
.395d05		6b		rtl		          RTL
.395d06						JOYSTICK_ENABLE_NES_SNES_PORT1
.395d06		e2 20		sep #$20	                SEP #$20        ; set A short
.395d08		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
.395d0c		29 fd		and #$fd	          AND #~NES_SNES_EN1
.395d0e		09 02		ora #$02	          ORA #NES_SNES_EN1
.395d10		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
.395d14		6b		rtl		          RTL
.395d15						JOYSTICK_DISABLE_NES_SNES_PORT0
.395d15		e2 20		sep #$20	                SEP #$20        ; set A short
.395d17		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
.395d1b		29 fe		and #$fe	          AND #~NES_SNES_EN0
.395d1d		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
.395d21		6b		rtl		          RTL
.395d22						JOYSTICK_DISABLE_NES_SNES_PORT1
.395d22		e2 20		sep #$20	                SEP #$20        ; set A short
.395d24		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
.395d28		29 fd		and #$fd	          AND #~NES_SNES_EN1
.395d2a		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
.395d2e		6b		rtl		          RTL
.395d2f						JOYSTICK_NES_SNES_TRIG_WITH_POLL
.395d2f		e2 20		sep #$20	                SEP #$20        ; set A short
.395d31		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
.395d35		29 03		and #$03	          AND #(NES_SNES_EN0 | NES_SNES_EN1)
.395d37		c9 00		cmp #$00	          CMP #$00
.395d39		f0 14		beq $395d4f	          BEQ END_OF_JOYSTICK_POLL
.395d3b		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
.395d3f		09 80		ora #$80	          ORA #NES_SNES_TRIG   ; Set to 1 (Will auto Clear)
.395d41		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
.395d45						JOYSTICK_POLLING_ISNOTOVER
.395d45		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE ;
.395d49		29 40		and #$40	          AND #NES_SNES_DONE
.395d4b		c9 40		cmp #$40	          CMP #NES_SNES_DONE
.395d4d		d0 f6		bne $395d45	          BNE JOYSTICK_POLLING_ISNOTOVER
.395d4f						END_OF_JOYSTICK_POLL
.395d4f		6b		rtl		          RTL

;******  Return to file: src\kernel.asm


;******  Processing file: src\sdc_library.asm

.395d50						SDC_TEST
.395d50		8b		phb		                PHB
.395d51		0b		phd		                PHD
.395d52		08		php		                PHP
.395d53		48		pha		                PHA             ; begin setdbr macro
.395d54		08		php		                PHP
.395d55		e2 20		sep #$20	                SEP #$20        ; set A short
.395d57		a9 00		lda #$00	                LDA #0
.395d59		48		pha		                PHA
.395d5a		ab		plb		                PLB
.395d5b		28		plp		                PLP
.395d5c		68		pla		                PLA             ; end setdbr macro
.395d5d		48		pha		                PHA             ; begin setdp macro
.395d5e		08		php		                PHP
.395d5f		c2 20		rep #$20	                REP #$20        ; set A long
.395d61		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395d64		5b		tcd		                TCD
.395d65		28		plp		                PLP
.395d66		68		pla		                PLA             ; end setdp macro
.395d67		e2 20		sep #$20	                SEP #$20        ; set A short
.395d69		a9 f0		lda #$f0	                LDA #$F0                            ; Set white on black background
.395d6b		8d 1e 00	sta $001e	                STA @w CURCOLOR
.395d6e		22 a8 10 00	jsl $0010a8	                JSL CLRSCREEN
.395d72		22 a0 10 00	jsl $0010a0	                JSL CSRHOME
.395d76		22 b6 5d 39	jsl $395db6	                JSL SDC_INIT                        ; Attempt to initilize the SDC interface
.395d7a		b0 03		bcs $395d7f	                BCS init_ok
.395d7c		82 15 00	brl $395d94	                BRL done
.395d7f		a9 02		lda #$02	init_ok         LDA #BIOS_DEV_SD
.395d81		85 01		sta $0321	                STA BIOS_DEV
.395d83		22 54 45 39	jsl $394554	                JSL DOS_MOUNT                       ; Attempt to mount the SDC
.395d87		b0 03		bcs $395d8c	                BCS mount_ok
.395d89		82 08 00	brl $395d94	                BRL done
.395d8c		22 07 56 39	jsl $395607	mount_ok        JSL IF_DIROPEN
.395d90		b0 02		bcs $395d94	                BCS all_ok
.395d92		80 00		bra $395d94	                BRA done
.395d94						all_ok
.395d94		22 6c 10 00	jsl $00106c	done            JSL PRINTCR
.395d98		28		plp		                PLP
.395d99		2b		pld		                PLD
.395d9a		ab		plb		                PLB
.395d9b		6b		rtl		                RTL
.395d9c						SDC_WAITBUSY
.395d9c		08		php		                PHP
.395d9d		e2 20		sep #$20	                SEP #$20        ; set A short
.395d9f		af 04 ea af	lda $afea04	wait_xact       LDA @l SDC_TRANS_STATUS_REG         ; Wait for the transaction to complete
.395da3		29 01		and #$01	                AND #SDC_TRANS_BUSY
.395da5		c9 01		cmp #$01	                CMP #SDC_TRANS_BUSY
.395da7		f0 f6		beq $395d9f	                BEQ wait_xact
.395da9		28		plp		                PLP
.395daa		6b		rtl		                RTL
.395dab						SDC_RESET
.395dab		08		php		                PHP
.395dac		e2 20		sep #$20	                SEP #$20        ; set A short
.395dae		a9 01		lda #$01	                LDA #1
.395db0		8f 01 ea af	sta $afea01	                STA @l SDC_CONTROL_REG
.395db4		28		plp		                PLP
.395db5		6b		rtl		                RTL
.395db6						SDC_INIT
.395db6		0b		phd		                PHD
.395db7		8b		phb		                PHB
.395db8		08		php		                PHP
.395db9		48		pha		                PHA             ; begin setdbr macro
.395dba		08		php		                PHP
.395dbb		e2 20		sep #$20	                SEP #$20        ; set A short
.395dbd		a9 00		lda #$00	                LDA #0
.395dbf		48		pha		                PHA
.395dc0		ab		plb		                PLB
.395dc1		28		plp		                PLP
.395dc2		68		pla		                PLA             ; end setdbr macro
.395dc3		48		pha		                PHA             ; begin setdp macro
.395dc4		08		php		                PHP
.395dc5		c2 20		rep #$20	                REP #$20        ; set A long
.395dc7		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395dca		5b		tcd		                TCD
.395dcb		28		plp		                PLP
.395dcc		68		pla		                PLA             ; end setdp macro
.395dcd		e2 20		sep #$20	                SEP #$20        ; set A short
.395dcf		a9 01		lda #$01	start_trans     LDA #SDC_TRANS_INIT_SD
.395dd1		8f 02 ea af	sta $afea02	                STA @l SDC_TRANS_TYPE_REG           ; Set Init SD
.395dd5		a9 01		lda #$01	                LDA #SDC_TRANS_START                ; Set the transaction to start
.395dd7		8f 03 ea af	sta $afea03	                STA @l SDC_TRANS_CONTROL_REG
.395ddb		22 9c 5d 39	jsl $395d9c	                JSL SDC_WAITBUSY                    ; Wait for initialization to complete
.395ddf		af 05 ea af	lda $afea05	                LDA @l SDC_TRANS_ERROR_REG          ; Check for errors
.395de3		d0 07		bne $395dec	                BNE ret_error                       ; Is there one? Process the error
.395de5		64 00		stz $0320	ret_success     STZ BIOS_STATUS
.395de7		28		plp		                PLP
.395de8		ab		plb		                PLB
.395de9		2b		pld		                PLD
.395dea		38		sec		                SEC
.395deb		6b		rtl		                RTL
.395dec		8d 06 03	sta $0306	ret_error       STA @w FDC_ST0
.395def		a9 8b		lda #$8b	                LDA #BIOS_ERR_NOTINIT
.395df1		85 00		sta $0320	set_error       STA BIOS_STATUS
.395df3		28		plp		                PLP
.395df4		ab		plb		                PLB
.395df5		2b		pld		                PLD
.395df6		18		clc		                CLC
.395df7		6b		rtl		                RTL
.395df8						SDC_GETBLOCK
.395df8		0b		phd		                PHD
.395df9		8b		phb		                PHB
.395dfa		08		php		                PHP
.395dfb		48		pha		                PHA             ; begin setdbr macro
.395dfc		08		php		                PHP
.395dfd		e2 20		sep #$20	                SEP #$20        ; set A short
.395dff		a9 00		lda #$00	                LDA #0
.395e01		48		pha		                PHA
.395e02		ab		plb		                PLB
.395e03		28		plp		                PLP
.395e04		68		pla		                PLA             ; end setdbr macro
.395e05		48		pha		                PHA             ; begin setdp macro
.395e06		08		php		                PHP
.395e07		c2 20		rep #$20	                REP #$20        ; set A long
.395e09		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395e0c		5b		tcd		                TCD
.395e0d		28		plp		                PLP
.395e0e		68		pla		                PLA             ; end setdp macro
.395e0f		e2 20		sep #$20	                SEP #$20        ; set A short
.395e11		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn on the SDC activity light
.395e15		09 02		ora #$02	                ORA #GABE_CTRL_SDC_LED
.395e17		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
.395e1b		a9 00		lda #$00	                LDA #0
.395e1d		8f 07 ea af	sta $afea07	                STA @l SDC_SD_ADDR_7_0_REG
.395e21		a5 02		lda $0322	                LDA BIOS_LBA                        ; Set the LBA to read
.395e23		0a		asl a		                ASL A
.395e24		8f 08 ea af	sta $afea08	                STA @l SDC_SD_ADDR_15_8_REG
.395e28		a5 03		lda $0323	                LDA BIOS_LBA+1
.395e2a		2a		rol a		                ROL A
.395e2b		8f 09 ea af	sta $afea09	                STA @l SDC_SD_ADDR_23_16_REG
.395e2f		a5 04		lda $0324	                LDA BIOS_LBA+2
.395e31		2a		rol a		                ROL A
.395e32		8f 0a ea af	sta $afea0a	                STA @l SDC_SD_ADDR_31_24_REG
.395e36		a9 02		lda #$02	                LDA #SDC_TRANS_READ_BLK             ; Set the transaction to READ
.395e38		8f 02 ea af	sta $afea02	                STA @l SDC_TRANS_TYPE_REG
.395e3c		a9 01		lda #$01	                LDA #SDC_TRANS_START                ; Set the transaction to start
.395e3e		8f 03 ea af	sta $afea03	                STA @l SDC_TRANS_CONTROL_REG
.395e42		22 9c 5d 39	jsl $395d9c	                JSL SDC_WAITBUSY                    ; Wait for transaction to complete
.395e46		af 05 ea af	lda $afea05	                LDA @l SDC_TRANS_ERROR_REG          ; Check for errors
.395e4a		d0 36		bne $395e82	                BNE ret_error                       ; Is there one? Process the error
.395e4c		e2 20		sep #$20	                SEP #$20        ; set A short
.395e4e		af 13 ea af	lda $afea13	                LDA @l SDC_RX_FIFO_DATA_CNT_LO      ; Record the number of bytes read
.395e52		85 0a		sta $032a	                STA BIOS_FIFO_COUNT
.395e54		af 12 ea af	lda $afea12	                LDA @l SDC_RX_FIFO_DATA_CNT_HI
.395e58		85 0b		sta $032b	                STA BIOS_FIFO_COUNT+1
.395e5a		c2 10		rep #$10	                REP #$10        ; set X long
.395e5c		a0 00 00	ldy #$0000	                LDY #0
.395e5f		af 10 ea af	lda $afea10	loop_rd         LDA @l SDC_RX_FIFO_DATA_REG         ; Get the byte...
.395e63		97 06		sta [$0326],y	                STA [BIOS_BUFF_PTR],Y               ; Save it to the buffer
.395e65		c8		iny		                INY                                 ; Advance to the next byte
.395e66		c0 00 02	cpy #$0200	                CPY #512                            ; Have we read all the bytes?
.395e69		d0 f4		bne $395e5f	                BNE loop_rd                         ; No: keep reading
.395e6b		af 05 ea af	lda $afea05	                LDA @l SDC_TRANS_ERROR_REG          ; Check for errors
.395e6f		d0 11		bne $395e82	                BNE ret_error                       ; Is there one? Process the error
.395e71		64 00		stz $0320	ret_success     STZ BIOS_STATUS                     ; Return success
.395e73		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn off the SDC activity light
.395e77		29 fd		and #$fd	                AND #~GABE_CTRL_SDC_LED
.395e79		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
.395e7d		28		plp		                PLP
.395e7e		ab		plb		                PLB
.395e7f		2b		pld		                PLD
.395e80		38		sec		                SEC
.395e81		6b		rtl		                RTL
.395e82		8d 06 03	sta $0306	ret_error       STA @w FDC_ST0
.395e85		a9 82		lda #$82	                LDA #BIOS_ERR_READ
.395e87		85 00		sta $0320	                STA BIOS_STATUS
.395e89		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn off the SDC activity light
.395e8d		29 fd		and #$fd	                AND #~GABE_CTRL_SDC_LED
.395e8f		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
.395e93		28		plp		                PLP
.395e94		ab		plb		                PLB
.395e95		2b		pld		                PLD
.395e96		18		clc		                CLC
.395e97		6b		rtl		                RTL
.395e98						SDC_PUTBLOCK
.395e98		0b		phd		                PHD
.395e99		8b		phb		                PHB
.395e9a		08		php		                PHP
.395e9b		48		pha		                PHA             ; begin setdbr macro
.395e9c		08		php		                PHP
.395e9d		e2 20		sep #$20	                SEP #$20        ; set A short
.395e9f		a9 00		lda #$00	                LDA #0
.395ea1		48		pha		                PHA
.395ea2		ab		plb		                PLB
.395ea3		28		plp		                PLP
.395ea4		68		pla		                PLA             ; end setdbr macro
.395ea5		48		pha		                PHA             ; begin setdp macro
.395ea6		08		php		                PHP
.395ea7		c2 20		rep #$20	                REP #$20        ; set A long
.395ea9		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.395eac		5b		tcd		                TCD
.395ead		28		plp		                PLP
.395eae		68		pla		                PLA             ; end setdp macro
.395eaf		e2 20		sep #$20	                SEP #$20        ; set A short
.395eb1		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn on the SDC activity light
.395eb5		09 02		ora #$02	                ORA #GABE_CTRL_SDC_LED
.395eb7		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
.395ebb		c2 10		rep #$10	                REP #$10        ; set X long
.395ebd		a0 00 00	ldy #$0000	                LDY #0
.395ec0		b7 06		lda [$0326],y	loop_wr         LDA [BIOS_BUFF_PTR],Y               ; Get the byte...
.395ec2		8f 20 ea af	sta $afea20	                STA @l SDC_TX_FIFO_DATA_REG         ; Save it to the SDC
.395ec6		c8		iny		                INY                                 ; Advance to the next byte
.395ec7		c0 00 02	cpy #$0200	                CPY #512                            ; Have we read all the bytes?
.395eca		d0 f4		bne $395ec0	                BNE loop_wr                         ; No: keep writing
.395ecc		a9 00		lda #$00	                LDA #0
.395ece		8f 07 ea af	sta $afea07	                STA @l SDC_SD_ADDR_7_0_REG
.395ed2		a5 02		lda $0322	                LDA BIOS_LBA                        ; Set the LBA to write
.395ed4		0a		asl a		                ASL A
.395ed5		8f 08 ea af	sta $afea08	                STA @l SDC_SD_ADDR_15_8_REG
.395ed9		a5 03		lda $0323	                LDA BIOS_LBA+1
.395edb		2a		rol a		                ROL A
.395edc		8f 09 ea af	sta $afea09	                STA @l SDC_SD_ADDR_23_16_REG
.395ee0		a5 04		lda $0324	                LDA BIOS_LBA+2
.395ee2		2a		rol a		                ROL A
.395ee3		8f 0a ea af	sta $afea0a	                STA @l SDC_SD_ADDR_31_24_REG
.395ee7		a9 03		lda #$03	                LDA #SDC_TRANS_WRITE_BLK            ; Set the transaction to WRITE
.395ee9		8f 02 ea af	sta $afea02	                STA @l SDC_TRANS_TYPE_REG
.395eed		a9 01		lda #$01	                LDA #SDC_TRANS_START                ; Set the transaction to start
.395eef		8f 03 ea af	sta $afea03	                STA @l SDC_TRANS_CONTROL_REG
.395ef3		22 9c 5d 39	jsl $395d9c	                JSL SDC_WAITBUSY                    ; Wait for transaction to complete
.395ef7		af 05 ea af	lda $afea05	                LDA @l SDC_TRANS_ERROR_REG          ; Check for errors
.395efb		d0 11		bne $395f0e	                BNE ret_error                       ; Is there one? Process the error
.395efd		64 00		stz $0320	ret_success     STZ BIOS_STATUS                     ; Return success
.395eff		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn off the SDC activity light
.395f03		29 fd		and #$fd	                AND #~GABE_CTRL_SDC_LED
.395f05		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
.395f09		28		plp		                PLP
.395f0a		ab		plb		                PLB
.395f0b		2b		pld		                PLD
.395f0c		38		sec		                SEC
.395f0d		6b		rtl		                RTL
.395f0e		8d 06 03	sta $0306	ret_error       STA @w FDC_ST0
.395f11		a9 82		lda #$82	                LDA #BIOS_ERR_READ
.395f13		85 00		sta $0320	                STA BIOS_STATUS
.395f15		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn off the SDC activity light
.395f19		29 fd		and #$fd	                AND #~GABE_CTRL_SDC_LED
.395f1b		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
.395f1f		28		plp		                PLP
.395f20		ab		plb		                PLB
.395f21		2b		pld		                PLD
.395f22		18		clc		                CLC
.395f23		6b		rtl		                RTL

;******  Return to file: src\kernel.asm


;******  Processing file: src\fdc_library.asm

=4295454					FDC_MOTOR_TIME = 4295454        ; Time to wait for the motor to come on: 300ms
=2147727					FDC_SEEK_TIME = 2147727         ; Time to wait for a seek to happen: 150ms
=900						FDC_MOTOR_ON_TIME = 60*15       ; Time (in SOF interrupt counts) for the motor to stay on: ~15s?
=30						FDC_WAIT_TIME = 30              ; Time (in SOF interrupt counts) to allow for a waiting loop to continue
=13						BPB_SECPERCLUS12_OFF = 13       ; Offset to sectors per cluster in a FAT12 boot sector
=17						BPB_ROOT_MAX_ENTRY12_OFF = 17   ; Offset to the maximum number of entries in the root directory in FAT12 boot sector
=22						BPB_SECPERFAT12_OFF = 22        ; Offset to sectors per FAT on a FAT12 boot sector
.395f24						FDC_TEST
.395f24		8b		phb		                    PHB
.395f25		0b		phd		                    PHD
.395f26		08		php		                    PHP
.395f27		48		pha		                PHA             ; begin setdbr macro
.395f28		08		php		                PHP
.395f29		e2 20		sep #$20	                SEP #$20        ; set A short
.395f2b		a9 00		lda #$00	                LDA #0
.395f2d		48		pha		                PHA
.395f2e		ab		plb		                PLB
.395f2f		28		plp		                PLP
.395f30		68		pla		                PLA             ; end setdbr macro
.395f31		48		pha		                PHA             ; begin setdp macro
.395f32		08		php		                PHP
.395f33		c2 20		rep #$20	                REP #$20        ; set A long
.395f35		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.395f38		5b		tcd		                TCD
.395f39		28		plp		                PLP
.395f3a		68		pla		                PLA             ; end setdp macro
.395f3b		e2 20		sep #$20	                SEP #$20        ; set A short
.395f3d		a9 f0		lda #$f0	                    LDA #$F0
.395f3f		8d 1e 00	sta $001e	                    STA @w CURCOLOR
.395f42		22 42 0b 39	jsl $390b42	                    JSL ICLRSCREEN
.395f46		22 66 09 39	jsl $390966	                    JSL ICSRHOME
.395f4a		c2 30		rep #$30	                REP #$30        ; set A&X long
.395f4c		22 1a 62 39	jsl $39621a	                    JSL FDC_Init
.395f50		b0 03		bcs $395f55	                    BCS init_ok
.395f52		82 20 00	brl $395f75	                    BRL motor_off
.395f55		22 19 69 39	jsl $396919	init_ok             JSL FDC_CHK_MEDIA
.395f59		90 03		bcc $395f5e	                    BCC no_media
.395f5b		82 03 00	brl $395f61	                    BRL is_ok1
.395f5e						no_media
.395f5e		82 14 00	brl $395f75	                    BRL motor_off
.395f61		22 ac 67 39	jsl $3967ac	is_ok1              JSL FDC_MOUNT
.395f65		90 03		bcc $395f6a	                    BCC mount_err
.395f67		82 03 00	brl $395f6d	                    BRL is_ok2
.395f6a						mount_err
.395f6a		82 08 00	brl $395f75	                    BRL motor_off
.395f6d		22 81 5f 39	jsl $395f81	is_ok2              JSL FDC_TEST_PUTBLOCK
.395f71		b0 02		bcs $395f75	                    BCS all_ok
.395f73		80 00		bra $395f75	                    BRA motor_off
.395f75						all_ok
.395f75		22 6c 10 00	jsl $00106c	motor_off           JSL PRINTCR
.395f79		22 ca 62 39	jsl $3962ca	                    JSL FDC_Motor_Off
.395f7d		28		plp		                    PLP
.395f7e		2b		pld		                    PLD
.395f7f		ab		plb		                    PLB
.395f80		6b		rtl		                    RTL
.395f81						FDC_TEST_PUTBLOCK
.395f81		e2 20		sep #$20	                SEP #$20        ; set A short
.395f83		a9 00		lda #$00	                    LDA #0                          ; Initialize the data to write to the drive
.395f85		a2 00 00	ldx #$0000	                    LDX #0
.395f88		9f 00 00 03	sta $030000,x	init_loop           STA @l TEST_BUFFER,X
.395f8c		1a		inc a		                    INC A
.395f8d		e8		inx		                    INX
.395f8e		e0 00 02	cpx #$0200	                    CPX #512
.395f91		d0 f5		bne $395f88	                    BNE init_loop
.395f93		c2 20		rep #$20	                REP #$20        ; set A long
.395f95		a9 00 00	lda #$0000	                    LDA #<>TEST_BUFFER              ; Set BIOS_BUFF_PTR
.395f98		8f 26 03 00	sta $000326	                    STA @l BIOS_BUFF_PTR
.395f9c		a9 03 00	lda #$0003	                    LDA #`TEST_BUFFER
.395f9f		8f 28 03 00	sta $000328	                    STA @l BIOS_BUFF_PTR+2
.395fa3		a9 64 00	lda #$0064	                    LDA #100                        ; Set LBA = 100
.395fa6		8f 22 03 00	sta $000322	                    STA @l BIOS_LBA
.395faa		a9 00 00	lda #$0000	                    LDA #0
.395fad		8f 24 03 00	sta $000324	                    STA @l BIOS_LBA+2
.395fb1		22 40 67 39	jsl $396740	                    JSL FDC_PUTBLOCK                ; Try to write the data
.395fb5		6b		rtl		                    RTL
>395fb6		40 46 3a 53 41 4d 50 4c		BOOT_FILE           .null "@F:SAMPLE.PGX Hello, world!"
>395fbe		45 2e 50 47 58 20 48 65 6c 6c 6f 2c 20 77 6f 72
>395fce		6c 64 21 00
=$020000					TEST_LOCATION = $020000                     ; Location to try to load it
=$030000					TEST_BUFFER = $030000                       ; Temporary location for a cluster buffer
.395fd2						FDC_Check_RQM
.395fd2		0b		phd		                    PHD
.395fd3		08		php		                    PHP
.395fd4		48		pha		                PHA             ; begin setdp macro
.395fd5		08		php		                PHP
.395fd6		c2 20		rep #$20	                REP #$20        ; set A long
.395fd8		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.395fdb		5b		tcd		                TCD
.395fdc		28		plp		                PLP
.395fdd		68		pla		                PLA             ; end setdp macro
.395fde		e2 20		sep #$20	                SEP #$20        ; set A short
.395fe0		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
.395fe2		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.395fe6		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
.395fe8		30 12		bmi $395ffc	                    BMI time_out            ; If so: signal a time out
.395fea		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
.395fee		89 80		bit #$80	                    BIT #FDC_MSR_RQM
.395ff0		f0 f4		beq $395fe6	                    BEQ loop
.395ff2		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
.395ff4		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.395ff8		28		plp		                    PLP
.395ff9		2b		pld		                    PLD
.395ffa		38		sec		                    SEC
.395ffb		60		rts		                    RTS
.395ffc		28		plp		time_out            PLP
.395ffd		2b		pld		                    PLD
.395ffe		18		clc		                    CLC
.395fff		60		rts		                    RTS
.396000						FDC_Check_DRV0_BSY
.396000		0b		phd		                    PHD
.396001		08		php		                    PHP
.396002		48		pha		                PHA             ; begin setdp macro
.396003		08		php		                PHP
.396004		c2 20		rep #$20	                REP #$20        ; set A long
.396006		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396009		5b		tcd		                TCD
.39600a		28		plp		                PLP
.39600b		68		pla		                PLA             ; end setdp macro
.39600c		e2 20		sep #$20	                SEP #$20        ; set A short
.39600e		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
.396010		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.396014		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
.396016		30 12		bmi $39602a	                    BMI time_out            ; If so: signal a time out
.396018		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
.39601c		89 01		bit #$01	                    BIT #FDC_MSR_DRV0BSY
.39601e		d0 f4		bne $396014	                    BNE loop
.396020		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
.396022		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.396026		28		plp		                    PLP
.396027		2b		pld		                    PLD
.396028		38		sec		                    SEC
.396029		60		rts		                    RTS
.39602a		28		plp		time_out            PLP
.39602b		2b		pld		                    PLD
.39602c		18		clc		                    CLC
.39602d		60		rts		                    RTS
.39602e						FDC_Check_CMD_BSY
.39602e		0b		phd		                    PHD
.39602f		08		php		                    PHP
.396030		48		pha		                PHA             ; begin setdp macro
.396031		08		php		                PHP
.396032		c2 20		rep #$20	                REP #$20        ; set A long
.396034		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396037		5b		tcd		                TCD
.396038		28		plp		                PLP
.396039		68		pla		                PLA             ; end setdp macro
.39603a		e2 20		sep #$20	                SEP #$20        ; set A short
.39603c		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
.39603e		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.396042		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
.396044		30 12		bmi $396058	                    BMI time_out            ; If so: signal a time out
.396046		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
.39604a		89 10		bit #$10	                    BIT #FDC_MSR_CMDBSY
.39604c		d0 f4		bne $396042	                    BNE loop
.39604e		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
.396050		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.396054		28		plp		                    PLP
.396055		2b		pld		                    PLD
.396056		38		sec		                    SEC
.396057		60		rts		                    RTS
.396058		28		plp		time_out            PLP
.396059		2b		pld		                    PLD
.39605a		18		clc		                    CLC
.39605b		60		rts		                    RTS
.39605c						FDC_Can_Read_Data
.39605c		0b		phd		                    PHD
.39605d		08		php		                    PHP
.39605e		48		pha		                PHA             ; begin setdp macro
.39605f		08		php		                PHP
.396060		c2 20		rep #$20	                REP #$20        ; set A long
.396062		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396065		5b		tcd		                TCD
.396066		28		plp		                PLP
.396067		68		pla		                PLA             ; end setdp macro
.396068		e2 20		sep #$20	                SEP #$20        ; set A short
.39606a		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
.39606c		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.396070		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
.396072		30 14		bmi $396088	                    BMI time_out            ; If so: signal a time out
.396074		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
.396078		29 40		and #$40	                    AND #FDC_MSR_DIO
.39607a		c9 40		cmp #$40	                    CMP #FDC_MSR_DIO
.39607c		d0 f2		bne $396070	                    BNE loop
.39607e		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
.396080		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.396084		28		plp		                    PLP
.396085		2b		pld		                    PLD
.396086		38		sec		                    SEC
.396087		60		rts		                    RTS
.396088		28		plp		time_out            PLP
.396089		2b		pld		                    PLD
.39608a		18		clc		                    CLC
.39608b		60		rts		                    RTS
.39608c						FDC_CAN_WRITE
.39608c		0b		phd		                    PHD
.39608d		08		php		                    PHP
.39608e		48		pha		                PHA             ; begin setdp macro
.39608f		08		php		                PHP
.396090		c2 20		rep #$20	                REP #$20        ; set A long
.396092		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396095		5b		tcd		                TCD
.396096		28		plp		                PLP
.396097		68		pla		                PLA             ; end setdp macro
.396098		e2 20		sep #$20	                SEP #$20        ; set A short
.39609a		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
.39609c		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.3960a0		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
.3960a2		30 14		bmi $3960b8	                    BMI time_out            ; If so: signal a time out
.3960a4		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
.3960a8		29 c0		and #$c0	                    AND #FDC_MSR_RQM | FDC_MSR_DIO
.3960aa		c9 80		cmp #$80	                    CMP #FDC_MSR_RQM
.3960ac		d0 f2		bne $3960a0	                    BNE loop
.3960ae		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
.3960b0		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.3960b4		28		plp		                    PLP
.3960b5		2b		pld		                    PLD
.3960b6		38		sec		                    SEC
.3960b7		60		rts		                    RTS
.3960b8		28		plp		time_out            PLP
.3960b9		2b		pld		                    PLD
.3960ba		18		clc		                    CLC
.3960bb		60		rts		                    RTS
.3960bc						FDC_DELAY_10MS
.3960bc		da		phx		                    PHX
.3960bd		08		php		                    PHP
.3960be		c2 10		rep #$10	                REP #$10        ; set X long
.3960c0		a2 80 3e	ldx #$3e80	                    LDX #16000          ; Wait for around 10ms
.3960c3		ea		nop		loop                NOP                 ; Each iteration should take 9 cycles
.3960c4		ca		dex		                    DEX
.3960c5		e0 00 00	cpx #$0000	                    CPX #0
.3960c8		d0 f9		bne $3960c3	                    BNE loop
.3960ca		28		plp		                    PLP
.3960cb		fa		plx		                    PLX
.3960cc		6b		rtl		                    RTL
.3960cd						FDC_COMMAND
.3960cd		da		phx		                    PHX
.3960ce		8b		phb		                    PHB
.3960cf		0b		phd		                    PHD
.3960d0		08		php		                    PHP
.3960d1		48		pha		                PHA             ; begin setdbr macro
.3960d2		08		php		                PHP
.3960d3		e2 20		sep #$20	                SEP #$20        ; set A short
.3960d5		a9 00		lda #$00	                LDA #0
.3960d7		48		pha		                PHA
.3960d8		ab		plb		                PLB
.3960d9		28		plp		                PLP
.3960da		68		pla		                PLA             ; end setdbr macro
.3960db		48		pha		                PHA             ; begin setdp macro
.3960dc		08		php		                PHP
.3960dd		c2 20		rep #$20	                REP #$20        ; set A long
.3960df		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.3960e2		5b		tcd		                TCD
.3960e3		28		plp		                PLP
.3960e4		68		pla		                PLA             ; end setdp macro
.3960e5		22 bc 60 39	jsl $3960bc	                    JSL FDC_DELAY_10MS                      ; Wait around 10ms
.3960e9		e2 30		sep #$30	                SEP #$30        ; set A&X short
.3960eb		a2 00		ldx #$00	                    LDX #0
.3960ed		a9 00		lda #$00	                    LDA #0
.3960ef		9d 10 05	sta $0510,x	clr_results         STA FDC_RESULTS,X                       ; Clear the result buffer
.3960f2		e8		inx		                    INX
.3960f3		e0 10		cpx #$10	                    CPX #16
.3960f5		d0 f8		bne $3960ef	                    BNE clr_results
.3960f7		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR                      ; Validate we can send a command
.3960fb		29 c0		and #$c0	                    AND #FDC_MSR_RQM | FDC_MSR_DIO
.3960fd		c9 80		cmp #$80	                    CMP #FDC_MSR_RQM
.3960ff		f0 04		beq $396105	                    BEQ start_send                          ; If so, start sending
.396101		22 1a 62 39	jsl $39621a	fdc_reset           JSL FDC_INIT                            ; Reset the FDC
.396105						start_send
.396105		e2 10		sep #$10	                SEP #$10        ; set X short
.396107		a2 00		ldx #$00	                    LDX #0
.396109		20 d2 5f	jsr $395fd2	send_loop           JSR FDC_Check_RQM                       ; Wait until we can write
.39610c		b0 03		bcs $396111	                    BCS send_param
.39610e		82 5e 00	brl $39616f	                    BRL time_out                            ; If there was a timeout, flag the time out
.396111		bd 00 05	lda $0500,x	send_param          LDA FDC_PARAMETERS,X                    ; Get the parameter/command byte to write
.396114		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA                      ; Send it
.396118		22 bc 60 39	jsl $3960bc	                    JSL FDC_DELAY_10MS                      ; Wait around 10ms for things to settle
.39611c		e8		inx		                    INX                                     ; Advance to the next byte
.39611d		ec 30 05	cpx $0530	                    CPX FDC_PARAM_NUM
.396120		d0 e7		bne $396109	                    BNE send_loop                           ; Keep sending until we've sent them all
.396122		ad 33 05	lda $0533	                    LDA FDC_EXPECT_DAT                      ; Check the data expectation byte
.396125		d0 03		bne $39612a	                    BNE chk_data_dir
.396127		82 80 00	brl $3961aa	                    BRL result_phase                        ; If 0: we just want a result
.39612a		10 3c		bpl $396168	chk_data_dir        BPL rd_data                             ; If >0: we want to read data
.39612c						wr_data
.39612c		a5 0b		lda $030b	wr_data_rdy         LDA FDC_STATUS                          ; Check that the motor is still spinning
.39612e		30 03		bmi $396133	                    BMI wr_chk_rqm
.396130		82 3c 00	brl $39616f	                    BRL time_out                            ; If not, raise an error
.396133		af f4 13 af	lda $af13f4	wr_chk_rqm          LDA @l SIO_FDC_MSR                      ; Wait for ready to write
.396137		89 80		bit #$80	                    BIT #FDC_MSR_RQM
.396139		f0 f1		beq $39612c	                    BEQ wr_data_rdy
.39613b		89 20		bit #$20	                    BIT #FDC_MSR_NONDMA                     ; Check if in execution mode
.39613d		d0 03		bne $396142	                    BNE wr_data_phase                       ; If so: transfer the data
.39613f		82 68 00	brl $3961aa	                    BRL result_phase                          ; If not: it's an error
.396142						wr_data_phase
.396142		c2 10		rep #$10	                REP #$10        ; set X long
.396144		a0 00 00	ldy #$0000	                    LDY #0
.396147		a5 0b		lda $030b	wr_data_loop        LDA FDC_STATUS                          ; Check that the motor is still spinning
.396149		30 03		bmi $39614e	                    BMI wr_chk_nondma
.39614b		82 21 00	brl $39616f	                    BRL time_out                            ; If not, raise an error
.39614e		af f4 13 af	lda $af13f4	wr_chk_nondma       LDA @l SIO_FDC_MSR                      ; Check to see if the FDC is in execution phase
.396152		89 20		bit #$20	                    BIT #FDC_MSR_NONDMA
.396154		f0 54		beq $3961aa	                    BEQ result_phase                        ; If not: break out to result phase
.396156		89 80		bit #$80	                    BIT #FDC_MSR_RQM                        ; Check if we can read data
.396158		f0 ed		beq $396147	                    BEQ wr_data_loop                        ; No: keep waiting
.39615a		b7 26		lda [$0326],y	                    LDA [BIOS_BUFF_PTR],Y                   ; Get the data byte
.39615c		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA                      ; And save it to the buffer
.396160		c8		iny		                    INY                                     ; Move to the next position
.396161		c0 00 02	cpy #$0200	                    CPY #512                                ; TODO: set this from the parameters?
.396164		d0 e1		bne $396147	                    BNE wr_data_loop                        ; If not at the end, keep fetching
.396166		80 42		bra $3961aa	                    BRA result_phase                        ; ready for the result phase
.396168		20 5c 60	jsr $39605c	rd_data             JSR FDC_Can_Read_Data
.39616b		a5 0b		lda $030b	rd_data_rdy         LDA FDC_STATUS                          ; Check that the motor is still spinning
.39616d		30 07		bmi $396176	                    BMI chk_rd_rdy                          ; If so, check to see if the data is ready
.39616f						time_out
.39616f		e2 20		sep #$20	                SEP #$20        ; set A short
.396171		a9 8c		lda #$8c	                    LDA #BIOS_ERR_TIMEOUT                   ; Otherwise: throw a BIOS_ERR_TIMEOUT error
.396173		82 9c 00	brl $396212	                    BRL pass_error
.396176		af f4 13 af	lda $af13f4	chk_rd_rdy          LDA @l SIO_FDC_MSR                      ; Wait for data to be ready
.39617a		29 c0		and #$c0	                    AND #FDC_MSR_RQM | FDC_MSR_DIO
.39617c		c9 c0		cmp #$c0	                    CMP #FDC_MSR_RQM | FDC_MSR_DIO
.39617e		d0 eb		bne $39616b	                    BNE rd_data_rdy
.396180		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR                      ; Check to see if the FDC is in execution phase
.396184		89 20		bit #$20	                    BIT #FDC_MSR_NONDMA
.396186		d0 03		bne $39618b	                    BNE rd_data_phase                       ; If so: transfer the data
.396188		82 83 00	brl $39620e	                    BRL error                               ; If not: it's an error
.39618b						rd_data_phase
.39618b		c2 10		rep #$10	                REP #$10        ; set X long
.39618d		a0 00 00	ldy #$0000	                    LDY #0
.396190		a5 0b		lda $030b	rd_data_loop        LDA FDC_STATUS                          ; Check that the motor is still spinning
.396192		10 db		bpl $39616f	                    BPL time_out                            ; If not: throw a timeout error
.396194		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR                      ; Wait for the next byte to be ready
.396198		29 c0		and #$c0	                    AND #FDC_MSR_RQM | FDC_MSR_DIO
.39619a		c9 c0		cmp #$c0	                    CMP #FDC_MSR_RQM | FDC_MSR_DIO
.39619c		d0 f2		bne $396190	                    BNE rd_data_loop
.39619e		af f5 13 af	lda $af13f5	                    LDA @l SIO_FDC_DTA                      ; Get the data byte
.3961a2		97 26		sta [$0326],y	                    STA [BIOS_BUFF_PTR],Y                   ; And save it to the buffer
.3961a4		c8		iny		                    INY                                     ; Move to the next position
.3961a5		c0 00 02	cpy #$0200	                    CPY #512                                ; TODO: set this from the parameters?
.3961a8		d0 e6		bne $396190	                    BNE rd_data_loop                        ; If not at the end, keep fetching
.3961aa		ad 32 05	lda $0532	result_phase        LDA FDC_RESULT_NUM                      ; If no results are expected...
.3961ad		f0 34		beq $3961e3	                    BEQ chk_busy                            ; Then we're done
.3961af		e2 10		sep #$10	                SEP #$10        ; set X short
.3961b1		a2 00		ldx #$00	                    LDX #0
.3961b3		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME                      ; Set the watchdog timer
.3961b5		22 03 41 39	jsl $394103	                    JSL ISETTIMEOUT
.3961b9		20 5c 60	jsr $39605c	result_loop         JSR FDC_Can_Read_Data                   ; Wait until we can read
.3961bc		90 b1		bcc $39616f	                    BCC time_out                            ; If there was a time out, raise an error
.3961be		af f5 13 af	lda $af13f5	                    LDA @l SIO_FDC_DTA                      ; Yes: get the data
.3961c2		20 5c 60	jsr $39605c	                    JSR FDC_Can_Read_Data                   ; Wait until we can read
.3961c5		90 a8		bcc $39616f	                    BCC time_out                            ; If there was a time out, raise an error
.3961c7		af f5 13 af	lda $af13f5	read_result         LDA @l SIO_FDC_DTA                      ; Yes: get the data
.3961cb		9d 10 05	sta $0510,x	                    STA FDC_RESULTS,X                       ; Save it to the result buffer
.3961ce		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM
.3961d1		90 9c		bcc $39616f	                    BCC time_out                            ; If there was a time out, flag the error
.3961d3		af f4 13 af	lda $af13f4	rd_chk_1            LDA @l SIO_FDC_MSR
.3961d7		29 50		and #$50	                    AND #FDC_MSR_DIO | FDC_MSR_CMDBSY
.3961d9		c9 50		cmp #$50	                    CMP #FDC_MSR_DIO | FDC_MSR_CMDBSY
.3961db		d0 06		bne $3961e3	                    BNE chk_busy
.3961dd		e8		inx		                    INX                                     ; Move to the next result positions
.3961de		ec 32 05	cpx $0532	                    CPX FDC_RESULT_NUM
.3961e1		d0 e4		bne $3961c7	                    BNE read_result                         ; And keep looping until we've read all
.3961e3						chk_busy
.3961e3		c2 10		rep #$10	                REP #$10        ; set X long
.3961e5		a2 0a 00	ldx #$000a	                    LDX #10                                 ; Wait 10ms (I guess?)
.3961e8		22 19 16 39	jsl $391619	                    JSL ILOOP_MS
.3961ec		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR                      ; Check the command busy bit
.3961f0		89 10		bit #$10	                    BIT #FDC_MSR_CMDBSY
.3961f2		f0 12		beq $396206	                    BEQ done                                ; If not set: we're done
.3961f4		20 5c 60	jsr $39605c	                    JSR FDC_Can_Read_Data                   ; Wait until we can read
.3961f7		b0 03		bcs $3961fc	                    BCS get_result_byte
.3961f9		82 73 ff	brl $39616f	                    BRL time_out                            ; If there was a time out, flag the error
.3961fc		af f5 13 af	lda $af13f5	get_result_byte     LDA @l SIO_FDC_DTA                      ; Read the data
.396200		9d 10 05	sta $0510,x	                    STA FDC_RESULTS,X
.396203		e8		inx		                    INX
.396204		80 dd		bra $3961e3	                    BRA chk_busy                            ; And keep checking
.396206						done
.396206		64 20		stz $0320	                    STZ BIOS_STATUS
.396208		28		plp		                    PLP
.396209		2b		pld		                    PLD
.39620a		ab		plb		                    PLB
.39620b		fa		plx		                    PLX
.39620c		38		sec		                    SEC
.39620d		6b		rtl		                    RTL
.39620e						error
.39620e		e2 20		sep #$20	                SEP #$20        ; set A short
.396210		a9 85		lda #$85	                    LDA #BIOS_ERR_CMD
.396212		85 20		sta $0320	pass_error          STA BIOS_STATUS
.396214		28		plp		                    PLP
.396215		2b		pld		                    PLD
.396216		ab		plb		                    PLB
.396217		fa		plx		                    PLX
.396218		18		clc		                    CLC
.396219		6b		rtl		                    RTL
.39621a						FDC_Init
.39621a		08		php		                    PHP
.39621b		c2 10		rep #$10	                REP #$10        ; set X long
.39621d		e2 20		sep #$20	                SEP #$20        ; set A short
.39621f		a9 00		lda #$00	                    LDA #0
.396221		8f f2 13 af	sta $af13f2	                    STA @l SIO_FDC_DOR
.396225		a2 e8 03	ldx #$03e8	                    LDX #1000                   ; Wait
.396228		a0 00 00	ldy #$0000	                    LDY #0
.39622b		22 26 16 39	jsl $391626	                    JSL IDELAY
.39622f		a9 04		lda #$04	                    LDA #FDC_DOR_NRESET         ; Reset the FDC
.396231		8f f2 13 af	sta $af13f2	                    STA @l SIO_FDC_DOR
.396235		ea		nop		                    NOP
.396236		ea		nop		                    NOP
.396237		ea		nop		                    NOP
.396238		ea		nop		                    NOP
.396239		a9 00		lda #$00	                    LDA #$00                    ; Make sure the Speed and Compensation has been set
.39623b		8f f4 13 af	sta $af13f4	                    STA @l SIO_FDC_DSR
.39623f		a9 00		lda #$00	                    LDA #$00                    ; Precompensation set to 0
.396241		8f f7 13 af	sta $af13f7	                    STA @l SIO_FDC_CCR
.396245		a2 8f c5	ldx #$c58f	                    LDX #<>FDC_SEEK_TIME
.396248		a0 20 00	ldy #$0020	                    LDY #`FDC_SEEK_TIME
.39624b		22 26 16 39	jsl $391626	                    JSL IDELAY
.39624f		22 2a 63 39	jsl $39632a	                    JSL FDC_Sense_Int_Status
.396253		90 25		bcc $39627a	                    BCC pass_failure
.396255		22 2a 63 39	jsl $39632a	                    JSL FDC_Sense_Int_Status
.396259		90 1f		bcc $39627a	                    BCC pass_failure
.39625b		22 2a 63 39	jsl $39632a	                    JSL FDC_Sense_Int_Status
.39625f		90 19		bcc $39627a	                    BCC pass_failure
.396261		22 2a 63 39	jsl $39632a	                    JSL FDC_Sense_Int_Status
.396265		90 13		bcc $39627a	                    BCC pass_failure
.396267		22 ec 63 39	jsl $3963ec	                    JSL FDC_Configure_Command
.39626b		90 0d		bcc $39627a	                    BCC pass_failure
.39626d		22 93 63 39	jsl $396393	                    JSL FDC_Specify_Command
.396271		90 07		bcc $39627a	                    BCC pass_failure
.396273		22 96 62 39	jsl $396296	                    JSL FDC_Motor_On
.396277		28		plp		                    PLP
.396278		38		sec		                    SEC
.396279		6b		rtl		                    RTL
.39627a		28		plp		pass_failure        PLP
.39627b		18		clc		                    CLC
.39627c		6b		rtl		                    RTL
.39627d						FDC_MOTOR_NEEDED
.39627d		08		php		                    PHP
.39627e		c2 20		rep #$20	                REP #$20        ; set A long
.396280		78		sei		                    SEI                         ; Turn off interrupts
.396281		a9 84 03	lda #$0384	                    LDA #FDC_MOTOR_ON_TIME      ; Reset the FDC timeout clock
.396284		8f 4e a0 38	sta $38a04e	                    STA @l FDC_MOTOR_TIMER
.396288		e2 20		sep #$20	                SEP #$20        ; set A short
.39628a		af 4c 01 00	lda $00014c	                    LDA @l INT_MASK_REG0
.39628e		29 fe		and #$fe	                    AND #~FNX0_INT00_SOF        ; Enable the SOF interrupt
.396290		8f 4c 01 00	sta $00014c	                    STA @l INT_MASK_REG0
.396294		28		plp		                    PLP
.396295		6b		rtl		                    RTL
.396296						FDC_Motor_On
.396296		08		php		                    PHP
.396297		22 7d 62 39	jsl $39627d	                    JSL FDC_MOTOR_NEEDED        ; Reset the spindle motor timeout clock
.39629b		e2 20		sep #$20	                SEP #$20        ; set A short
.39629d		af f2 13 af	lda $af13f2	                    LDA @l SIO_FDC_DOR          ; Check to see if the motor is already on
.3962a1		89 10		bit #$10	                    BIT #FDC_DOR_MOT0
.3962a3		d0 1f		bne $3962c4	                    BNE done                    ; If so: skip
.3962a5		a9 14		lda #$14	                    LDA #FDC_DOR_MOT0 | FDC_DOR_NRESET
.3962a7		8f f2 13 af	sta $af13f2	                    STA @l SIO_FDC_DOR
.3962ab		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM           ; Make sure we can leave knowing that everything set properly
.3962ae		90 17		bcc $3962c7	                    BCC time_out
.3962b0		a2 1e 8b	ldx #$8b1e	                    LDX #<>FDC_MOTOR_TIME       ; Wait a suitable time for the motor to spin up
.3962b3		a0 41 00	ldy #$0041	                    LDY #`FDC_MOTOR_TIME
.3962b6		22 26 16 39	jsl $391626	                    JSL IDELAY
.3962ba		af 0b 03 00	lda $00030b	                    LDA @l FDC_STATUS
.3962be		09 80		ora #$80	                    ORA #$80                    ; Flag that the motor should be on
.3962c0		8f 0b 03 00	sta $00030b	                    STA @l FDC_STATUS
.3962c4		28		plp		done                PLP
.3962c5		38		sec		                    SEC
.3962c6		6b		rtl		                    RTL
.3962c7		28		plp		time_out            PLP                         ; Return a timeout error
.3962c8		18		clc		                    CLC
.3962c9		6b		rtl		                    RTL
.3962ca						FDC_Motor_Off
.3962ca		08		php		                    PHP
.3962cb		e2 20		sep #$20	                SEP #$20        ; set A short
.3962cd		a9 04		lda #$04	                    LDA #FDC_DOR_NRESET
.3962cf		8f f2 13 af	sta $af13f2	                    STA @L SIO_FDC_DOR
.3962d3		c2 20		rep #$20	                REP #$20        ; set A long
.3962d5		78		sei		                    SEI                         ; Turn off interrupts
.3962d6		a9 00 00	lda #$0000	                    LDA #0                      ; Set FDC motor timeout counter to 0 to disable it
.3962d9		8f 4e a0 38	sta $38a04e	                    STA @l FDC_MOTOR_TIMER
.3962dd		e2 20		sep #$20	                SEP #$20        ; set A short
.3962df		af 4c 01 00	lda $00014c	                    LDA @l INT_MASK_REG0
.3962e3		09 01		ora #$01	                    ORA #FNX0_INT00_SOF         ; Disable the SOF interrupt
.3962e5		8f 4c 01 00	sta $00014c	                    STA @l INT_MASK_REG0
.3962e9		af 0b 03 00	lda $00030b	                    LDA @l FDC_STATUS
.3962ed		29 7f		and #$7f	                    AND #$7F                    ; Flag that the motor should be off
.3962ef		8f 0b 03 00	sta $00030b	                    STA @l FDC_STATUS
.3962f3		28		plp		                    PLP
.3962f4		6b		rtl		                    RTL
.3962f5						FDC_Recalibrate_Command
.3962f5		0b		phd		                    PHD
.3962f6		08		php		                    PHP
.3962f7		48		pha		                PHA             ; begin setdp macro
.3962f8		08		php		                PHP
.3962f9		c2 20		rep #$20	                REP #$20        ; set A long
.3962fb		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.3962fe		5b		tcd		                TCD
.3962ff		28		plp		                PLP
.396300		68		pla		                PLA             ; end setdp macro
.396301		22 7d 62 39	jsl $39627d	                    JSL FDC_MOTOR_NEEDED        ; Reset the spindle motor timeout clock
.396305		e2 20		sep #$20	                SEP #$20        ; set A short
.396307		a9 07		lda #$07	                    LDA #FDC_CMD_RECALIBRATE    ; RECALIBRATE Command
.396309		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
.39630c		a5 00		lda $0300	                    LDA FDC_DRIVE
.39630e		8d 01 05	sta $0501	                    STA FDC_PARAMETERS+1
.396311		a9 02		lda #$02	                    LDA #2
.396313		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM           ; 2 parameters
.396316		9c 33 05	stz $0533	                    STZ FDC_EXPECT_DAT          ; 0 data
.396319		9c 32 05	stz $0532	                    STZ FDC_RESULT_NUM          ; 0 results
.39631c		22 cd 60 39	jsl $3960cd	                    JSL FDC_COMMAND             ; Issue the command
.396320		90 04		bcc $396326	                    BCC pass_failure            ; If failure, pass the failure up
.396322		28		plp		                    PLP
.396323		2b		pld		                    PLD
.396324		38		sec		                    SEC
.396325		6b		rtl		                    RTL
.396326		28		plp		pass_failure        PLP
.396327		2b		pld		                    PLD
.396328		18		clc		                    CLC
.396329		6b		rtl		                    RTL
.39632a						FDC_Sense_Int_Status
.39632a		8b		phb		                    PHB
.39632b		0b		phd		                    PHD
.39632c		08		php		                    PHP
.39632d		48		pha		                PHA             ; begin setdbr macro
.39632e		08		php		                PHP
.39632f		e2 20		sep #$20	                SEP #$20        ; set A short
.396331		a9 00		lda #$00	                LDA #0
.396333		48		pha		                PHA
.396334		ab		plb		                PLB
.396335		28		plp		                PLP
.396336		68		pla		                PLA             ; end setdbr macro
.396337		48		pha		                PHA             ; begin setdp macro
.396338		08		php		                PHP
.396339		c2 20		rep #$20	                REP #$20        ; set A long
.39633b		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.39633e		5b		tcd		                TCD
.39633f		28		plp		                PLP
.396340		68		pla		                PLA             ; end setdp macro
.396341		c2 30		rep #$30	                REP #$30        ; set A&X long
.396343		a2 0a 00	ldx #$000a	                    LDX #10                            ; Wait for 10ms
.396346		22 19 16 39	jsl $391619	                    JSL ILOOP_MS
.39634a		e2 20		sep #$20	                SEP #$20        ; set A short
.39634c		64 06		stz $0306	                    STZ FDC_ST0                         ; Clear ST0
.39634e		a9 ff		lda #$ff	                    LDA #$FF
.396350		85 0a		sta $030a	                    STA FDC_PCN                         ; Set PCN to some obviously bad value
.396352		20 2e 60	jsr $39602e	                    JSR FDC_Check_CMD_BSY               ; Check I can send a command
.396355		90 30		bcc $396387	                    BCC time_out                        ; If there was a time out, raise an error
.396357		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM                   ; Check if I can transfer data
.39635a		90 2b		bcc $396387	                    BCC time_out                        ; If there was a time out, raise an error
.39635c		a9 08		lda #$08	                    LDA #FDC_CMD_SENSE_INTERRUPT
.39635e		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
.396362		20 5c 60	jsr $39605c	                    JSR FDC_Can_Read_Data
.396365		90 20		bcc $396387	                    BCC time_out                        ; If there was a time out, raise an error
.396367		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM                   ; Check if I can transfer data
.39636a		90 1b		bcc $396387	                    BCC time_out                        ; If there was a time out, raise an error
.39636c		af f5 13 af	lda $af13f5	                    LDA @l SIO_FDC_DTA
.396370		85 06		sta $0306	                    STA FDC_ST0                         ; --- ST0 ---
.396372		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM                   ; Check if I can transfer data
.396375		90 10		bcc $396387	                    BCC time_out                        ; If there was a time out, raise an error
.396377		af f5 13 af	lda $af13f5	                    LDA @l SIO_FDC_DTA
.39637b		85 0a		sta $030a	                    STA FDC_PCN                         ; --- Cylinder ---
.39637d		e2 20		sep #$20	                SEP #$20        ; set A short
.39637f		9c 20 03	stz $0320	                    STZ @w BIOS_STATUS
.396382		28		plp		                    PLP
.396383		2b		pld		                    PLD
.396384		ab		plb		                    PLB
.396385		38		sec		                    SEC
.396386		6b		rtl		                    RTL
.396387						time_out
.396387		e2 20		sep #$20	                SEP #$20        ; set A short
.396389		a9 8c		lda #$8c	                    LDA #BIOS_ERR_TIMEOUT               ; Return a time out error
.39638b		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
.39638e		28		plp		                    PLP
.39638f		2b		pld		                    PLD
.396390		ab		plb		                    PLB
.396391		18		clc		                    CLC
.396392		6b		rtl		                    RTL
.396393						FDC_Specify_Command
.396393		8b		phb		                    PHB
.396394		0b		phd		                    PHD
.396395		08		php		                    PHP
.396396		48		pha		                PHA             ; begin setdbr macro
.396397		08		php		                PHP
.396398		e2 20		sep #$20	                SEP #$20        ; set A short
.39639a		a9 00		lda #$00	                LDA #0
.39639c		48		pha		                PHA
.39639d		ab		plb		                PLB
.39639e		28		plp		                PLP
.39639f		68		pla		                PLA             ; end setdbr macro
.3963a0		48		pha		                PHA             ; begin setdp macro
.3963a1		08		php		                PHP
.3963a2		c2 20		rep #$20	                REP #$20        ; set A long
.3963a4		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.3963a7		5b		tcd		                TCD
.3963a8		28		plp		                PLP
.3963a9		68		pla		                PLA             ; end setdp macro
.3963aa		c2 30		rep #$30	                REP #$30        ; set A&X long
.3963ac		a2 0a 00	ldx #$000a	                    LDX #10                 ; Wait for 10ms
.3963af		22 19 16 39	jsl $391619	                    JSL ILOOP_MS
.3963b3		e2 20		sep #$20	                SEP #$20        ; set A short
.3963b5		20 2e 60	jsr $39602e	                    JSR FDC_Check_CMD_BSY   ; Check I can send a command
.3963b8		90 26		bcc $3963e0	                    BCC time_out            ; If there was a time out, raise an error
.3963ba		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM       ; Check if I can transfer data
.3963bd		90 21		bcc $3963e0	                    BCC time_out            ; If there was a time out, raise an error
.3963bf		a9 03		lda #$03	                    LDA #FDC_CMD_SPECIFY    ; Specify Command
.3963c1		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
.3963c5		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM       ; Check if I can transfer data
.3963c8		90 16		bcc $3963e0	                    BCC time_out            ; If there was a time out, raise an error
.3963ca		a9 cf		lda #$cf	                    LDA #$CF
.3963cc		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
.3963d0		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM       ; Check if I can transfer data
.3963d3		90 0b		bcc $3963e0	                    BCC time_out            ; If there was a time out, raise an error
.3963d5		a9 01		lda #$01	                    LDA #$01                ; 1 = Non-DMA
.3963d7		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
.3963db		28		plp		                    PLP
.3963dc		2b		pld		                    PLD
.3963dd		ab		plb		                    PLB
.3963de		38		sec		                    SEC
.3963df		6b		rtl		                    RTL
.3963e0						time_out
.3963e0		e2 20		sep #$20	                SEP #$20        ; set A short
.3963e2		a9 8c		lda #$8c	                    LDA #BIOS_ERR_TIMEOUT   ; Return a time out error
.3963e4		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
.3963e7		28		plp		                    PLP
.3963e8		2b		pld		                    PLD
.3963e9		ab		plb		                    PLB
.3963ea		18		clc		                    CLC
.3963eb		6b		rtl		                    RTL
.3963ec						FDC_Configure_Command
.3963ec		8b		phb		                    PHB
.3963ed		0b		phd		                    PHD
.3963ee		08		php		                    PHP
.3963ef		48		pha		                PHA             ; begin setdbr macro
.3963f0		08		php		                PHP
.3963f1		e2 20		sep #$20	                SEP #$20        ; set A short
.3963f3		a9 00		lda #$00	                LDA #0
.3963f5		48		pha		                PHA
.3963f6		ab		plb		                PLB
.3963f7		28		plp		                PLP
.3963f8		68		pla		                PLA             ; end setdbr macro
.3963f9		48		pha		                PHA             ; begin setdp macro
.3963fa		08		php		                PHP
.3963fb		c2 20		rep #$20	                REP #$20        ; set A long
.3963fd		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396400		5b		tcd		                TCD
.396401		28		plp		                PLP
.396402		68		pla		                PLA             ; end setdp macro
.396403		c2 30		rep #$30	                REP #$30        ; set A&X long
.396405		a2 0a 00	ldx #$000a	                    LDX #10                 ; Wait for 10ms
.396408		22 19 16 39	jsl $391619	                    JSL ILOOP_MS
.39640c		e2 20		sep #$20	                SEP #$20        ; set A short
.39640e		20 2e 60	jsr $39602e	                    JSR FDC_Check_CMD_BSY   ; Check I can send a command
.396411		90 36		bcc $396449	                    BCC time_out            ; If there was a time out, raise an error
.396413		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM       ; Check if I can transfer data
.396416		90 31		bcc $396449	                    BCC time_out            ; If there was a time out, raise an error
.396418		a9 13		lda #$13	                    LDA #FDC_CMD_CONFIGURE  ; Specify Command
.39641a		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
.39641e		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM       ; Check if I can transfer data
.396421		90 26		bcc $396449	                    BCC time_out            ; If there was a time out, raise an error
.396423		a9 00		lda #$00	                    LDA #$00
.396425		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
.396429		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM       ; Check if I can transfer data
.39642c		90 1b		bcc $396449	                    BCC time_out            ; If there was a time out, raise an error
.39642e		a9 44		lda #$44	                    LDA #$44                ; Implied Seek, FIFOTHR = 4 byte
.396430		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
.396434		20 d2 5f	jsr $395fd2	                    JSR FDC_Check_RQM       ; Check if I can transfer data
.396437		90 10		bcc $396449	                    BCC time_out            ; If there was a time out, raise an error
.396439		a9 00		lda #$00	                    LDA #$00
.39643b		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
.39643f		20 2e 60	jsr $39602e	                    JSR FDC_Check_CMD_BSY   ; Check I can send a command
.396442		90 05		bcc $396449	                    BCC time_out            ; If there was a time out, raise an error
.396444		28		plp		                    PLP
.396445		2b		pld		                    PLD
.396446		ab		plb		                    PLB
.396447		38		sec		                    SEC
.396448		6b		rtl		                    RTL
.396449						time_out
.396449		e2 20		sep #$20	                SEP #$20        ; set A short
.39644b		a9 8c		lda #$8c	                    LDA #BIOS_ERR_TIMEOUT   ; Return a time out error
.39644d		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
.396450		28		plp		                    PLP
.396451		2b		pld		                    PLD
.396452		ab		plb		                    PLB
.396453		18		clc		                    CLC
.396454		6b		rtl		                    RTL
.396455						FDC_Read_ID_Command
.396455		8b		phb		                    PHB
.396456		0b		phd		                    PHD
.396457		08		php		                    PHP
.396458		48		pha		                PHA             ; begin setdbr macro
.396459		08		php		                PHP
.39645a		e2 20		sep #$20	                SEP #$20        ; set A short
.39645c		a9 00		lda #$00	                LDA #0
.39645e		48		pha		                PHA
.39645f		ab		plb		                PLB
.396460		28		plp		                PLP
.396461		68		pla		                PLA             ; end setdbr macro
.396462		48		pha		                PHA             ; begin setdp macro
.396463		08		php		                PHP
.396464		c2 20		rep #$20	                REP #$20        ; set A long
.396466		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396469		5b		tcd		                TCD
.39646a		28		plp		                PLP
.39646b		68		pla		                PLA             ; end setdp macro
.39646c		e2 20		sep #$20	                SEP #$20        ; set A short
.39646e		a9 0a		lda #$0a	                    LDA #FDC_CMD_READ_ID                ; READID Command
.396470		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
.396473		a9 01		lda #$01	                    LDA #1
.396475		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 4 parameter (the command)
.396478		9c 33 05	stz $0533	                    STZ FDC_EXPECT_DAT                  ; 0 data
.39647b		a9 07		lda #$07	                    LDA #7
.39647d		8d 32 05	sta $0532	                    STA FDC_RESULT_NUM                  ; 7 results
.396480		22 cd 60 39	jsl $3960cd	                    JSL FDC_COMMAND                     ; Issue the command
.396484		90 27		bcc $3964ad	                    BCC pass_failure
.396486		ad 10 05	lda $0510	                    LDA FDC_RESULTS
.396489		85 06		sta $0306	                    STA FDC_ST0                         ; Get ST0
.39648b		ad 11 05	lda $0511	                    LDA FDC_RESULTS+1
.39648e		85 07		sta $0307	                    STA FDC_ST1                         ; Get ST1
.396490		ad 12 05	lda $0512	                    LDA FDC_RESULTS+2
.396493		85 08		sta $0308	                    STA FDC_ST2                         ; Get ST2
.396495		ad 13 05	lda $0513	                    LDA FDC_RESULTS+3
.396498		85 02		sta $0302	                    STA FDC_CYLINDER                    ; Get the cylinder
.39649a		ad 14 05	lda $0514	                    LDA FDC_RESULTS+4
.39649d		85 01		sta $0301	                    STA FDC_HEAD                        ; Get the head
.39649f		ad 15 05	lda $0515	                    LDA FDC_RESULTS+5
.3964a2		85 0a		sta $030a	                    STA FDC_PCN                         ; Get the sector
.3964a4		ad 16 05	lda $0516	                    LDA FDC_RESULTS+6
.3964a7		85 04		sta $0304	                    STA FDC_SECTOR_SIZE                 ; Get the sector size code
.3964a9		28		plp		                    PLP
.3964aa		2b		pld		                    PLD
.3964ab		ab		plb		                    PLB
.3964ac		6b		rtl		                    RTL
.3964ad		28		plp		pass_failure        PLP
.3964ae		2b		pld		                    PLD
.3964af		ab		plb		                    PLB
.3964b0		18		clc		                    CLC
.3964b1		6b		rtl		                    RTL
.3964b2						FDC_DumpReg_Command
.3964b2		0b		phd		                    PHD
.3964b3		08		php		                    PHP
.3964b4		e2 20		sep #$20	                SEP #$20        ; set A short
.3964b6		a9 0e		lda #$0e	                    LDA #FDC_CMD_DUMPREG                ; DUMPREG Command
.3964b8		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
.3964bb		a9 01		lda #$01	                    LDA #1
.3964bd		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 4 parameter (the command)
.3964c0		9c 33 05	stz $0533	                    STZ FDC_EXPECT_DAT                  ; 0 data
.3964c3		a9 0a		lda #$0a	                    LDA #10
.3964c5		8d 32 05	sta $0532	                    STA FDC_RESULT_NUM                  ; 10 results
.3964c8		22 cd 60 39	jsl $3960cd	                    JSL FDC_COMMAND                     ; Issue the command
.3964cc		90 03		bcc $3964d1	                    BCC pass_failure
.3964ce		28		plp		                    PLP
.3964cf		2b		pld		                    PLD
.3964d0		6b		rtl		                    RTL
.3964d1		28		plp		pass_failure        PLP
.3964d2		2b		pld		                    PLD
.3964d3		18		clc		                    CLC
.3964d4		6b		rtl		                    RTL
.3964d5						FDC_Seek_Track
.3964d5		8b		phb		                    PHB
.3964d6		0b		phd		                    PHD
.3964d7		08		php		                    PHP
.3964d8		48		pha		                PHA             ; begin setdbr macro
.3964d9		08		php		                PHP
.3964da		e2 20		sep #$20	                SEP #$20        ; set A short
.3964dc		a9 00		lda #$00	                LDA #0
.3964de		48		pha		                PHA
.3964df		ab		plb		                PLB
.3964e0		28		plp		                PLP
.3964e1		68		pla		                PLA             ; end setdbr macro
.3964e2		48		pha		                PHA             ; begin setdp macro
.3964e3		08		php		                PHP
.3964e4		c2 20		rep #$20	                REP #$20        ; set A long
.3964e6		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.3964e9		5b		tcd		                TCD
.3964ea		28		plp		                PLP
.3964eb		68		pla		                PLA             ; end setdp macro
.3964ec		22 7d 62 39	jsl $39627d	                    JSL FDC_MOTOR_NEEDED                ; Reset the spindle motor timeout clock
.3964f0		e2 20		sep #$20	                SEP #$20        ; set A short
.3964f2		a9 0f		lda #$0f	                    LDA #FDC_CMD_SEEK                   ; Seek Command
.3964f4		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
.3964f7		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Get the head
.3964f9		29 01		and #$01	                    AND #$01
.3964fb		0a		asl a		                    ASL A
.3964fc		0a		asl a		                    ASL A
.3964fd		05 00		ora $0300	                    ORA FDC_DRIVE                       ; And the drive number
.3964ff		8d 01 05	sta $0501	                    STA FDC_PARAMETERS+1
.396502		a5 02		lda $0302	                    LDA FDC_CYLINDER                    ; And the track
.396504		8d 02 05	sta $0502	                    STA FDC_PARAMETERS+2
.396507		a9 03		lda #$03	                    LDA #3
.396509		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 3 parameter (the command)
.39650c		9c 33 05	stz $0533	                    STZ FDC_EXPECT_DAT                  ; 0 data
.39650f		9c 32 05	stz $0532	                    STZ FDC_RESULT_NUM                  ; 0 results
.396512		22 cd 60 39	jsl $3960cd	                    JSL FDC_COMMAND                     ; Issue the command
.396516		90 05		bcc $39651d	                    BCC pass_failure
.396518		28		plp		                    PLP
.396519		2b		pld		                    PLD
.39651a		ab		plb		                    PLB
.39651b		38		sec		                    SEC
.39651c		6b		rtl		                    RTL
.39651d		28		plp		pass_failure        PLP
.39651e		2b		pld		                    PLD
.39651f		ab		plb		                    PLB
.396520		18		clc		                    CLC
.396521		6b		rtl		                    RTL
.396522						FDC_Read_Sector
.396522		8b		phb		                    PHB
.396523		0b		phd		                    PHD
.396524		08		php		                    PHP
.396525		48		pha		                PHA             ; begin setdbr macro
.396526		08		php		                PHP
.396527		e2 20		sep #$20	                SEP #$20        ; set A short
.396529		a9 00		lda #$00	                LDA #0
.39652b		48		pha		                PHA
.39652c		ab		plb		                PLB
.39652d		28		plp		                PLP
.39652e		68		pla		                PLA             ; end setdbr macro
.39652f		48		pha		                PHA             ; begin setdp macro
.396530		08		php		                PHP
.396531		c2 20		rep #$20	                REP #$20        ; set A long
.396533		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396536		5b		tcd		                TCD
.396537		28		plp		                PLP
.396538		68		pla		                PLA             ; end setdp macro
.396539		22 7d 62 39	jsl $39627d	                    JSL FDC_MOTOR_NEEDED                ; Reset the spindle motor timeout clock
.39653d		e2 20		sep #$20	                SEP #$20        ; set A short
.39653f		a9 06		lda #$06	                    LDA #FDC_CMD_READ_DATA              ; The READ_DATA command
.396541		09 40		ora #$40	                    ORA #FDC_CMD_MFM                    ; Turn on MFM mode
.396543		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
.396546		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Get the head
.396548		29 01		and #$01	                    AND #$01
.39654a		0a		asl a		                    ASL A
.39654b		0a		asl a		                    ASL A
.39654c		05 00		ora $0300	                    ORA FDC_DRIVE                       ; And the drive number
.39654e		8d 01 05	sta $0501	                    STA FDC_PARAMETERS+1
.396551		a5 02		lda $0302	                    LDA FDC_CYLINDER                    ; Send the cylinder number
.396553		8d 02 05	sta $0502	                    STA FDC_PARAMETERS+2
.396556		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Send the head number
.396558		8d 03 05	sta $0503	                    STA FDC_PARAMETERS+3
.39655b		a5 03		lda $0303	                    LDA FDC_SECTOR                      ; Send the sector number
.39655d		8d 04 05	sta $0504	                    STA FDC_PARAMETERS+4
.396560		a9 02		lda #$02	                    LDA #$02                            ; --- N ---- Sector Size (2 = 512Bytes)
.396562		8d 05 05	sta $0505	                    STA FDC_PARAMETERS+5
.396565		a9 12		lda #$12	                    LDA #18                             ; --- EOT ---- End of Track
.396567		8d 06 05	sta $0506	                    STA FDC_PARAMETERS+6
.39656a		a9 1b		lda #$1b	                    LDA #$1B                            ; --- GPL ---- End of Track
.39656c		8d 07 05	sta $0507	                    STA FDC_PARAMETERS+7
.39656f		a9 ff		lda #$ff	                    LDA #$FF                            ; --- DTL ---- Special sector size
.396571		8d 08 05	sta $0508	                    STA FDC_PARAMETERS+8
.396574		a9 09		lda #$09	                    LDA #9
.396576		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 9 parameter (the command)
.396579		a9 01		lda #$01	                    LDA #1
.39657b		8d 33 05	sta $0533	                    STA FDC_EXPECT_DAT                  ; Expect data
.39657e		a9 07		lda #$07	                    LDA #7
.396580		8d 32 05	sta $0532	                    STA FDC_RESULT_NUM                  ; 7 results
.396583		22 cd 60 39	jsl $3960cd	command             JSL FDC_COMMAND                     ; Issue the command
.396587		08		php		                    PHP
.396588		ad 10 05	lda $0510	get_results         LDA FDC_RESULTS
.39658b		85 06		sta $0306	                    STA FDC_ST0                         ; --- ST0 ----
.39658d		ad 11 05	lda $0511	                    LDA FDC_RESULTS+1
.396590		85 07		sta $0307	                    STA FDC_ST1                         ; --- ST1 ----
.396592		ad 12 05	lda $0512	                    LDA FDC_RESULTS+2
.396595		85 08		sta $0308	                    STA FDC_ST2                         ; --- ST2 ----
.396597		ad 13 05	lda $0513	                    LDA FDC_RESULTS+3
.39659a		85 02		sta $0302	                    STA FDC_CYLINDER                    ; -- C ---
.39659c		ad 14 05	lda $0514	                    LDA FDC_RESULTS+4
.39659f		85 01		sta $0301	                    STA FDC_HEAD                        ; --- H ---
.3965a1		ad 15 05	lda $0515	                    LDA FDC_RESULTS+5
.3965a4		85 0a		sta $030a	                    STA FDC_PCN                      ; --- R ---
.3965a6		ad 16 05	lda $0516	                    LDA FDC_RESULTS+6
.3965a9		85 04		sta $0304	                    STA FDC_SECTOR_SIZE                 ; --- N ---
.3965ab		28		plp		                    PLP
.3965ac		90 04		bcc $3965b2	                    BCC pass_failure
.3965ae		28		plp		done                PLP
.3965af		2b		pld		                    PLD
.3965b0		ab		plb		                    PLB
.3965b1		6b		rtl		                    RTL
.3965b2		28		plp		pass_failure        PLP
.3965b3		2b		pld		                    PLD
.3965b4		ab		plb		                    PLB
.3965b5		18		clc		                    CLC
.3965b6		6b		rtl		                    RTL
.3965b7						FDC_Write_Sector
.3965b7		8b		phb		                    PHB
.3965b8		0b		phd		                    PHD
.3965b9		08		php		                    PHP
.3965ba		48		pha		                PHA             ; begin setdbr macro
.3965bb		08		php		                PHP
.3965bc		e2 20		sep #$20	                SEP #$20        ; set A short
.3965be		a9 00		lda #$00	                LDA #0
.3965c0		48		pha		                PHA
.3965c1		ab		plb		                PLB
.3965c2		28		plp		                PLP
.3965c3		68		pla		                PLA             ; end setdbr macro
.3965c4		48		pha		                PHA             ; begin setdp macro
.3965c5		08		php		                PHP
.3965c6		c2 20		rep #$20	                REP #$20        ; set A long
.3965c8		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.3965cb		5b		tcd		                TCD
.3965cc		28		plp		                PLP
.3965cd		68		pla		                PLA             ; end setdp macro
.3965ce		e2 20		sep #$20	                SEP #$20        ; set A short
.3965d0		22 7d 62 39	jsl $39627d	                    JSL FDC_MOTOR_NEEDED                ; Reset the spindle motor timeout clock
.3965d4		a9 05		lda #$05	                    LDA #FDC_CMD_WRITE_DATA             ; The WRITE_DATA command
.3965d6		09 40		ora #$40	                    ORA #FDC_CMD_MFM                    ; Turn on MFM mode
.3965d8		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
.3965db		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Get the head
.3965dd		29 01		and #$01	                    AND #$01
.3965df		0a		asl a		                    ASL A
.3965e0		0a		asl a		                    ASL A
.3965e1		05 00		ora $0300	                    ORA FDC_DRIVE                       ; And the drive number
.3965e3		8d 01 05	sta $0501	                    STA FDC_PARAMETERS+1
.3965e6		a5 02		lda $0302	                    LDA FDC_CYLINDER                    ; Send the cylinder number
.3965e8		8d 02 05	sta $0502	                    STA FDC_PARAMETERS+2
.3965eb		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Send the head number
.3965ed		8d 03 05	sta $0503	                    STA FDC_PARAMETERS+3
.3965f0		a5 03		lda $0303	                    LDA FDC_SECTOR                      ; Send the sector number
.3965f2		8d 04 05	sta $0504	                    STA FDC_PARAMETERS+4
.3965f5		a9 02		lda #$02	                    LDA #$02                            ; --- N ---- Sector Size (2 = 512Bytes)
.3965f7		8d 05 05	sta $0505	                    STA FDC_PARAMETERS+5
.3965fa		a9 12		lda #$12	                    LDA #18                             ; --- EOT ---- End of Track
.3965fc		8d 06 05	sta $0506	                    STA FDC_PARAMETERS+6
.3965ff		a9 1b		lda #$1b	                    LDA #$1B                            ; --- GPL ---- End of Track
.396601		8d 07 05	sta $0507	                    STA FDC_PARAMETERS+7
.396604		a9 ff		lda #$ff	                    LDA #$FF                            ; --- DTL ---- Special sector size
.396606		8d 08 05	sta $0508	                    STA FDC_PARAMETERS+8
.396609		a9 09		lda #$09	                    LDA #9
.39660b		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 9 parameter (the command)
.39660e		a9 ff		lda #$ff	                    LDA #$FF
.396610		8d 33 05	sta $0533	                    STA FDC_EXPECT_DAT                  ; Expect to write data
.396613		a9 07		lda #$07	                    LDA #7
.396615		8d 32 05	sta $0532	                    STA FDC_RESULT_NUM                  ; 7 results
.396618		22 cd 60 39	jsl $3960cd	command             JSL FDC_COMMAND                     ; Issue the command
.39661c		08		php		                    PHP
.39661d		ad 10 05	lda $0510	get_results         LDA FDC_RESULTS
.396620		85 06		sta $0306	                    STA FDC_ST0                         ; --- ST0 ---
.396622		ad 11 05	lda $0511	                    LDA FDC_RESULTS+1
.396625		85 07		sta $0307	                    STA FDC_ST1                         ; --- ST1 ---
.396627		ad 12 05	lda $0512	                    LDA FDC_RESULTS+2
.39662a		85 08		sta $0308	                    STA FDC_ST2                         ; --- ST2 ---
.39662c		ad 13 05	lda $0513	                    LDA FDC_RESULTS+3
.39662f		85 02		sta $0302	                    STA FDC_CYLINDER                    ; --- C ---
.396631		ad 14 05	lda $0514	                    LDA FDC_RESULTS+4
.396634		85 01		sta $0301	                    STA FDC_HEAD                        ; --- H ---
.396636		ad 15 05	lda $0515	                    LDA FDC_RESULTS+5
.396639		85 0a		sta $030a	                    STA FDC_PCN                      ; --- R ---
.39663b		ad 16 05	lda $0516	                    LDA FDC_RESULTS+6
.39663e		85 04		sta $0304	                    STA FDC_SECTOR_SIZE                 ; --- N ---
.396640		28		plp		check_status        PLP
.396641		90 04		bcc $396647	                    BCC pass_failure
.396643		28		plp		done                PLP
.396644		2b		pld		                    PLD
.396645		ab		plb		                    PLB
.396646		6b		rtl		                    RTL
.396647		28		plp		pass_failure        PLP
.396648		2b		pld		                    PLD
.396649		ab		plb		                    PLB
.39664a		18		clc		                    CLC
.39664b		6b		rtl		                    RTL
.39664c						DIVIDE32
.39664c		da		phx		                    PHX
.39664d		5a		phy		                    PHY
.39664e		0b		phd		                    PHD
.39664f		08		php		                    PHP
.396650		48		pha		                PHA             ; begin setdp macro
.396651		08		php		                PHP
.396652		c2 20		rep #$20	                REP #$20        ; set A long
.396654		a9 0c 03	lda #$030c	                LDA #DIVIDEND         ; set DP to page 0
.396657		5b		tcd		                TCD
.396658		28		plp		                PLP
.396659		68		pla		                PLA             ; end setdp macro
.39665a		c2 30		rep #$30	                REP #$30        ; set A&X long
.39665c		64 08		stz $0314	                    STZ REMAINDER           ; Initialize the remainder
.39665e		64 0a		stz $0316	                    STZ REMAINDER+2
.396660		a2 20 00	ldx #$0020	                    LDX #32                 ; Set the number of bits to process
.396663		06 00		asl $030c	loop                ASL DIVIDEND
.396665		26 02		rol $030e	                    ROL DIVIDEND+2
.396667		26 08		rol $0314	                    ROL REMAINDER
.396669		26 0a		rol $0316	                    ROL REMAINDER+2
.39666b		a5 08		lda $0314	                    LDA REMAINDER
.39666d		38		sec		                    SEC
.39666e		e5 04		sbc $0310	                    SBC DIVISOR
.396670		a8		tay		                    TAY
.396671		a5 0a		lda $0316	                    LDA REMAINDER+2
.396673		e5 06		sbc $0312	                    SBC DIVISOR+2
.396675		90 06		bcc $39667d	                    BCC skip
.396677		85 0a		sta $0316	                    STA REMAINDER+2
.396679		84 08		sty $0314	                    STY REMAINDER
.39667b		e6 00		inc $030c	                    INC DIVIDEND
.39667d		ca		dex		skip                DEX
.39667e		d0 e3		bne $396663	                    BNE loop
.396680		28		plp		                    PLP
.396681		2b		pld		                    PLD
.396682		7a		ply		                    PLY
.396683		fa		plx		                    PLX
.396684		60		rts		                    RTS
.396685						LBA2CHS
.396685		8b		phb		                    PHB
.396686		0b		phd		                    PHD
.396687		08		php		                    PHP
.396688		48		pha		                PHA             ; begin setdbr macro
.396689		08		php		                PHP
.39668a		e2 20		sep #$20	                SEP #$20        ; set A short
.39668c		a9 00		lda #$00	                LDA #0
.39668e		48		pha		                PHA
.39668f		ab		plb		                PLB
.396690		28		plp		                PLP
.396691		68		pla		                PLA             ; end setdbr macro
.396692		48		pha		                PHA             ; begin setdp macro
.396693		08		php		                PHP
.396694		c2 20		rep #$20	                REP #$20        ; set A long
.396696		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396699		5b		tcd		                TCD
.39669a		28		plp		                PLP
.39669b		68		pla		                PLA             ; end setdp macro
.39669c		c2 30		rep #$30	                REP #$30        ; set A&X long
.39669e		a5 22		lda $0322	                    LDA BIOS_LBA
.3966a0		85 0c		sta $030c	                    STA DIVIDEND
.3966a2		a5 24		lda $0324	                    LDA BIOS_LBA+2
.3966a4		85 0e		sta $030e	                    STA DIVIDEND+2
.3966a6		a9 24 00	lda #$0024	                    LDA #36
.3966a9		85 10		sta $0310	                    STA DIVISOR
.3966ab		64 12		stz $0312	                    STZ DIVISOR+2
.3966ad		20 4c 66	jsr $39664c	                    JSR DIVIDE32
.3966b0		e2 20		sep #$20	                SEP #$20        ; set A short
.3966b2		a5 0c		lda $030c	                    LDA DIVIDEND
.3966b4		85 02		sta $0302	                    STA FDC_CYLINDER
.3966b6		c2 20		rep #$20	                REP #$20        ; set A long
.3966b8		a5 14		lda $0314	                    LDA REMAINDER
.3966ba		85 0c		sta $030c	                    STA DIVIDEND
.3966bc		a5 16		lda $0316	                    LDA REMAINDER+2
.3966be		85 0e		sta $030e	                    STA DIVIDEND+2
.3966c0		a9 12 00	lda #$0012	                    LDA #18
.3966c3		85 10		sta $0310	                    STA DIVISOR
.3966c5		64 12		stz $0312	                    STZ DIVISOR+2
.3966c7		20 4c 66	jsr $39664c	                    JSR DIVIDE32
.3966ca		e2 20		sep #$20	                SEP #$20        ; set A short
.3966cc		a5 0c		lda $030c	                    LDA DIVIDEND
.3966ce		29 01		and #$01	                    AND #$01
.3966d0		85 01		sta $0301	                    STA FDC_HEAD
.3966d2		a5 14		lda $0314	                    LDA REMAINDER
.3966d4		1a		inc a		                    INC A
.3966d5		85 03		sta $0303	                    STA FDC_SECTOR
.3966d7		28		plp		                    PLP
.3966d8		2b		pld		                    PLD
.3966d9		ab		plb		                    PLB
.3966da		6b		rtl		                    RTL
.3966db						FDC_GETBLOCK
.3966db		8b		phb		                    PHB
.3966dc		0b		phd		                    PHD
.3966dd		08		php		                    PHP
.3966de		48		pha		                PHA             ; begin setdbr macro
.3966df		08		php		                PHP
.3966e0		e2 20		sep #$20	                SEP #$20        ; set A short
.3966e2		a9 00		lda #$00	                LDA #0
.3966e4		48		pha		                PHA
.3966e5		ab		plb		                PLB
.3966e6		28		plp		                PLP
.3966e7		68		pla		                PLA             ; end setdbr macro
.3966e8		48		pha		                PHA             ; begin setdp macro
.3966e9		08		php		                PHP
.3966ea		c2 20		rep #$20	                REP #$20        ; set A long
.3966ec		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.3966ef		5b		tcd		                TCD
.3966f0		28		plp		                PLP
.3966f1		68		pla		                PLA             ; end setdp macro
.3966f2		e2 20		sep #$20	                SEP #$20        ; set A short
.3966f4		a9 03		lda #$03	                    LDA #3                      ; We can retry 3 times
.3966f6		8d 34 05	sta $0534	                    STA FDC_CMD_RETRY
.3966f9		c2 30		rep #$30	                REP #$30        ; set A&X long
.3966fb		22 85 66 39	jsl $396685	                    JSL LBA2CHS                 ; Convert the LBA to CHS
.3966ff		e2 20		sep #$20	                SEP #$20        ; set A short
.396701		a5 03		lda $0303	                    LDA FDC_SECTOR              ; Just make sure the sector is ok
.396703		f0 29		beq $39672e	                    BEQ read_failure
.396705						try_read
.396705		c2 20		rep #$20	                REP #$20        ; set A long
.396707		22 22 65 39	jsl $396522	                    JSL FDC_Read_Sector         ; Read the sector
.39670b		90 14		bcc $396721	                    BCC retry
.39670d		e2 20		sep #$20	                SEP #$20        ; set A short
.39670f		a5 06		lda $0306	                    LDA FDC_ST0
.396711		29 d0		and #$d0	                    AND #%11010000              ; Check the error bits
.396713		d0 19		bne $39672e	                    BNE read_failure
.396715						ret_success
.396715		e2 20		sep #$20	                SEP #$20        ; set A short
.396717		a9 00		lda #$00	                    LDA #0
.396719		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
.39671c		28		plp		                    PLP
.39671d		2b		pld		                    PLD
.39671e		ab		plb		                    PLB
.39671f		38		sec		                    SEC
.396720		6b		rtl		                    RTL
.396721						retry
.396721		e2 20		sep #$20	                SEP #$20        ; set A short
.396723		ce 34 05	dec $0534	                    DEC FDC_CMD_RETRY           ; Decrement the retry counter
.396726		30 13		bmi $39673b	                    BMI pass_failure            ; If it's gone negative, we should quit with an error
.396728		22 1a 62 39	jsl $39621a	                    JSL FDC_INIT                ; Otherwise, reinitialize the FDC
.39672c		80 d7		bra $396705	                    BRA try_read                ; And try the read again
.39672e						read_failure
.39672e		e2 20		sep #$20	                SEP #$20        ; set A short
.396730		a9 82		lda #$82	                    LDA #BIOS_ERR_READ
.396732		80 04		bra $396738	                    BRA ret_failure
.396734						seek_failure
.396734		e2 20		sep #$20	                SEP #$20        ; set A short
.396736		a9 84		lda #$84	                    LDA #BIOS_ERR_TRACK
.396738		8d 20 03	sta $0320	ret_failure         STA @w BIOS_STATUS
.39673b		28		plp		pass_failure        PLP
.39673c		2b		pld		                    PLD
.39673d		ab		plb		                    PLB
.39673e		18		clc		                    CLC
.39673f		6b		rtl		                    RTL
.396740						FDC_PUTBLOCK
.396740		8b		phb		                    PHB
.396741		0b		phd		                    PHD
.396742		08		php		                    PHP
.396743		48		pha		                PHA             ; begin setdbr macro
.396744		08		php		                PHP
.396745		e2 20		sep #$20	                SEP #$20        ; set A short
.396747		a9 00		lda #$00	                LDA #0
.396749		48		pha		                PHA
.39674a		ab		plb		                PLB
.39674b		28		plp		                PLP
.39674c		68		pla		                PLA             ; end setdbr macro
.39674d		48		pha		                PHA             ; begin setdp macro
.39674e		08		php		                PHP
.39674f		c2 20		rep #$20	                REP #$20        ; set A long
.396751		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396754		5b		tcd		                TCD
.396755		28		plp		                PLP
.396756		68		pla		                PLA             ; end setdp macro
.396757		e2 20		sep #$20	                SEP #$20        ; set A short
.396759		a9 03		lda #$03	                    LDA #3                      ; Set the number of retries we're willing to do
.39675b		8d 34 05	sta $0534	                    STA @w FDC_CMD_RETRY
.39675e		c2 30		rep #$30	                REP #$30        ; set A&X long
.396760		22 85 66 39	jsl $396685	                    JSL LBA2CHS                 ; Convert the LBA to CHS
.396764		22 b7 65 39	jsl $3965b7	retry               JSL FDC_Write_Sector        ; Write the sector
.396768		b0 03		bcs $39676d	                    BCS chk_st0
.39676a		82 28 00	brl $396795	                    BRL attempt_retry
.39676d						chk_st0
.39676d		e2 20		sep #$20	                SEP #$20        ; set A short
.39676f		a5 06		lda $0306	                    LDA FDC_ST0
.396771		29 d0		and #$d0	                    AND #%11010000              ; Check the error bits
.396773		d0 0c		bne $396781	                    BNE write_failure
.396775						ret_success
.396775		e2 20		sep #$20	                SEP #$20        ; set A short
.396777		a9 00		lda #$00	                    LDA #0
.396779		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
.39677c		28		plp		                    PLP
.39677d		2b		pld		                    PLD
.39677e		ab		plb		                    PLB
.39677f		38		sec		                    SEC
.396780		6b		rtl		                    RTL
.396781						write_failure
.396781		e2 20		sep #$20	                SEP #$20        ; set A short
.396783		a5 07		lda $0307	                    LDA FDC_ST1                         ; Check ST1 for write protect
.396785		89 02		bit #$02	                    BIT #FDC_ST1_NW
.396787		f0 04		beq $39678d	                    BEQ generic_err
.396789		a9 86		lda #$86	                    LDA #BIOS_ERR_WRITEPROT             ; Yes: return a write-protect error
.39678b		80 17		bra $3967a4	                    BRA ret_failure
.39678d		89 10		bit #$10	generic_err         BIT #FDC_ST1_OR                     ; TODO: properly handle over/under run errors
.39678f		d0 e4		bne $396775	                    BNE ret_success
.396791		89 80		bit #$80	                    BIT #FDC_ST1_EN                     ; TODO: properly handle end-of-track
.396793		d0 e0		bne $396775	                    BNE ret_success
.396795						attempt_retry
.396795		e2 20		sep #$20	                SEP #$20        ; set A short
.396797		ce 34 05	dec $0534	                    DEC @w FDC_CMD_RETRY                ; Count down the retries
.39679a		d0 c8		bne $396764	                    BNE retry                           ; And retry unless we have none left
.39679c		a9 83		lda #$83	                    LDA #BIOS_ERR_WRITE                 ; Otherwise: return a generic write error
.39679e		80 04		bra $3967a4	                    BRA ret_failure
.3967a0						seek_failure
.3967a0		e2 20		sep #$20	                SEP #$20        ; set A short
.3967a2		a9 84		lda #$84	                    LDA #BIOS_ERR_TRACK
.3967a4						ret_failure
.3967a4		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
.3967a7		28		plp		pass_failure        PLP
.3967a8		2b		pld		                    PLD
.3967a9		ab		plb		                    PLB
.3967aa		18		clc		                    CLC
.3967ab		6b		rtl		                    RTL
.3967ac						FDC_MOUNT
.3967ac		8b		phb		                    PHB
.3967ad		0b		phd		                    PHD
.3967ae		08		php		                    PHP
.3967af		48		pha		                PHA             ; begin setdbr macro
.3967b0		08		php		                PHP
.3967b1		e2 20		sep #$20	                SEP #$20        ; set A short
.3967b3		a9 00		lda #$00	                LDA #0
.3967b5		48		pha		                PHA
.3967b6		ab		plb		                PLB
.3967b7		28		plp		                PLP
.3967b8		68		pla		                PLA             ; end setdbr macro
.3967b9		48		pha		                PHA             ; begin setdp macro
.3967ba		08		php		                PHP
.3967bb		c2 20		rep #$20	                REP #$20        ; set A long
.3967bd		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.3967c0		5b		tcd		                TCD
.3967c1		28		plp		                PLP
.3967c2		68		pla		                PLA             ; end setdp macro
.3967c3		22 1a 62 39	jsl $39621a	                    JSL FDC_INIT
.3967c7		e2 20		sep #$20	                SEP #$20        ; set A short
.3967c9		c2 10		rep #$10	                REP #$10        ; set X long
.3967cb		a9 00		lda #$00	                    LDA #0
.3967cd		a2 00 00	ldx #$0000	                    LDX #0
.3967d0		9f 00 a3 38	sta $38a300,x	zero_loop           STA DOS_SECTOR,X
.3967d4		e8		inx		                    INX
.3967d5		e0 00 02	cpx #$0200	                    CPX #512
.3967d8		d0 f6		bne $3967d0	                    BNE zero_loop
.3967da		a9 00		lda #$00	                    LDA #0                                  ; We only support drive 0
.3967dc		85 00		sta $0300	                    STA FDC_DRIVE
.3967de		22 96 62 39	jsl $396296	                    JSL FDC_Motor_On                        ; Turn the motor on
.3967e2		c2 30		rep #$30	                REP #$30        ; set A&X long
.3967e4		a9 00 00	lda #$0000	                    LDA #0                                  ; We want sector 0
.3967e7		85 22		sta $0322	                    STA BIOS_LBA
.3967e9		85 24		sta $0324	                    STA BIOS_LBA+2
.3967eb		a9 00 a3	lda #$a300	                    LDA #<>DOS_SECTOR                       ; And load it into DOS_SECTOR
.3967ee		85 26		sta $0326	                    STA BIOS_BUFF_PTR
.3967f0		a9 38 00	lda #$0038	                    LDA #`DOS_SECTOR
.3967f3		85 28		sta $0328	                    STA BIOS_BUFF_PTR+2
.3967f5		22 db 66 39	jsl $3966db	                    JSL FDC_GETBLOCK                        ; Attempt to read the data
.3967f9		b0 03		bcs $3967fe	                    BCS parse_boot                          ; If ok: start parsing the boot record
.3967fb		82 d3 00	brl $3968d1	                    BRL pass_failure                        ; Pass the error up the chain
.3967fe						parse_boot
.3967fe		e2 20		sep #$20	                SEP #$20        ; set A short
.396800		a9 00		lda #$00	                    LDA #PART_TYPE_FAT12                    ; Set the file system to FAT12
.396802		8f 01 a0 38	sta $38a001	                    STA @l FILE_SYSTEM
.396806		a9 00		lda #$00	                    LDA #0                                  ; There are no partitions on the disk
.396808		8f 02 a0 38	sta $38a002	                    STA @l PARTITION
.39680c		e2 20		sep #$20	                SEP #$20        ; set A short
.39680e		af 0d a3 38	lda $38a30d	                    LDA DOS_SECTOR+BPB_SECPERCLUS12_OFF     ; Get the # of sectors per cluster (usually 1)
.396812		8f 03 a0 38	sta $38a003	                    STA @l SECTORS_PER_CLUSTER
.396816		c2 20		rep #$20	                REP #$20        ; set A long
.396818		a9 00 00	lda #$0000	                    LDA #0                                  ; First sector of the "partition" is 0
.39681b		8f 04 a0 38	sta $38a004	                    STA @l FIRSTSECTOR
.39681f		8f 06 a0 38	sta $38a006	                    STA @l FIRSTSECTOR+2
.396823		af 16 a3 38	lda $38a316	                    LDA DOS_SECTOR+BPB_SECPERFAT12_OFF      ; Get the number of sectors per FAT
.396827		8f 10 a0 38	sta $38a010	                    STA @l SEC_PER_FAT
.39682b		a9 00 00	lda #$0000	                    LDA #0
.39682e		8f 12 a0 38	sta $38a012	                    STA @l SEC_PER_FAT+2
.396832		a9 01 00	lda #$0001	                    LDA #1                                  ; FAT#1 begins at sector 1
.396835		8f 14 a0 38	sta $38a014	                    STA @l FAT_BEGIN_LBA
.396839		18		clc		                    CLC
.39683a		6f 10 a0 38	adc $38a010	                    ADC @l SEC_PER_FAT
.39683e		8f 18 a0 38	sta $38a018	                    STA @l FAT2_BEGIN_LBA                   ; FAT#2 begins SEC_PER_FAT sectors later
.396842		a9 00 00	lda #$0000	                    LDA #0
.396845		8f 16 a0 38	sta $38a016	                    STA @l FAT_BEGIN_LBA+2
.396849		8f 1a a0 38	sta $38a01a	                    STA @L FAT2_BEGIN_LBA+2
.39684d		18		clc		                    CLC                                     ; Calculate the root directory's starting sector
.39684e		af 18 a0 38	lda $38a018	                    LDA @l FAT2_BEGIN_LBA
.396852		6f 10 a0 38	adc $38a010	                    ADC @l SEC_PER_FAT
.396856		8f 20 a0 38	sta $38a020	                    STA @l ROOT_DIR_FIRST_CLUSTER           ; ROOT_DIR_FIRST_CLUSTER will be a sector LBA for FAT12!
.39685a		a9 00 00	lda #$0000	                    LDA #0
.39685d		8f 22 a0 38	sta $38a022	                    STA @l ROOT_DIR_FIRST_CLUSTER+2
.396861		af 11 a3 38	lda $38a311	                    LDA DOS_SECTOR+BPB_ROOT_MAX_ENTRY12_OFF ; Get the maximum number of directory entries for the root dir
.396865		8f 24 a0 38	sta $38a024	                    STA @l ROOT_DIR_MAX_ENTRY
.396869		4a		lsr a		                    LSR A                                   ; 16 entries per sector
.39686a		4a		lsr a		                    LSR A
.39686b		4a		lsr a		                    LSR A
.39686c		4a		lsr a		                    LSR A                                   ; So now A is the number of sectors in the root directory
.39686d		18		clc		                    CLC
.39686e		6f 20 a0 38	adc $38a020	                    ADC @L ROOT_DIR_FIRST_CLUSTER           ; Add that to the first sector LBA for the root directory
.396872		8f 1c a0 38	sta $38a01c	                    STA @l CLUSTER_BEGIN_LBA                ; And that is the LBA for the first cluster
.396876		a9 00 00	lda #$0000	                    LDA #0
.396879		8f 1e a0 38	sta $38a01e	                    STA @l CLUSTER_BEGIN_LBA+2
.39687d		af 13 a3 38	lda $38a313	                    LDA DOS_SECTOR+BPB_TOTAL_SECTORS        ; Set the sector limit
.396881		8f 08 a0 38	sta $38a008	                    STA @l SECTORCOUNT
.396885		a9 00 00	lda #$0000	                    LDA #0
.396888		8f 0a a0 38	sta $38a00a	                    STA @l SECTORCOUNT+2
.39688c		af 0e a3 38	lda $38a30e	                    LDA DOS_SECTOR+BPB_RSRVCLUS_OFF         ; Get the number of reserved clusters
.396890		8f 0c a0 38	sta $38a00c	                    STA @l NUM_RSRV_SEC
.396894		a9 00 02	lda #$0200	                    LDA #DOS_SECTOR_SIZE                    ; Set the size of a FAT12 cluster
.396897		8f 0e a0 38	sta $38a00e	                    STA @l CLUSTER_SIZE
.39689b		e2 20		sep #$20	                SEP #$20        ; set A short
.39689d		af 26 a3 38	lda $38a326	                    LDA DOS_SECTOR+BPB_SIGNATUREB           ; Is signature B $29?
.3968a1		c9 29		cmp #$29	                    CMP #BPB_EXTENDED_RECORD
.3968a3		80 14		bra $3968b9	                    BRA no_volume_id                        ; No: there is no volume ID
.3968a5						is_extended
.3968a5		c2 20		rep #$20	                REP #$20        ; set A long
.3968a7		af 27 a3 38	lda $38a327	                    LDA DOS_SECTOR+BPB_VOLUMEID             ; Yes: set the volume ID
.3968ab		8f 26 a0 38	sta $38a026	                    STA @l VOLUME_ID
.3968af		af 29 a3 38	lda $38a329	                    LDA DOS_SECTOR+BPB_VOLUMEID+2
.3968b3		8f 28 a0 38	sta $38a028	                    STA @l VOLUME_ID+2
.3968b7		80 0d		bra $3968c6	                    BRA ret_success
.3968b9						no_volume_id
.3968b9		c2 20		rep #$20	                REP #$20        ; set A long
.3968bb		a9 00 00	lda #$0000	                    LDA #0                                  ; No: blank the Volume ID
.3968be		8f 26 a0 38	sta $38a026	                    STA @l VOLUME_ID
.3968c2		8f 28 a0 38	sta $38a028	                    STA @L VOLUME_ID+2
.3968c6						ret_success
.3968c6		e2 20		sep #$20	                SEP #$20        ; set A short
.3968c8		a9 00		lda #$00	                    LDA #0
.3968ca		85 20		sta $0320	                    STA BIOS_STATUS
.3968cc		28		plp		                    PLP
.3968cd		2b		pld		                    PLD
.3968ce		ab		plb		                    PLB
.3968cf		38		sec		                    SEC
.3968d0		6b		rtl		                    RTL
.3968d1		28		plp		pass_failure        PLP
.3968d2		2b		pld		                    PLD
.3968d3		ab		plb		                    PLB
.3968d4		18		clc		                    CLC
.3968d5		6b		rtl		                    RTL
.3968d6						FDC_CMDBLOCK
.3968d6		8b		phb		                    PHB
.3968d7		0b		phd		                    PHD
.3968d8		08		php		                    PHP
.3968d9		48		pha		                PHA             ; begin setdbr macro
.3968da		08		php		                PHP
.3968db		e2 20		sep #$20	                SEP #$20        ; set A short
.3968dd		a9 00		lda #$00	                LDA #0
.3968df		48		pha		                PHA
.3968e0		ab		plb		                PLB
.3968e1		28		plp		                PLP
.3968e2		68		pla		                PLA             ; end setdbr macro
.3968e3		48		pha		                PHA             ; begin setdp macro
.3968e4		08		php		                PHP
.3968e5		c2 20		rep #$20	                REP #$20        ; set A long
.3968e7		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.3968ea		5b		tcd		                TCD
.3968eb		28		plp		                PLP
.3968ec		68		pla		                PLA             ; end setdp macro
.3968ed		e2 30		sep #$30	                SEP #$30        ; set A&X short
.3968ef		e0 01		cpx #$01	                    CPX #FDC_DEVCMD_MOTOR_ON
.3968f1		f0 0f		beq $396902	                    BEQ motor_on
.3968f3		e0 02		cpx #$02	                    CPX #FDC_DEVCMD_MOTOR_OFF
.3968f5		f0 11		beq $396908	                    BEQ motor_off
.3968f7		e0 03		cpx #$03	                    CPX #FDC_DEVCMD_RECAL
.3968f9		f0 13		beq $39690e	                    BEQ recalibrate
.3968fb		64 20		stz $0320	ret_success         STZ BIOS_STATUS
.3968fd		28		plp		                    PLP
.3968fe		2b		pld		                    PLD
.3968ff		ab		plb		                    PLB
.396900		38		sec		                    SEC
.396901		6b		rtl		                    RTL
.396902		22 96 62 39	jsl $396296	motor_on            JSL FDC_Motor_On
.396906		80 f3		bra $3968fb	                    BRA ret_success
.396908		22 ca 62 39	jsl $3962ca	motor_off           JSL FDC_Motor_Off
.39690c		80 ed		bra $3968fb	                    BRA ret_success
.39690e		22 f5 62 39	jsl $3962f5	recalibrate         JSL FDC_Recalibrate_Command
.396912		b0 e7		bcs $3968fb	                    BCS ret_success
.396914		28		plp		pass_failure        PLP
.396915		2b		pld		                    PLD
.396916		ab		plb		                    PLB
.396917		18		clc		                    CLC
.396918		6b		rtl		                    RTL
.396919						FDC_CHK_MEDIA
.396919		0b		phd		                    PHD
.39691a		08		php		                    PHP
.39691b		48		pha		                PHA             ; begin setdp macro
.39691c		08		php		                PHP
.39691d		c2 20		rep #$20	                REP #$20        ; set A long
.39691f		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
.396922		5b		tcd		                TCD
.396923		28		plp		                PLP
.396924		68		pla		                PLA             ; end setdp macro
.396925		22 96 62 39	jsl $396296	                    JSL FDC_Motor_On                ; Turn on the motor
.396929		e2 20		sep #$20	                SEP #$20        ; set A short
.39692b		af f7 13 af	lda $af13f7	                    LDA @l SIO_FDC_DIR              ; Check if the DSKCHG bit is set
.39692f		89 80		bit #$80	                    BIT #FDC_DIR_DSKCHG
.396931		f0 42		beq $396975	                    BEQ ret_true                    ; If not: assume the disk is present
.396933		a9 00		lda #$00	                    LDA #0
.396935		85 00		sta $0300	                    STA FDC_DRIVE
.396937		a9 00		lda #$00	                    LDA #0
.396939		85 01		sta $0301	                    STA FDC_HEAD
.39693b		a9 50		lda #$50	                    LDA #80
.39693d		85 02		sta $0302	                    STA FDC_CYLINDER
.39693f		22 d5 64 39	jsl $3964d5	                    JSL FDC_Seek_Track              ; Attempt to seek to track 80
.396943		90 34		bcc $396979	                    BCC ret_false                   ; If fail: return false
.396945		c2 10		rep #$10	                REP #$10        ; set X long
.396947		a2 1e 8b	ldx #$8b1e	                    LDX #<>FDC_MOTOR_TIME       ; Wait a suitable time for the motor to spin up
.39694a		a0 41 00	ldy #$0041	                    LDY #`FDC_MOTOR_TIME
.39694d		22 26 16 39	jsl $391626	                    JSL IDELAY
.396951		22 2a 63 39	jsl $39632a	                    JSL FDC_Sense_Int_Status
.396955		a5 06		lda $0306	                    LDA FDC_ST0
.396957		29 d0		and #$d0	                    AND #%11010000
.396959		d0 1e		bne $396979	                    BNE ret_false
.39695b		22 f5 62 39	jsl $3962f5	                    JSL FDC_Recalibrate_Command     ; Attempt to recalibrate
.39695f		90 18		bcc $396979	                    BCC ret_false                   ; If fail: return false
.396961		a2 1e 8b	ldx #$8b1e	                    LDX #<>FDC_MOTOR_TIME       ; Wait a suitable time for the motor to spin up
.396964		a0 41 00	ldy #$0041	                    LDY #`FDC_MOTOR_TIME
.396967		22 26 16 39	jsl $391626	                    JSL IDELAY
.39696b		22 2a 63 39	jsl $39632a	                    JSL FDC_Sense_Int_Status
.39696f		a5 06		lda $0306	                    LDA FDC_ST0
.396971		29 d0		and #$d0	                    AND #%11010000
.396973		d0 04		bne $396979	                    BNE ret_false
.396975						ret_true
.396975		28		plp		                    PLP
.396976		2b		pld		                    PLD
.396977		38		sec		                    SEC
.396978		6b		rtl		                    RTL
.396979						ret_false
.396979		28		plp		                    PLP
.39697a		2b		pld		                    PLD
.39697b		18		clc		                    CLC
.39697c		6b		rtl		                    RTL
.39697d						FDC_WRITEVBR
.39697d		8b		phb		                    PHB
.39697e		0b		phd		                    PHD
.39697f		08		php		                    PHP
.396980		48		pha		                PHA             ; begin setdbr macro
.396981		08		php		                PHP
.396982		e2 20		sep #$20	                SEP #$20        ; set A short
.396984		a9 00		lda #$00	                LDA #0
.396986		48		pha		                PHA
.396987		ab		plb		                PLB
.396988		28		plp		                PLP
.396989		68		pla		                PLA             ; end setdbr macro
.39698a		48		pha		                PHA             ; begin setdp macro
.39698b		08		php		                PHP
.39698c		c2 20		rep #$20	                REP #$20        ; set A long
.39698e		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.396991		5b		tcd		                TCD
.396992		28		plp		                PLP
.396993		68		pla		                PLA             ; end setdp macro
.396994		22 ac 67 39	jsl $3967ac	                    JSL FDC_MOUNT               ; Mount the floppy disk
.396998		c2 30		rep #$30	                REP #$30        ; set A&X long
.39699a		a9 00 00	lda #$0000	                    LDA #0                      ; Clear the sector buffer
.39699d		a2 00 00	ldx #$0000	                    LDX #0
.3969a0		9f 00 a3 38	sta $38a300,x	clr_loop            STA DOS_SECTOR,X
.3969a4		e8		inx		                    INX
.3969a5		e8		inx		                    INX
.3969a6		e0 00 02	cpx #$0200	                    CPX #512
.3969a9		d0 f5		bne $3969a0	                    BNE clr_loop
.3969ab		e2 20		sep #$20	                SEP #$20        ; set A short
.3969ad		a2 00 00	ldx #$0000	                    LDX #0                      ; Copy the prototype VBR to the sector buffer
.3969b0		bf 65 6a 39	lda $396a65,x	copy_loop           LDA FDC_VBR_BEGIN,X
.3969b4		9f 00 a3 38	sta $38a300,x	                    STA DOS_SECTOR,X
.3969b8		e8		inx		                    INX
.3969b9		e0 c9 00	cpx #$00c9	                    CPX #<>(FDC_VBR_END - FDC_VBR_BEGIN + 1)
.3969bc		d0 f2		bne $3969b0	                    BNE copy_loop
.3969be		a0 00 00	ldy #$0000	                    LDY #0                      ; Copy the boot binary path to the VBR
.3969c1		a2 40 00	ldx #$0040	                    LDX #FDC_VBR_PATH
.3969c4		b7 3c		lda [$035c],y	path_copy_loop      LDA [DOS_RUN_PTR],Y
.3969c6		9f 00 a3 38	sta $38a300,x	                    STA DOS_SECTOR,X
.3969ca		f0 07		beq $3969d3	                    BEQ path_copy_done
.3969cc		e8		inx		                    INX
.3969cd		c8		iny		                    INY
.3969ce		c0 80 00	cpy #$0080	                    CPY #128
.3969d1		d0 f1		bne $3969c4	                    BNE path_copy_loop
.3969d3						path_copy_done
.3969d3		c2 20		rep #$20	                REP #$20        ; set A long
.3969d5		a9 55 aa	lda #$aa55	                    LDA #$AA55                  ; Set the VBR signature bytes at the end
.3969d8		8f fe a4 38	sta $38a4fe	                    STA DOS_SECTOR+BPB_SIGNATURE
.3969dc		c2 20		rep #$20	                REP #$20        ; set A long
.3969de		a9 00 a3	lda #$a300	                    LDA #<>DOS_SECTOR           ; Point to the BIOS buffer
.3969e1		85 06		sta $0326	                    STA BIOS_BUFF_PTR
.3969e3		a9 38 00	lda #$0038	                    LDA #`DOS_SECTOR
.3969e6		85 08		sta $0328	                    STA BIOS_BUFF_PTR+2
.3969e8		a9 00 00	lda #$0000	                    LDA #0                      ; Set the sector to #0 (boot record)
.3969eb		85 02		sta $0322	                    STA BIOS_LBA
.3969ed		85 04		sta $0324	                    STA BIOS_LBA+2
.3969ef		e2 20		sep #$20	                SEP #$20        ; set A short
.3969f1		a9 00		lda #$00	                    LDA #BIOS_DEV_FDC
.3969f3		85 01		sta $0321	                    STA BIOS_DEV
.3969f5		22 24 10 00	jsl $001024	                    JSL PUTBLOCK                ; Attempt to write the boot record
.3969f9		b0 09		bcs $396a04	                    BCS ret_success
.3969fb		22 ca 62 39	jsl $3962ca	                    JSL FDC_Motor_Off
.3969ff		28		plp		                    PLP                         ; Return the failure
.396a00		2b		pld		                    PLD
.396a01		ab		plb		                    PLB
.396a02		18		clc		                    CLC
.396a03		6b		rtl		                    RTL
.396a04		22 ca 62 39	jsl $3962ca	ret_success         JSL FDC_Motor_Off
.396a08		e2 20		sep #$20	                SEP #$20        ; set A short
.396a0a		a9 00		lda #$00	                    LDA #0
.396a0c		85 00		sta $0320	                    STA BIOS_STATUS
.396a0e		28		plp		                    PLP
.396a0f		2b		pld		                    PLD
.396a10		ab		plb		                    PLB
.396a11		38		sec		                    SEC
.396a12		6b		rtl		                    RTL
.396a13						FDC_TIME_HANDLE
.396a13		08		php		                    PHP
.396a14		e2 20		sep #$20	                SEP #$20        ; set A short
.396a16		af 4e a0 38	lda $38a04e	                    LDA @l FDC_MOTOR_TIMER          ; Check the FDC motor count-down timer
.396a1a		d0 06		bne $396a22	                    BNE dec_motor                   ; If not zero: decrement the timer
.396a1c		af 4f a0 38	lda $38a04f	                    LDA @l FDC_MOTOR_TIMER+1        ; Check the high byte
.396a20		f0 28		beq $396a4a	                    BEQ sof_timeout                 ; If zero: move on to the next timer
.396a22		af 4e a0 38	lda $38a04e	dec_motor           LDA @l FDC_MOTOR_TIMER          ; Decrement the low byte
.396a26		3a		dec a		                    DEC A
.396a27		8f 4e a0 38	sta $38a04e	                    STA @l FDC_MOTOR_TIMER
.396a2b		c9 ff		cmp #$ff	                    CMP #$FF                        ; Did it roll over?
.396a2d		d0 0b		bne $396a3a	                    BNE chk_motor_end               ; No: check to see if we're a the end
.396a2f		af 4f a0 38	lda $38a04f	                    LDA @l FDC_MOTOR_TIMER+1        ; Decrement the high byte
.396a33		3a		dec a		                    DEC A
.396a34		8f 4f a0 38	sta $38a04f	                    STA @l FDC_MOTOR_TIMER+1
.396a38		80 10		bra $396a4a	                    BRA sof_timeout                 ; And move on to the next timer
.396a3a		af 4e a0 38	lda $38a04e	chk_motor_end       LDA @l FDC_MOTOR_TIMER          ; Check timer
.396a3e		d0 0a		bne $396a4a	                    BNE sof_timeout                 ; if it's <>0, move on to the next timer
.396a40		af 4f a0 38	lda $38a04f	                    LDA @l FDC_MOTOR_TIMER+1
.396a44		d0 04		bne $396a4a	                    BNE sof_timeout
.396a46		22 ca 62 39	jsl $3962ca	                    JSL FDC_Motor_Off               ; Otherwise, turn off the motor
.396a4a						sof_timeout
.396a4a		e2 20		sep #$20	                SEP #$20        ; set A short
.396a4c		af 2d 03 00	lda $00032d	                    LDA @l BIOS_TIMER               ; Check the BIOS_TIMER
.396a50		f0 11		beq $396a63	                    BEQ sof_int_done                ; If it's 0, we don't do anything
.396a52		3a		dec a		                    DEC A                           ; Count down one tick
.396a53		8f 2d 03 00	sta $00032d	                    STA @l BIOS_TIMER
.396a57		d0 0a		bne $396a63	                    BNE sof_int_done                ; If not 0, we're done
.396a59		af 2c 03 00	lda $00032c	                    LDA @l BIOS_FLAGS               ; Otherwise: flag a time out event
.396a5d		09 80		ora #$80	                    ORA #BIOS_TIMEOUT
.396a5f		8f 2c 03 00	sta $00032c	                    STA @l BIOS_FLAGS
.396a63		28		plp		sof_int_done        PLP
.396a64		6b		rtl		                    RTL
=62						FDC_BOOT_START = 62                         ; Entry point to the boot code
=64						FDC_VBR_PATH = 64                           ; Offset to the path in the VBR
.396a65						FDC_VBR_BEGIN
>396a65		eb 00 90			start               .byte $EB, $00, $90     ; Entry point
>396a68		43 32 35 36 44 4f 53 20		magic               .text "C256DOS "        ; OEM name / magic text for booting
>396a70		00 02				bytes_per_sec       .word 512               ; How many bytes per sector
>396a72		01				sec_per_cluster     .byte 1                 ; How many sectors per cluster
>396a73		01 00				rsrv_sectors        .word 1                 ; Number of reserved sectors
>396a75		02				num_fat             .byte 2                 ; Number of FATs
>396a76		e0 00				max_dir_entry       .word (32-18)*16        ; Total number of root dir entries
>396a78		40 0b				total_sectors       .word 2880              ; Total sectors
>396a7a		f0				media_descriptor    .byte $F0               ; 3.5" 1.44 MB floppy 80 tracks, 18 tracks per sector
>396a7b		09 00				sec_per_fat         .word 9                 ; Sectors per FAT
>396a7d		12 00				sec_per_track       .word 18                ; Sectors per track
>396a7f		02 00				num_head            .word 2                 ; Number of heads
>396a81		00 00 00 00			ignore2             .dword 0
>396a85		00 00 00 00			fat32_sector        .dword 0                ; # of sectors in FAT32
>396a89		00 00				ignore3             .word 0
>396a8b		29				boot_signature      .byte $29
>396a8c		78 56 34 12			volume_id           .dword $12345678        ; Replaced by code
>396a90		55 4e 54 49 54 4c 45 44		volume_name         .text "UNTITLED   "     ; Replace by code
>396a98		20 20 20
>396a9b		46 41 54 31 32 20 20 20		fs_type             .text "FAT12   "
.396aa3		80 40		bra $396ae5	                    BRA vbr_start
>396aa5						file_path           .fill 64                ; Reserve 64 bytes for a path and any options
.396ae5						vbr_start
.396ae5		c2 20		rep #$20	                REP #$20        ; set A long
.396ae7		a9 40 a3	lda #$a340	                    LDA #<>(DOS_SECTOR + (file_path - FDC_VBR_BEGIN))
.396aea		8f 60 03 00	sta $000360	                    STA @l DOS_RUN_PARAM
.396aee		a9 38 00	lda #$0038	                    LDA #`(DOS_SECTOR + (file_path - FDC_VBR_BEGIN))
.396af1		8f 62 03 00	sta $000362	                    STA @l DOS_RUN_PARAM+2
.396af5		22 92 59 39	jsl $395992	                    JSL IF_RUN              ; And try to execute the binary file
.396af9		b0 0c		bcs $396b07	                    BCS lock                ; If it returned success... lock up... I guess?
.396afb						error
.396afb		e2 20		sep #$20	                SEP #$20        ; set A short
.396afd		4b		phk		                    PHK                     ; Otherwise, print an error message
.396afe		ab		plb		                    PLB
.396aff		62 08 00	per $396b0a	                    PER message
.396b02		fa		plx		                    PLX
.396b03		22 1c 10 00	jsl $00101c	                    JSL PUTS
.396b07		ea		nop		lock                NOP                     ; And lock up
.396b08		80 fd		bra $396b07	                    BRA lock
>396b0a		43 6f 75 6c 64 20 6e 6f		message             .null "Could not find a bootable binary.",13
>396b12		74 20 66 69 6e 64 20 61 20 62 6f 6f 74 61 62 6c
>396b22		65 20 62 69 6e 61 72 79 2e 0d 00
.396b2d						FDC_VBR_END

;******  Return to file: src\kernel.asm


;******  Processing file: src\ide_library.asm

.0000						IDE_ID
>0000		00 00				General_Config        .word $0000
>0002		00 00				Obsolete0             .word $0000
>0004		00 00				Specific_Config       .word $0000
>0006		00 00				Obsolete1             .word $0000
>0008		00 00				Retired0              .word $0000
>000a		00 00				Retired1              .word $0000
>000c		00 00				Obsolete2             .word $0000
>000e		00 00				Reserved_CFlash0      .word $0000
>0010		00 00				Reserved_CFlash1      .word $0000
>0012		00 00				Retired2              .word $0000
>0014		00 00 00 00 00 00 00 00		Serial_Number_String  .byte $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>001c		00 00 00 00 00 00 00 00 00 00 00 00
>0028		00 00 00 00			Retired3              .word $0000, $0000
>002c		00 00				Obsolete3             .word $0000
>002e		00 00 00 00 00 00 00 00		Firmware_Rev_String   .byte $00, $00, $00, $00, $00, $00, $00, $00
>0036		00 00 00 00 00 00 00 00		Model_Number_String   .byte $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>003e		00 00 00 00 00 00 00 00
>0046		00 00 00 00 00 00 00 00		                      .byte $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
>004e		00 00 00 00 00 00 00 00
>0056		00 00 00 00 00 00 00 00		                      .byte $00, $00, $00, $00, $00, $00, $00, $00
>005e		00 00				Max_Number_Logic_Sec  .word $0000
>0060		00 00				Trusted_Comp_Feature  .word $0000
>0062		00 00 00 00			Capabilities          .word $0000, $0000
>0066		00 00 00 00			Obsolete4             .word $0000, $0000
>006a		00 00				Free_Fall_Control     .word $0000
>006c		00 00 00 00 00 00 00 00		Obsolete5             .word $0000, $0000, $0000, $0000, $0000
>0074		00 00
>0076		00 00				Reserved0             .word $0000
>0078		00 00 00 00			Total_Addy_Logic_Sec  .word $0000, $0000
>007c		00 00				Obsolete6             .word $0000
>007e		00 00 00 00			Reserved1             .word $0000, $0000
>0082		00 00				Min_Multiword_DMA_Trf .word $0000
>0084		00 00				Manu_Recommended_Mult .word $0000
>0086		00 00				Min_PIO_Trf           .word $0000      ; Word 67
>0088		00 00				Min_PIO_Trf_with_IORD .word $0000      ; Word 68
>008a		00 00 00 00			Reserved2             .word $0000, $0000
>008e		00 00 00 00 00 00 00 00		Reserved3             .word $0000, $0000, $0000, $0000
>0096		00 00				Queue_Dept            .word $0000
>0098		00 00				SATA_Capabilities     .word $0000
>009a		00 00				Reserved_SATA         .word $0000
>009c		00 00				Sup_Feat_SATA         .word $0000
>009e		00 00				Sup_Feat_SATA_Enabled .word $0000    ; Word 79
>00a0		00 00				Major_Version_Number  .word $0000    ; Word 80
>00a2		00 00				Minor_Version_Number  .word $0000    ; Word 81
>00a4		00 00 00 00 00 00 00 00		Cmd_And_Features_Sup  .word $0000, $0000, $0000, $0000, $0000, $0000
>00ac		00 00 00 00
>00b0		00 00				UDMA_Modes            .word $0000
>00b2		00 00 00 00			Reserved4             .word $0000, $0000 ; Word 89
>00b6		00 00				Current_APM_Level     .word $0000
>00b8		00 00				Master_Password_Ident .word $0000
>00ba		00 00				Hardware_Reset_Result .word $0000
>00bc		00 00				Current_AAM_Value     .word $0000  ; Word 94
>00be		00 00				Stream_Min_Req_Size   .word $0000  ; Word 95
>00c0		00 00				Stream_Trf_Time_DMA   .word $0000  ; Word 96
>00c2		00 00				Stream_Access_Lat     .word $0000
>00c4		00 00 00 00			Streaming_Perf_Gran   .word $0000, $0000
>00c8		00 00 00 00 00 00 00 00		Tot_Num_Add_Logic_Sec .word $0000, $0000, $0000, $0000
>00d0		00 00				Streaming_Trf_Time    .word $0000 ; Word 104
>00d2		00 00				Reserved5             .word $0000 ; Word 105
.396b2d						IDE_TEST
.396b2d		08		php		                PHP
.396b2e		c2 20		rep #$20	                REP #$20        ; set A long
.396b30		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR
.396b33		8f 26 03 00	sta $000326	                STA @l BIOS_BUFF_PTR
.396b37		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
.396b3a		8f 28 03 00	sta $000328	                STA @l BIOS_BUFF_PTR+2
.396b3e		22 5b 6c 39	jsl $396c5b	                JSL IDE_IDENTIFY
.396b42		b0 03		bcs $396b47	                BCS id_ok
.396b44		82 ab 00	brl $396bf2	                BRL done
.396b47						id_ok
.396b47		c2 10		rep #$10	                REP #$10        ; set X long
.396b49		e2 20		sep #$20	                SEP #$20        ; set A short
.396b4b		a0 28 00	ldy #$0028	                LDY #40
.396b4e		a2 36 00	ldx #$0036	                LDX #27*2
.396b51		bf 01 a3 38	lda $38a301,x	pr_model        LDA DOS_SECTOR+1,X
.396b55		22 18 10 00	jsl $001018	                JSL PUTC
.396b59		bf 00 a3 38	lda $38a300,x	                LDA DOS_SECTOR,X
.396b5d		22 18 10 00	jsl $001018	                JSL PUTC
.396b61		e8		inx		                INX
.396b62		e8		inx		                INX
.396b63		88		dey		                DEY
.396b64		88		dey		                DEY
.396b65		d0 ea		bne $396b51	                BNE pr_model
.396b67		c2 10		rep #$10	                REP #$10        ; set X long
.396b69		e2 20		sep #$20	                SEP #$20        ; set A short
.396b6b		a0 14 00	ldy #$0014	                LDY #20
.396b6e		a2 14 00	ldx #$0014	                LDX #10*2
.396b71		bf 01 a3 38	lda $38a301,x	pr_serial       LDA DOS_SECTOR+1,X
.396b75		22 18 10 00	jsl $001018	                JSL PUTC
.396b79		bf 00 a3 38	lda $38a300,x	                LDA DOS_SECTOR,X
.396b7d		22 18 10 00	jsl $001018	                JSL PUTC
.396b81		e8		inx		                INX
.396b82		e8		inx		                INX
.396b83		88		dey		                DEY
.396b84		88		dey		                DEY
.396b85		d0 ea		bne $396b71	                BNE pr_serial
.396b87		22 6c 10 00	jsl $00106c	                JSL PRINTCR
.396b8b		c2 30		rep #$30	                REP #$30        ; set A&X long
.396b8d		a9 01 00	lda #$0001	                LDA #1                 ; Set LBA = 1
.396b90		8f 22 03 00	sta $000322	                STA @l BIOS_LBA
.396b94		a9 00 00	lda #$0000	                LDA #0
.396b97		8f 24 03 00	sta $000324	                STA @l BIOS_LBA+2
.396b9b		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR
.396b9e		8f 26 03 00	sta $000326	                STA @l BIOS_BUFF_PTR
.396ba2		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
.396ba5		8f 28 03 00	sta $000328	                STA @l BIOS_BUFF_PTR+2
.396ba9		a2 00 00	ldx #$0000	                LDX #0                  ; Initialize the block to some recognizable data
.396bac		a9 a5 5a	lda #$5aa5	                LDA #$5AA5
.396baf		9f 00 a3 38	sta $38a300,x	init_loop       STA DOS_SECTOR,X
.396bb3		e8		inx		                INX
.396bb4		e8		inx		                INX
.396bb5		e0 00 02	cpx #$0200	                CPX #512
.396bb8		d0 f5		bne $396baf	                BNE init_loop
.396bba		22 7a 6d 39	jsl $396d7a	                JSL IDE_PUTBLOCK        ; Attempt to write the block
.396bbe		b0 06		bcs $396bc6	                BCS read_sect1
.396bc0		22 6c 10 00	jsl $00106c	                JSL PRINTCR
.396bc4		80 2c		bra $396bf2	                BRA done
.396bc6		a9 01 00	lda #$0001	read_sect1      LDA #1                 ; Set LBA = 1
.396bc9		8f 22 03 00	sta $000322	                STA @l BIOS_LBA
.396bcd		a9 00 00	lda #$0000	                LDA #0
.396bd0		8f 24 03 00	sta $000324	                STA @l BIOS_LBA+2
.396bd4		a9 00 a5	lda #$a500	                LDA #<>DOS_FAT_SECTORS
.396bd7		8f 26 03 00	sta $000326	                STA @l BIOS_BUFF_PTR
.396bdb		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
.396bde		8f 28 03 00	sta $000328	                STA @l BIOS_BUFF_PTR+2
.396be2		22 e9 6c 39	jsl $396ce9	                JSL IDE_GETBLOCK        ; Attempt to read the block
.396be6		b0 06		bcs $396bee	                BCS all_ok
.396be8		22 6c 10 00	jsl $00106c	                JSL PRINTCR
.396bec		80 04		bra $396bf2	                BRA done
.396bee						all_ok
.396bee		22 6c 10 00	jsl $00106c	                JSL PRINTCR
.396bf2		28		plp		done            PLP
.396bf3		6b		rtl		                RTL
.396bf4						IDE_INIT
.396bf4		e2 20		sep #$20	                SEP #$20        ; set A short
.396bf6		20 17 6c	jsr $396c17	              JSR IDE_DRIVE_BSY ; Check to see if drive is busy
.396bf9		a9 00		lda #$00	              LDA #$00
.396bfb		8f 35 e8 af	sta $afe835	              STA IDE_CLDR_HI
.396bff		8f 34 e8 af	sta $afe834	              STA IDE_CLDR_LO
.396c03		8f 32 e8 af	sta $afe832	              STA IDE_SECT_CNT
.396c07		a9 01		lda #$01	              LDA #$01
.396c09		8f 33 e8 af	sta $afe833	              STA IDE_SECT_SRT
.396c0d		a9 a0		lda #$a0	              LDA #$A0 ; HEAD 0 - Select Master Drive
.396c0f		8f 36 e8 af	sta $afe836	              STA IDE_HEAD
.396c13		20 35 6c	jsr $396c35	              JSR IDE_DRV_READY_NOTBUSY
.396c16		6b		rtl		              RTL
.396c17						IDE_DRIVE_BSY
.396c17		08		php		                PHP
.396c18		e2 20		sep #$20	                SEP #$20        ; set A short
.396c1a		af 37 e8 af	lda $afe837	loop            LDA @l IDE_CMD_STAT
.396c1e		29 80		and #$80	                AND #IDE_STAT_BSY         ; Check for RDY Bit, this needs to be 1'b1
.396c20		c9 80		cmp #$80	                CMP #IDE_STAT_BSY         ; If not go read again
.396c22		f0 f6		beq $396c1a	                BEQ loop
.396c24		28		plp		                PLP
.396c25		60		rts		                RTS
.396c26						IDE_DRIVE_READY
.396c26		08		php		                PHP
.396c27		e2 20		sep #$20	                SEP #$20        ; set A short
.396c29		af 37 e8 af	lda $afe837	loop            LDA @l IDE_CMD_STAT
.396c2d		29 40		and #$40	                AND #IDE_STAT_DRDY          ; Check to see if the Busy Signal is Cleared
.396c2f		c9 40		cmp #$40	                CMP #IDE_STAT_DRDY          ; if it is still one, then go back to read again.
.396c31		d0 f6		bne $396c29	                BNE loop
.396c33		28		plp		                PLP
.396c34		60		rts		                RTS
.396c35						IDE_DRV_READY_NOTBUSY
.396c35		08		php		                PHP
.396c36		e2 20		sep #$20	                SEP #$20        ; set A short
.396c38		af 37 e8 af	lda $afe837	loop            LDA @l IDE_CMD_STAT                 ; Check the status
.396c3c		29 c0		and #$c0	                AND #IDE_STAT_BSY | IDE_STAT_DRDY
.396c3e		c9 40		cmp #$40	                CMP #IDE_STAT_DRDY                  ; Is it READY but not BUSY?
.396c40		d0 f6		bne $396c38	                BNE loop                            ; No: keep waiting
.396c42		28		plp		ret_success     PLP                                 ; Return success
.396c43		38		sec		                SEC
.396c44		60		rts		                RTS
.396c45		8f 07 03 00	sta $000307	ret_failure     STA @l FDC_ST1                      ; Save the status code to FDC_ST1
.396c49		28		plp		                PLP                                 ; Return failure
.396c4a		18		clc		                CLC
.396c4b		60		rts		                RTS
.396c4c						IDE_NOT_DRQ
.396c4c		08		php		                PHP
.396c4d		e2 20		sep #$20	                SEP #$20        ; set A short
.396c4f		af 37 e8 af	lda $afe837	loop            LDA @l IDE_CMD_STAT     ; Get the status
.396c53		29 08		and #$08	                AND #IDE_STAT_DRQ
.396c55		c9 08		cmp #$08	                CMP #IDE_STAT_DRQ       ; Is the DRQ bit set?
.396c57		d0 f6		bne $396c4f	                BNE loop                ; No: keep waiting
.396c59		28		plp		                PLP
.396c5a		60		rts		                RTS
.396c5b						IDE_IDENTIFY
.396c5b		5a		phy		                PHY
.396c5c		8b		phb		                PHB
.396c5d		0b		phd		                PHD
.396c5e		08		php		                PHP
.396c5f		48		pha		                PHA             ; begin setdbr macro
.396c60		08		php		                PHP
.396c61		e2 20		sep #$20	                SEP #$20        ; set A short
.396c63		a9 00		lda #$00	                LDA #0
.396c65		48		pha		                PHA
.396c66		ab		plb		                PLB
.396c67		28		plp		                PLP
.396c68		68		pla		                PLA             ; end setdbr macro
.396c69		48		pha		                PHA             ; begin setdp macro
.396c6a		08		php		                PHP
.396c6b		c2 20		rep #$20	                REP #$20        ; set A long
.396c6d		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.396c70		5b		tcd		                TCD
.396c71		28		plp		                PLP
.396c72		68		pla		                PLA             ; end setdp macro
.396c73		e2 20		sep #$20	                SEP #$20        ; set A short
.396c75		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; Wait until the IDE is clear to accept commands
.396c78		a5 05		lda $0325	                LDA BIOS_LBA+3                  ; Get the high bits of the LBA
.396c7a		29 07		and #$07	                AND #$07
.396c7c		09 a0		ora #$a0	                ORA #%10100000                  ; Select DEV=0 and LBA mode = 1
.396c7e		8f 36 e8 af	sta $afe836	                STA @l IDE_HEAD                 ; Ensure master is selected
.396c82		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; And wait for it to take effect
.396c85		e2 20		sep #$20	                SEP #$20        ; set A short
.396c87		a9 00		lda #$00	                LDA #0                          ; Clear sector count and LBA
.396c89		8f 32 e8 af	sta $afe832	                STA @l IDE_SECT_CNT
.396c8d		8f 33 e8 af	sta $afe833	                STA @l IDE_SECT_SRT
.396c91		8f 34 e8 af	sta $afe834	                STA @l IDE_CLDR_LO
.396c95		8f 35 e8 af	sta $afe835	                STA @l IDE_CLDR_HI
.396c99		a9 ec		lda #$ec	                LDA #IDE_CMD_IDENTIFY           ; The IDENTIFY command
.396c9b		8f 37 e8 af	sta $afe837	                STA @l IDE_CMD_STAT             ; Check the status
.396c9f		f0 29		beq $396cca	                BEQ no_media                    ; If 0: there is no drive
.396ca1		20 17 6c	jsr $396c17	                JSR IDE_DRIVE_BSY               ; Othewise: wait for drive to not be busy
.396ca4		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; Wait for the device to be ready
.396ca7		90 2d		bcc $396cd6	                BCC ret_failure                 ; If an error occurred, return it
.396ca9		c2 30		rep #$30	                REP #$30        ; set A&X long
.396cab		a0 00 00	ldy #$0000	                LDY #0
.396cae		af 38 e8 af	lda $afe838	read_loop       LDA @l IDE_DATA_LO              ; Get the word of data from the device
.396cb2		97 06		sta [$0326],y	                STA [BIOS_BUFF_PTR],Y           ; Save it to the buffer
.396cb4		c8		iny		                INY                             ; Move to the next position
.396cb5		c8		iny		                INY
.396cb6		c0 00 02	cpy #$0200	                CPY #512
.396cb9		d0 f3		bne $396cae	                BNE read_loop
.396cbb						ret_success
.396cbb		e2 20		sep #$20	                SEP #$20        ; set A short
.396cbd		a9 00		lda #$00	                LDA #0
.396cbf		85 00		sta $0320	                STA BIOS_STATUS
.396cc1		8d 06 03	sta $0306	                STA @w FDC_ST0
.396cc4		28		plp		                PLP                             ; Return success
.396cc5		2b		pld		                PLD
.396cc6		ab		plb		                PLB
.396cc7		7a		ply		                PLY
.396cc8		38		sec		                SEC
.396cc9		6b		rtl		                RTL
.396cca						no_media
.396cca		e2 20		sep #$20	                SEP #$20        ; set A short
.396ccc		a9 87		lda #$87	                LDA #BIOS_ERR_NOMEDIA
.396cce		80 0a		bra $396cda	                BRA pass_failure
.396cd0						not_ata
.396cd0		e2 20		sep #$20	                SEP #$20        ; set A short
.396cd2		a9 8a		lda #$8a	                LDA #BIOS_ERR_NOTATA
.396cd4		80 04		bra $396cda	                BRA pass_failure
.396cd6						ret_failure
.396cd6		e2 20		sep #$20	                SEP #$20        ; set A short
.396cd8		a9 82		lda #$82	                LDA #BIOS_ERR_READ
.396cda		85 00		sta $0320	pass_failure    STA BIOS_STATUS
.396cdc		af 31 e8 af	lda $afe831	                LDA @l IDE_ERROR
.396ce0		8d 06 03	sta $0306	                STA @w FDC_ST0
.396ce3		28		plp		                PLP
.396ce4		2b		pld		                PLD
.396ce5		ab		plb		                PLB
.396ce6		7a		ply		                PLY
.396ce7		18		clc		                CLC
.396ce8		6b		rtl		                RTL
.396ce9						IDE_GETBLOCK
.396ce9		5a		phy		                PHY
.396cea		8b		phb		                PHB
.396ceb		0b		phd		                PHD
.396cec		08		php		                PHP
.396ced		48		pha		                PHA             ; begin setdbr macro
.396cee		08		php		                PHP
.396cef		e2 20		sep #$20	                SEP #$20        ; set A short
.396cf1		a9 00		lda #$00	                LDA #0
.396cf3		48		pha		                PHA
.396cf4		ab		plb		                PLB
.396cf5		28		plp		                PLP
.396cf6		68		pla		                PLA             ; end setdbr macro
.396cf7		48		pha		                PHA             ; begin setdp macro
.396cf8		08		php		                PHP
.396cf9		c2 20		rep #$20	                REP #$20        ; set A long
.396cfb		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.396cfe		5b		tcd		                TCD
.396cff		28		plp		                PLP
.396d00		68		pla		                PLA             ; end setdp macro
.396d01		e2 20		sep #$20	                SEP #$20        ; set A short
.396d03		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; Wait until the IDE is clear to accept commands
.396d06		a5 05		lda $0325	                LDA BIOS_LBA+3                  ; Get the high bits of the LBA
.396d08		29 07		and #$07	                AND #$07
.396d0a		09 e0		ora #$e0	                ORA #%11100000                  ; Select DEV=0 and LBA mode = 1
.396d0c		8f 36 e8 af	sta $afe836	                STA @l IDE_HEAD                 ; Ensure master is selected
.396d10		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; And wait for it to take effect
.396d13		e2 20		sep #$20	                SEP #$20        ; set A short
.396d15		a9 01		lda #$01	                LDA #1                          ; Set that we want one sector
.396d17		8f 32 e8 af	sta $afe832	                STA @l IDE_SECT_CNT
.396d1b		a5 02		lda $0322	                LDA BIOS_LBA                    ; Set the lower bits of the LBA
.396d1d		8f 33 e8 af	sta $afe833	                STA @l IDE_SECT_SRT
.396d21		a5 03		lda $0323	                LDA BIOS_LBA+1
.396d23		8f 34 e8 af	sta $afe834	                STA @l IDE_CLDR_LO
.396d27		a5 04		lda $0324	                LDA BIOS_LBA+2
.396d29		8f 35 e8 af	sta $afe835	                STA @l IDE_CLDR_HI
.396d2d		a9 21		lda #$21	                LDA #IDE_CMD_READ_SECTOR        ; The READ SECTOR command
.396d2f		8f 37 e8 af	sta $afe837	                STA @l IDE_CMD_STAT
.396d33		ea		nop		                NOP                             ; Wait about 500ns
.396d34		ea		nop		                NOP
.396d35		ea		nop		                NOP
.396d36		ea		nop		                NOP
.396d37		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; Wait for the device to be ready
.396d3a		90 2b		bcc $396d67	                BCC ret_failure                 ; If an error occurred, return it
.396d3c		e2 20		sep #$20	                SEP #$20        ; set A short
.396d3e		af 30 e8 af	lda $afe830	                LDA @l IDE_DATA                 ; Read and toss out one byte from the 8-bit interface
.396d42		a0 00 00	ldy #$0000	                LDY #0
.396d45		c2 20		rep #$20	                REP #$20        ; set A long
.396d47		af 38 e8 af	lda $afe838	read_loop       LDA @l IDE_DATA_LO              ; Get the word of data from the device
.396d4b		97 06		sta [$0326],y	                STA [BIOS_BUFF_PTR],Y           ; Save it to the buffer
.396d4d		c8		iny		                INY                             ; Move to the next position
.396d4e		c8		iny		                INY
.396d4f		c0 00 02	cpy #$0200	                CPY #512
.396d52		d0 f3		bne $396d47	                BNE read_loop
.396d54		ea		nop		                NOP                             ; Wait about 500ns
.396d55		ea		nop		                NOP
.396d56		ea		nop		                NOP
.396d57		ea		nop		                NOP
.396d58						ret_success
.396d58		e2 20		sep #$20	                SEP #$20        ; set A short
.396d5a		a9 00		lda #$00	                LDA #0
.396d5c		85 00		sta $0320	                STA BIOS_STATUS
.396d5e		8d 06 03	sta $0306	                STA @w FDC_ST0
.396d61		28		plp		                PLP                             ; Return success
.396d62		2b		pld		                PLD
.396d63		ab		plb		                PLB
.396d64		7a		ply		                PLY
.396d65		38		sec		                SEC
.396d66		6b		rtl		                RTL
.396d67						ret_failure
.396d67		e2 20		sep #$20	                SEP #$20        ; set A short
.396d69		af 31 e8 af	lda $afe831	                LDA @l IDE_ERROR
.396d6d		8d 06 03	sta $0306	                STA @w FDC_ST0
.396d70		a9 82		lda #$82	                LDA #BIOS_ERR_READ
.396d72		85 00		sta $0320	                STA BIOS_STATUS
.396d74		28		plp		                PLP
.396d75		2b		pld		                PLD
.396d76		ab		plb		                PLB
.396d77		7a		ply		                PLY
.396d78		18		clc		                CLC
.396d79		6b		rtl		                RTL
.396d7a						IDE_PUTBLOCK
.396d7a		5a		phy		                PHY
.396d7b		8b		phb		                PHB
.396d7c		0b		phd		                PHD
.396d7d		08		php		                PHP
.396d7e		48		pha		                PHA             ; begin setdbr macro
.396d7f		08		php		                PHP
.396d80		e2 20		sep #$20	                SEP #$20        ; set A short
.396d82		a9 00		lda #$00	                LDA #0
.396d84		48		pha		                PHA
.396d85		ab		plb		                PLB
.396d86		28		plp		                PLP
.396d87		68		pla		                PLA             ; end setdbr macro
.396d88		48		pha		                PHA             ; begin setdp macro
.396d89		08		php		                PHP
.396d8a		c2 20		rep #$20	                REP #$20        ; set A long
.396d8c		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
.396d8f		5b		tcd		                TCD
.396d90		28		plp		                PLP
.396d91		68		pla		                PLA             ; end setdp macro
.396d92		e2 20		sep #$20	                SEP #$20        ; set A short
.396d94		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; Wait until the IDE is clear to accept commands
.396d97		a5 05		lda $0325	                LDA BIOS_LBA+3                  ; Get the high bits of the LBA
.396d99		29 07		and #$07	                AND #$07
.396d9b		09 e0		ora #$e0	                ORA #%11100000                  ; Select DEV=0 and LBA mode = 1
.396d9d		8f 36 e8 af	sta $afe836	                STA @l IDE_HEAD                 ; Ensure master is selected
.396da1		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; And wait for it to take effect
.396da4		e2 20		sep #$20	                SEP #$20        ; set A short
.396da6		a9 01		lda #$01	                LDA #1                          ; Set that we want one sector
.396da8		8f 32 e8 af	sta $afe832	                STA @l IDE_SECT_CNT
.396dac		a5 02		lda $0322	                LDA BIOS_LBA                    ; Set the lower bits of the LBA
.396dae		8f 33 e8 af	sta $afe833	                STA @l IDE_SECT_SRT
.396db2		a5 03		lda $0323	                LDA BIOS_LBA+1
.396db4		8f 34 e8 af	sta $afe834	                STA @l IDE_CLDR_LO
.396db8		a5 04		lda $0324	                LDA BIOS_LBA+2
.396dba		8f 35 e8 af	sta $afe835	                STA @l IDE_CLDR_HI
.396dbe		a9 30		lda #$30	                LDA #IDE_CMD_WRITE_SECTOR       ; The READ SECTOR command
.396dc0		8f 37 e8 af	sta $afe837	                STA @l IDE_CMD_STAT
.396dc4		ea		nop		                NOP                             ; Wait about 500ns
.396dc5		ea		nop		                NOP
.396dc6		ea		nop		                NOP
.396dc7		ea		nop		                NOP
.396dc8		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; Wait for the device to be ready
.396dcb		90 33		bcc $396e00	                BCC ret_failure                 ; If an error occurred, return it
.396dcd		c2 30		rep #$30	                REP #$30        ; set A&X long
.396dcf		a0 00 00	ldy #$0000	                LDY #0
.396dd2		b7 06		lda [$0326],y	read_loop       LDA [BIOS_BUFF_PTR],Y           ; Get the word from the buffer
.396dd4		8f 38 e8 af	sta $afe838	                STA @l IDE_DATA_LO              ; Save the word to the device
.396dd8		c8		iny		                INY                             ; Move to the next position
.396dd9		c8		iny		                INY
.396dda		c0 00 02	cpy #$0200	                CPY #512
.396ddd		d0 f3		bne $396dd2	                BNE read_loop
.396ddf		ea		nop		                NOP                             ; Wait about 500ns
.396de0		ea		nop		                NOP
.396de1		ea		nop		                NOP
.396de2		ea		nop		                NOP
.396de3		20 35 6c	jsr $396c35	                JSR IDE_DRV_READY_NOTBUSY       ; Wait for the device to be ready
.396de6		90 18		bcc $396e00	                BCC ret_failure                 ; If an error occurred, return it
.396de8		af 37 e8 af	lda $afe837	                LDA @l IDE_CMD_STAT             ; Check the status
.396dec		89 21 00	bit #$0021	                BIT #IDE_STAT_ERR | IDE_STAT_DF
.396def		d0 0f		bne $396e00	                BNE ret_failure                 ; If error: return failure
.396df1						ret_success
.396df1		e2 20		sep #$20	                SEP #$20        ; set A short
.396df3		a9 00		lda #$00	                LDA #0
.396df5		85 00		sta $0320	                STA BIOS_STATUS
.396df7		8d 06 03	sta $0306	                STA @w FDC_ST0
.396dfa		28		plp		                PLP                             ; Return success
.396dfb		2b		pld		                PLD
.396dfc		ab		plb		                PLB
.396dfd		7a		ply		                PLY
.396dfe		38		sec		                SEC
.396dff		6b		rtl		                RTL
.396e00						ret_failure
.396e00		e2 20		sep #$20	                SEP #$20        ; set A short
.396e02		af 31 e8 af	lda $afe831	                LDA @l IDE_ERROR
.396e06		8d 06 03	sta $0306	                STA @w FDC_ST0
.396e09		a9 82		lda #$82	                LDA #BIOS_ERR_READ
.396e0b		85 00		sta $0320	                STA BIOS_STATUS
.396e0d		28		plp		                PLP
.396e0e		2b		pld		                PLD
.396e0f		ab		plb		                PLB
.396e10		7a		ply		                PLY
.396e11		18		clc		                CLC
.396e12		6b		rtl		                RTL

;******  Return to file: src\kernel.asm

.396e13						KERNEL_DATA
>396e13		20 20 20 20 0b 0c 0b 0c		greet_msg       .text $20, $20, $20, $20, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, " FFFFFFF MMMMMMMM XX    XXX " ,$0D
>396e1b		0b 0c 0b 0c 0b 0c 20 46 46 46 46 46 46 46 20 4d
>396e2b		4d 4d 4d 4d 4d 4d 4d 20 58 58 20 20 20 20 58 58
>396e3b		58 20 0d
>396e3e		20 20 20 0b 0c 0b 0c 0b		                .text $20, $20, $20, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $20, "FF      MM MM MM   XX XXX   ",$0D
>396e46		0c 0b 0c 0b 0c 20 46 46 20 20 20 20 20 20 4d 4d
>396e56		20 4d 4d 20 4d 4d 20 20 20 58 58 20 58 58 58 20
>396e66		20 20 0d
>396e69		20 20 0b 0c 0b 0c 0b 0c		                .text $20, $20, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $20, "FFFFF   MM MM MM    XXX      ",$0D
>396e71		0b 0c 0b 0c 20 46 46 46 46 46 20 20 20 4d 4d 20
>396e81		4d 4d 20 4d 4d 20 20 20 20 58 58 58 20 20 20 20
>396e91		20 20 0d
>396e94		20 0b 0c 0b 0c 0b 0c 0b		                .text $20, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $20, "FF      MM MM MM  XXX  XX     ",$0D
>396e9c		0c 0b 0c 20 46 46 20 20 20 20 20 20 4d 4d 20 4d
>396eac		4d 20 4d 4d 20 20 58 58 58 20 20 58 58 20 20 20
>396ebc		20 20 0d
>396ebf		0b 0c 0b 0c 0b 0c 0b 0c		                .text $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $20, "FF      MM MM MM XXX     XX    ",$0D
>396ec7		0b 0c 20 46 46 20 20 20 20 20 20 4d 4d 20 4d 4d
>396ed7		20 4d 4d 20 58 58 58 20 20 20 20 20 58 58 20 20
>396ee7		20 20 0d
>396eea		0d 43 32 35 36 20 46 4f		                .text $0D, "C256 FOENIX FMX -- 3,670,016 Bytes Free", $0D
>396ef2		45 4e 49 58 20 46 4d 58 20 2d 2d 20 33 2c 36 37
>396f02		30 2c 30 31 36 20 42 79 74 65 73 20 46 72 65 65
>396f12		0d
>396f13		77 77 77 2e 63 32 35 36		                .text "www.c256foenix.com - Kernel version: "
>396f1b		66 6f 65 6e 69 78 2e 63 6f 6d 20 2d 20 4b 65 72
>396f2b		6e 65 6c 20 76 65 72 73 69 6f 6e 3a 20

;******  Processing file: src\version.asm

>396f38		76 30 2e 31 2e 30 2d 61		.text "v0.1.0-alpha+1011 (2020-12-31)"
>396f40		6c 70 68 61 2b 31 30 31 31 20 28 32 30 32 30 2d
>396f50		31 32 2d 33 31 29

;******  Return to file: src\kernel.asm

>396f56		0d 00				                .text $0D,$00
.396f58						old_pc_style_stat
>396f58		1d 1d 1d 1d 1d 1d 8d 8d		greet_clr_line1 .text $1D, $1D, $1D, $1D, $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
>396f60		4d 4d 2d 2d 5d 5d fd fd fd fd fd fd fd fd fd fd
>396f70		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
>396f80		fd fd
>396f82		1d 1d 1d 1d 1d 8d 8d 4d		greet_clr_line2 .text $1D, $1D, $1D, $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
>396f8a		4d 2d 2d 5d 5d fd fd fd fd fd fd fd fd fd fd fd
>396f9a		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
>396faa		fd fd
>396fac		1d 1d 1d 1d 8d 8d 4d 4d		greet_clr_line3 .text $1D, $1D, $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
>396fb4		2d 2d 5d 5d fd fd fd fd fd fd fd fd fd fd fd fd
>396fc4		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
>396fd4		fd fd
>396fd6		1d 1d 1d 8d 8d 4d 4d 2d		greet_clr_line4 .text $1D, $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
>396fde		2d 5d 5d fd fd fd fd fd fd fd fd fd fd fd fd fd
>396fee		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
>396ffe		fd fd
>397000		1d 1d 8d 8d 4d 4d 2d 2d		greet_clr_line5 .text $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
>397008		5d 5d fd fd fd fd fd fd fd fd fd fd fd fd fd fd
>397018		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
>397028		fd fd
>39702a		00 00 00 ff			fg_color_lut	  .text $00, $00, $00, $FF
>39702e		00 00 80 ff			                .text $00, $00, $80, $FF
>397032		00 80 00 ff			                .text $00, $80, $00, $FF
>397036		80 00 00 ff			                .text $80, $00, $00, $FF
>39703a		00 80 80 ff			                .text $00, $80, $80, $FF
>39703e		80 80 00 ff			                .text $80, $80, $00, $FF
>397042		80 00 80 ff			                .text $80, $00, $80, $FF
>397046		80 80 80 ff			                .text $80, $80, $80, $FF
>39704a		00 45 ff ff			                .text $00, $45, $FF, $FF
>39704e		13 45 8b ff			                .text $13, $45, $8B, $FF
>397052		00 00 20 ff			                .text $00, $00, $20, $FF
>397056		00 20 00 ff			                .text $00, $20, $00, $FF
>39705a		20 00 00 ff			                .text $20, $00, $00, $FF
>39705e		20 20 20 ff			                .text $20, $20, $20, $FF
>397062		40 40 40 ff			                .text $40, $40, $40, $FF
>397066		ff ff ff ff			                .text $FF, $FF, $FF, $FF
>39706a		00 00 00 ff			bg_color_lut	  .text $00, $00, $00, $FF
>39706e		00 00 80 ff			                .text $00, $00, $80, $FF
>397072		00 80 00 ff			                .text $00, $80, $00, $FF
>397076		80 00 00 ff			                .text $80, $00, $00, $FF
>39707a		00 20 20 ff			                .text $00, $20, $20, $FF
>39707e		20 20 00 ff			                .text $20, $20, $00, $FF
>397082		20 00 20 ff			                .text $20, $00, $20, $FF
>397086		20 20 20 ff			                .text $20, $20, $20, $FF
>39708a		1e 69 d2 ff			                .text $1E, $69, $D2, $FF
>39708e		13 45 8b ff			                .text $13, $45, $8B, $FF
>397092		00 00 20 ff			                .text $00, $00, $20, $FF
>397096		00 20 00 ff			                .text $00, $20, $00, $FF
>39709a		40 00 00 ff			                .text $40, $00, $00, $FF
>39709e		10 10 10 ff			                .text $10, $10, $10, $FF
>3970a2		40 40 40 ff			                .text $40, $40, $40, $FF
>3970a6		ff ff ff ff			                .text $FF, $FF, $FF, $FF
>3970aa		43 6d 64 20 30 78 41 41		pass_tst0xAAmsg .text "Cmd 0xAA Test passed...", $0D, $00
>3970b2		20 54 65 73 74 20 70 61 73 73 65 64 2e 2e 2e 0d
>3970c2		00
>3970c3		43 6d 64 20 30 78 41 42		pass_tst0xABmsg .text "Cmd 0xAB Test passed...", $0D, $00
>3970cb		20 54 65 73 74 20 70 61 73 73 65 64 2e 2e 2e 0d
>3970db		00
>3970dc		43 6d 64 20 30 78 36 30		pass_cmd0x60msg .text "Cmd 0x60 Executed.", $0D, $00
>3970e4		20 45 78 65 63 75 74 65 64 2e 0d 00
>3970f0		43 6d 64 20 30 78 46 46		pass_cmd0xFFmsg .text "Cmd 0xFF (Reset) Done.", $0D, $00
>3970f8		20 28 52 65 73 65 74 29 20 44 6f 6e 65 2e 0d 00
>397108		43 6d 64 20 30 78 45 45		pass_cmd0xEEmsg .text "Cmd 0xEE Echo Test passed...", $0D, $00
>397110		20 45 63 68 6f 20 54 65 73 74 20 70 61 73 73 65
>397120		64 2e 2e 2e 0d 00
>397126		4b 65 79 62 6f 61 72 64		Success_kb_init .text "Keyboard Present", $0D, $00
>39712e		20 50 72 65 73 65 6e 74 0d 00
>397138		4e 6f 20 4b 65 79 62 6f		Failed_kb_init  .text "No Keyboard Attached or Failed Init...", $0D, $00
>397140		61 72 64 20 41 74 74 61 63 68 65 64 20 6f 72 20
>397150		46 61 69 6c 65 64 20 49 6e 69 74 2e 2e 2e 0d 00
>397160		4e 4f 20 53 49 47 4e 41		bmp_parser_err0 .text "NO SIGNATURE FOUND.", $00
>397168		54 55 52 45 20 46 4f 55 4e 44 2e 00
>397174		42 4d 50 20 4c 4f 41 44		bmp_parser_msg0 .text "BMP LOADED.", $00
>39717c		45 44 2e 00
>397180		45 58 45 43 55 54 49 4e		bmp_parser_msg1 .text "EXECUTING BMP PARSER", $00
>397188		47 20 42 4d 50 20 50 41 52 53 45 52 00
>397195		49 44 45 20 48 44 44 20		IDE_HDD_Present_msg0 .text "IDE HDD Present:", $00
>39719d		50 72 65 73 65 6e 74 3a 00
>3971a6		42 6f 6f 74 20 44 49 50		boot_invalid    .null "Boot DIP switch settings are invalid."
>3971ae		20 73 77 69 74 63 68 20 73 65 74 74 69 6e 67 73
>3971be		20 61 72 65 20 69 6e 76 61 6c 69 64 2e 00
>3971cc		50 72 65 73 73 20 52 20		boot_retry      .null "Press R to retry, B to go to BASIC.", 13
>3971d4		74 6f 20 72 65 74 72 79 2c 20 42 20 74 6f 20 67
>3971e4		6f 20 74 6f 20 42 41 53 49 43 2e 0d 00
>3971f1		55 6e 61 62 6c 65 20 74		sdc_err_boot    .null "Unable to read the SD card."
>3971f9		6f 20 72 65 61 64 20 74 68 65 20 53 44 20 63 61
>397209		72 64 2e 00
>39720d		55 6e 61 62 6c 65 20 74		ide_err_boot    .null "Unable to read from the IDE drive."
>397215		6f 20 72 65 61 64 20 66 72 6f 6d 20 74 68 65 20
>397225		49 44 45 20 64 72 69 76 65 2e 00
>397230		55 6e 61 62 6c 65 20 74		fdc_err_boot    .null "Unable to read from the floppy drive."
>397238		6f 20 72 65 61 64 20 66 72 6f 6d 20 74 68 65 20
>397248		66 6c 6f 70 70 79 20 64 72 69 76 65 2e 00
>397256		42 6f 6f 74 69 6e 67 20		fdc_boot        .null "Booting from floppy..."
>39725e		66 72 6f 6d 20 66 6c 6f 70 70 79 2e 2e 2e 00
>39726d		0d 52 45 41 44 59 2e 00		ready_msg       .null $0D,"READY."
>397275		41 42 4f 52 54 20 45 52		error_01        .null "ABORT ERROR"
>39727d		52 4f 52 00
>397281		30 31 32 33 34 35 36 37		hex_digits      .text "0123456789ABCDEF",0
>397289		38 39 41 42 43 44 45 46 00
>397292						.align 256
>397300		00 1b 31 32 33 34 35 36		ScanCode_Press_Set1   .text $00, $1B, $31, $32, $33, $34, $35, $36, $37, $38, $39, $30, $2D, $3D, $08, $09    ; $00
>397308		37 38 39 30 2d 3d 08 09
>397310		71 77 65 72 74 79 75 69		                      .text $71, $77, $65, $72, $74, $79, $75, $69, $6F, $70, $5B, $5D, $0D, $00, $61, $73    ; $10
>397318		6f 70 5b 5d 0d 00 61 73
>397320		64 66 67 68 6a 6b 6c 3b		                      .text $64, $66, $67, $68, $6A, $6B, $6C, $3B, $27, $60, $00, $5C, $7A, $78, $63, $76    ; $20
>397328		27 60 00 5c 7a 78 63 76
>397330		62 6e 6d 2c 2e 2f 00 2a		                      .text $62, $6E, $6D, $2C, $2E, $2F, $00, $2A, $00, $20, $00, $81, $82, $83, $84, $85    ; $30
>397338		00 20 00 81 82 83 84 85
>397340		86 87 88 89 8a 00 00 00		                      .text $86, $87, $88, $89, $8A, $00, $00, $00, $11, $00, $00, $9D, $00, $1D, $00, $00    ; $40
>397348		11 00 00 9d 00 1d 00 00
>397350		91 00 00 00 00 00 00 8b		                      .text $91, $00, $00, $00, $00, $00, $00, $8B, $8C, $00, $00, $00, $00, $00, $00, $00    ; $50
>397358		8c 00 00 00 00 00 00 00
>397360		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
>397368		00 00 00 00 00 00 00 00
>397370		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
>397378		00 00 00 00 00 00 00 00
>397380		00 00 21 40 23 24 25 5e		ScanCode_Shift_Set1   .text $00, $00, $21, $40, $23, $24, $25, $5E, $26, $2A, $28, $29, $5F, $2B, $08, $09    ; $00
>397388		26 2a 28 29 5f 2b 08 09
>397390		51 57 45 52 54 59 55 49		                      .text $51, $57, $45, $52, $54, $59, $55, $49, $4F, $50, $7B, $7D, $0D, $00, $41, $53    ; $10
>397398		4f 50 7b 7d 0d 00 41 53
>3973a0		44 46 47 48 4a 4b 4c 3a		                      .text $44, $46, $47, $48, $4A, $4B, $4C, $3A, $22, $7E, $00, $7C, $5A, $58, $43, $56    ; $20
>3973a8		22 7e 00 7c 5a 58 43 56
>3973b0		42 4e 4d 3c 3e 3f 00 00		                      .text $42, $4E, $4D, $3C, $3E, $3F, $00, $00, $00, $20, $00, $00, $00, $00, $00, $00    ; $30
>3973b8		00 20 00 00 00 00 00 00
>3973c0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $40
>3973c8		00 00 00 00 00 00 00 00
>3973d0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
>3973d8		00 00 00 00 00 00 00 00
>3973e0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
>3973e8		00 00 00 00 00 00 00 00
>3973f0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
>3973f8		00 00 00 00 00 00 00 00
>397400		00 1b 31 32 33 34 35 36		ScanCode_Ctrl_Set1    .text $00, $1B, $31, $32, $33, $34, $35, $36, $37, $38, $39, $30, $2D, $3D, $08, $09    ; $00
>397408		37 38 39 30 2d 3d 08 09
>397410		11 17 05 12 14 19 15 09		                      .text $11, $17, $05, $12, $14, $19, $15, $09, $0F, $10, $5B, $5D, $0D, $00, $01, $13    ; $10
>397418		0f 10 5b 5d 0d 00 01 13
>397420		04 06 07 08 0a 0b 0c 3b		                      .text $04, $06, $07, $08, $0A, $0B, $0C, $3B, $27, $00, $00, $5C, $1A, $18, $03, $16    ; $20
>397428		27 00 00 5c 1a 18 03 16
>397430		02 0e 0d 2c 2e 2f 00 2a		                      .text $02, $0E, $0D, $2C, $2E, $2F, $00, $2A, $00, $20, $00, $00, $00, $00, $00, $00    ; $30
>397438		00 20 00 00 00 00 00 00
>397440		00 00 00 00 00 18 00 00		                      .text $00, $00, $00, $00, $00, $18, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $40
>397448		00 00 00 00 00 00 00 00
>397450		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
>397458		00 00 00 00 00 00 00 00
>397460		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
>397468		00 00 00 00 00 00 00 00
>397470		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
>397478		00 00 00 00 00 00 00 00
>397480		00 1b 31 32 33 34 35 36		ScanCode_Alt_Set1     .text $00, $1B, $31, $32, $33, $34, $35, $36, $37, $38, $39, $30, $2D, $3D, $08, $09    ; $00
>397488		37 38 39 30 2d 3d 08 09
>397490		71 77 65 72 74 79 75 69		                      .text $71, $77, $65, $72, $74, $79, $75, $69, $6F, $70, $5B, $5D, $0D, $00, $61, $73    ; $10
>397498		6f 70 5b 5d 0d 00 61 73
>3974a0		64 66 67 68 6a 6b 6c 3b		                      .text $64, $66, $67, $68, $6A, $6B, $6C, $3B, $27, $60, $00, $5C, $7A, $78, $63, $76    ; $20
>3974a8		27 60 00 5c 7a 78 63 76
>3974b0		62 6e 6d 2c 2e 2f 00 2a		                      .text $62, $6E, $6D, $2C, $2E, $2F, $00, $2A, $00, $20, $00, $00, $00, $00, $00, $00    ; $30
>3974b8		00 20 00 00 00 00 00 00
>3974c0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $40
>3974c8		00 00 00 00 00 00 00 00
>3974d0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
>3974d8		00 00 00 00 00 00 00 00
>3974e0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
>3974e8		00 00 00 00 00 00 00 00
>3974f0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
>3974f8		00 00 00 00 00 00 00 00
>397500		00 1b 31 32 33 34 35 36		ScanCode_NumLock_Set1 .text $00, $1B, $31, $32, $33, $34, $35, $36, $37, $38, $39, $30, $2D, $3D, $08, $09    ; $00
>397508		37 38 39 30 2d 3d 08 09
>397510		71 77 65 72 74 79 75 69		                      .text $71, $77, $65, $72, $74, $79, $75, $69, $6F, $70, $5B, $5D, $0D, $00, $61, $73    ; $10
>397518		6f 70 5b 5d 0d 00 61 73
>397520		64 66 67 68 6a 6b 6c 3b		                      .text $64, $66, $67, $68, $6A, $6B, $6C, $3B, $27, $60, $00, $5C, $7A, $78, $63, $76    ; $20
>397528		27 60 00 5c 7a 78 63 76
>397530		62 6e 6d 2c 2e 2f 00 2a		                      .text $62, $6E, $6D, $2C, $2E, $2F, $00, $2A, $00, $20, $00, $00, $00, $00, $00, $00    ; $30
>397538		00 20 00 00 00 00 00 00
>397540		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $40
>397548		00 00 00 00 00 00 00 00
>397550		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
>397558		00 00 00 00 00 00 00 00
>397560		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
>397568		00 00 00 00 00 00 00 00
>397570		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
>397578		00 00 00 00 00 00 00 00
>397580		00 00 00 00 00 00 00 00		ScanCode_Prefix_Set1  .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $00
>397588		00 00 00 00 00 00 00 00
>397590		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $10
>397598		00 00 00 00 00 00 00 00
>3975a0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $20
>3975a8		00 00 00 00 00 00 00 00
>3975b0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $30
>3975b8		00 00 00 00 00 00 00 00
>3975c0		00 00 00 00 00 00 00 01		                      .text $00, $00, $00, $00, $00, $00, $00, $01, $11, $00, $00, $9D, $00, $1D, $00, $05    ; $40
>3975c8		11 00 00 9d 00 1d 00 05
>3975d0		91 00 0f 7f 00 00 00 00		                      .text $91, $00, $0F, $7F, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
>3975d8		00 00 00 00 00 00 00 00
>3975e0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
>3975e8		00 00 00 00 00 00 00 00
>3975f0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
>3975f8		00 00 00 00 00 00 00 00
>397600						.align 256
>397600		00 14 1c 21 26 2a 2e 31		GAMMA_2_2_Tbl         .text  $00, $14, $1c, $21, $26, $2a, $2e, $31, $34, $37, $3a, $3d, $3f, $41, $44, $46
>397608		34 37 3a 3d 3f 41 44 46
>397610		48 4a 4c 4e 50 51 53 55		                      .text  $48, $4a, $4c, $4e, $50, $51, $53, $55, $57, $58, $5a, $5b, $5d, $5e, $60, $61
>397618		57 58 5a 5b 5d 5e 60 61
>397620		63 64 66 67 68 6a 6b 6c		                      .text  $63, $64, $66, $67, $68, $6a, $6b, $6c, $6d, $6f, $70, $71, $72, $73, $75, $76
>397628		6d 6f 70 71 72 73 75 76
>397630		77 78 79 7a 7b 7c 7d 7e		                      .text  $77, $78, $79, $7a, $7b, $7c, $7d, $7e, $80, $81, $82, $83, $84, $85, $86, $87
>397638		80 81 82 83 84 85 86 87
>397640		88 88 89 8a 8b 8c 8d 8e		                      .text  $88, $88, $89, $8a, $8b, $8c, $8d, $8e, $8f, $90, $91, $92, $93, $93, $94, $95
>397648		8f 90 91 92 93 93 94 95
>397650		96 97 98 99 99 9a 9b 9c		                      .text  $96, $97, $98, $99, $99, $9a, $9b, $9c, $9d, $9e, $9e, $9f, $a0, $a1, $a2, $a2
>397658		9d 9e 9e 9f a0 a1 a2 a2
>397660		a3 a4 a5 a5 a6 a7 a8 a8		                      .text  $a3, $a4, $a5, $a5, $a6, $a7, $a8, $a8, $a9, $aa, $ab, $ab, $ac, $ad, $ae, $ae
>397668		a9 aa ab ab ac ad ae ae
>397670		af b0 b0 b1 b2 b2 b3 b4		                      .text  $AF, $b0, $b0, $b1, $b2, $b2, $b3, $b4, $b5, $b5, $b6, $b7, $b7, $b8, $b9, $b9
>397678		b5 b5 b6 b7 b7 b8 b9 b9
>397680		ba bb bb bc bd bd be be		                      .text  $ba, $bb, $bb, $bc, $bd, $bd, $be, $be, $bf, $c0, $c0, $c1, $c2, $c2, $c3, $c4
>397688		bf c0 c0 c1 c2 c2 c3 c4
>397690		c4 c5 c5 c6 c7 c7 c8 c8		                      .text  $c4, $c5, $c5, $c6, $c7, $c7, $c8, $c8, $c9, $ca, $ca, $cb, $cb, $cc, $cd, $cd
>397698		c9 ca ca cb cb cc cd cd
>3976a0		ce ce cf d0 d0 d1 d1 d2		                      .text  $ce, $ce, $cf, $d0, $d0, $d1, $d1, $d2, $d2, $d3, $d4, $d4, $d5, $d5, $d6, $d6
>3976a8		d2 d3 d4 d4 d5 d5 d6 d6
>3976b0		d7 d8 d8 d9 d9 da da db		                      .text  $d7, $d8, $d8, $d9, $d9, $da, $da, $db, $db, $dc, $dc, $dd, $de, $de, $df, $df
>3976b8		db dc dc dd de de df df
>3976c0		e0 e0 e1 e1 e2 e2 e3 e3		                      .text  $e0, $e0, $e1, $e1, $e2, $e2, $e3, $e3, $e4, $e4, $e5, $e5, $e6, $e6, $e7, $e7
>3976c8		e4 e4 e5 e5 e6 e6 e7 e7
>3976d0		e8 e8 e9 e9 ea ea eb eb		                      .text  $e8, $e8, $e9, $e9, $ea, $ea, $eb, $eb, $ec, $ec, $ed, $ed, $ee, $ee, $ef, $ef
>3976d8		ec ec ed ed ee ee ef ef
>3976e0		f0 f0 f1 f1 f2 f2 f3 f3		                      .text  $f0, $f0, $f1, $f1, $f2, $f2, $f3, $f3, $f4, $f4, $f5, $f5, $f6, $f6, $f7, $f7
>3976e8		f4 f4 f5 f5 f6 f6 f7 f7
>3976f0		f8 f8 f9 f9 f9 fa fa fb		                      .text  $f8, $f8, $f9, $f9, $f9, $fa, $fa, $fb, $fb, $fc, $fc, $fd, $fd, $fe, $fe, $ff
>3976f8		fb fc fc fd fd fe fe ff
>397700						.align 256
>397700		00 0b 11 15 19 1c 1f 22		GAMMA_1_8_Tbl         .text  $00, $0b, $11, $15, $19, $1c, $1f, $22, $25, $27, $2a, $2c, $2e, $30, $32, $34
>397708		25 27 2a 2c 2e 30 32 34
>397710		36 38 3a 3c 3d 3f 41 43		                      .text  $36, $38, $3a, $3c, $3d, $3f, $41, $43, $44, $46, $47, $49, $4a, $4c, $4d, $4f
>397718		44 46 47 49 4a 4c 4d 4f
>397720		50 51 53 54 55 57 58 59		                      .text  $50, $51, $53, $54, $55, $57, $58, $59, $5b, $5c, $5d, $5e, $60, $61, $62, $63
>397728		5b 5c 5d 5e 60 61 62 63
>397730		64 65 67 68 69 6a 6b 6c		                      .text  $64, $65, $67, $68, $69, $6a, $6b, $6c, $6d, $6e, $70, $71, $72, $73, $74, $75
>397738		6d 6e 70 71 72 73 74 75
>397740		76 77 78 79 7a 7b 7c 7d		                      .text  $76, $77, $78, $79, $7a, $7b, $7c, $7d, $7e, $7f, $80, $81, $82, $83, $84, $84
>397748		7e 7f 80 81 82 83 84 84
>397750		85 86 87 88 89 8a 8b 8c		                      .text  $85, $86, $87, $88, $89, $8a, $8b, $8c, $8d, $8e, $8e, $8f, $90, $91, $92, $93
>397758		8d 8e 8e 8f 90 91 92 93
>397760		94 95 95 96 97 98 99 9a		                      .text  $94, $95, $95, $96, $97, $98, $99, $9a, $9a, $9b, $9c, $9d, $9e, $9f, $9f, $a0
>397768		9a 9b 9c 9d 9e 9f 9f a0
>397770		a1 a2 a3 a3 a4 a5 a6 a6		                      .text  $a1, $a2, $a3, $a3, $a4, $a5, $a6, $a6, $a7, $a8, $a9, $aa, $aa, $ab, $ac, $ad
>397778		a7 a8 a9 aa aa ab ac ad
>397780		ad ae af b0 b0 b1 b2 b3		                      .text  $ad, $ae, $af, $b0, $b0, $b1, $b2, $b3, $b3, $b4, $b5, $b6, $b6, $b7, $b8, $b8
>397788		b3 b4 b5 b6 b6 b7 b8 b8
>397790		b9 ba bb bb bc bd bd be		                      .text  $b9, $ba, $bb, $bb, $bc, $bd, $bd, $be, $bf, $bf, $c0, $c1, $c2, $c2, $c3, $c4
>397798		bf bf c0 c1 c2 c2 c3 c4
>3977a0		c4 c5 c6 c6 c7 c8 c8 c9		                      .text  $c4, $c5, $c6, $c6, $c7, $c8, $c8, $c9, $ca, $ca, $cb, $cc, $cc, $cd, $ce, $ce
>3977a8		ca ca cb cc cc cd ce ce
>3977b0		cf d0 d0 d1 d2 d2 d3 d4		                      .text  $cf, $d0, $d0, $d1, $d2, $d2, $d3, $d4, $d4, $d5, $d6, $d6, $d7, $d7, $d8, $d9
>3977b8		d4 d5 d6 d6 d7 d7 d8 d9
>3977c0		d9 da db db dc dc dd de		                      .text  $d9, $da, $db, $db, $dc, $dc, $dd, $de, $de, $df, $e0, $e0, $e1, $e1, $e2, $e3
>3977c8		de df e0 e0 e1 e1 e2 e3
>3977d0		e3 e4 e4 e5 e6 e6 e7 e7		                      .text  $e3, $e4, $e4, $e5, $e6, $e6, $e7, $e7, $e8, $e9, $e9, $ea, $ea, $eb, $ec, $ec
>3977d8		e8 e9 e9 ea ea eb ec ec
>3977e0		ed ed ee ef ef f0 f0 f1		                      .text  $ed, $ed, $ee, $ef, $ef, $f0, $f0, $f1, $f1, $f2, $f3, $f3, $f4, $f4, $f5, $f5
>3977e8		f1 f2 f3 f3 f4 f4 f5 f5
>3977f0		f6 f7 f7 f8 f8 f9 f9 fa		                      .text  $f6, $f7, $f7, $f8, $f8, $f9, $f9, $fa, $fb, $fb, $fc, $fc, $fd, $fd, $fe, $ff
>3977f8		fb fb fc fc fd fd fe ff
>397800						.align 256
>397800		1d c8 a7 ac 10 d6 52 7c		RANDOM_LUT_Tbl		    .text  $1d, $c8, $a7, $ac, $10, $d6, $52, $7c, $83, $dd, $ce, $39, $cd, $c5, $3b, $15
>397808		83 dd ce 39 cd c5 3b 15
>397810		22 55 3b 94 e0 33 1f 38						              .text  $22, $55, $3b, $94, $e0, $33, $1f, $38, $87, $12, $31, $65, $89, $27, $88, $42
>397818		87 12 31 65 89 27 88 42
>397820		b2 32 72 84 b2 b2 31 52						              .text  $b2, $32, $72, $84, $b2, $b2, $31, $52, $94, $ce, $56, $ec, $fe, $da, $58, $c9
>397828		94 ce 56 ec fe da 58 c9
>397830		c8 5b 53 2a 08 3b 19 c1						              .text  $c8, $5b, $53, $2a, $08, $3b, $19, $c1, $d0, $10, $2c, $b2, $4b, $ea, $32, $61
>397838		d0 10 2c b2 4b ea 32 61
>397840		da 34 33 8f 2b da 49 89						              .text  $da, $34, $33, $8f, $2b, $da, $49, $89, $a1, $e6, $ca, $2d, $b3, $ce, $b0, $79
>397848		a1 e6 ca 2d b3 ce b0 79
>397850		44 aa 32 82 91 e9 29 16						              .text  $44, $aa, $32, $82, $91, $e9, $29, $16, $5f, $e3, $fb, $bd, $15, $2e, $be, $f5
>397858		5f e3 fb bd 15 2e be f5
>397860		e9 4a e4 2e 60 24 94 35						              .text  $e9, $4a, $e4, $2e, $60, $24, $94, $35, $8d, $8f, $2c, $80, $0a, $5e, $99, $36
>397868		8d 8f 2c 80 0a 5e 99 36
>397870		ac ab 21 26 42 7c 5e bc						              .text  $ac, $ab, $21, $26, $42, $7c, $5e, $bc, $13, $52, $44, $2f, $e3, $ef, $44, $a2
>397878		13 52 44 2f e3 ef 44 a2
>397880		86 c1 9c 47 5f 36 6d 02						              .text  $86, $c1, $9c, $47, $5f, $36, $6d, $02, $be, $23, $02, $58, $0a, $52, $5e, $b4
>397888		be 23 02 58 0a 52 5e b4
>397890		9f 06 08 c9 97 cb 9e dd						              .text  $9f, $06, $08, $c9, $97, $cb, $9e, $dd, $d5, $cf, $3e, $df, $c4, $9e, $da, $bb
>397898		d5 cf 3e df c4 9e da bb
>3978a0		9b 5d c9 f5 d9 c3 7e 87						              .text  $9b, $5d, $c9, $f5, $d9, $c3, $7e, $87, $77, $7d, $b1, $3b, $4a, $68, $35, $6e
>3978a8		77 7d b1 3b 4a 68 35 6e
>3978b0		ee 47 ad 8f fd 73 2e 46						              .text  $ee, $47, $ad, $8f, $fd, $73, $2e, $46, $b5, $8f, $44, $63, $55, $6f, $e1, $50
>3978b8		b5 8f 44 63 55 6f e1 50
>3978c0		f4 b6 a3 4f 68 c4 a5 a4						              .text  $f4, $b6, $a3, $4f, $68, $c4, $a5, $a4, $57, $74, $b9, $bd, $05, $14, $50, $eb
>3978c8		57 74 b9 bd 05 14 50 eb
>3978d0		a5 5c 57 2f 99 dc 2e 8a						              .text  $a5, $5c, $57, $2f, $99, $dc, $2e, $8a, $44, $bc, $ec, $db, $22, $58, $fc, $be
>3978d8		44 bc ec db 22 58 fc be
>3978e0		5f 3f 50 bd 2a 36 ab ae						              .text  $5f, $3f, $50, $bd, $2a, $36, $ab, $ae, $24, $aa, $82, $11, $5c, $9f, $43, $4d
>3978e8		24 aa 82 11 5c 9f 43 4d
>3978f0		8f 0c 20 00 91 b6 45 9e						              .text  $8f, $0c, $20, $00, $91, $b6, $45, $9e, $3e, $3d, $66, $7e, $0a, $1c, $6b, $74
>3978f8		3e 3d 66 7e 0a 1c 6b 74
>397900						.align 16
>397900		00 01 01 00 00 00 00 00		MOUSE_POINTER_PTR     .text $00,$01,$01,$00,$00,$00,$00,$00,$01,$01,$01,$00,$00,$00,$00,$00
>397908		01 01 01 00 00 00 00 00
>397910		01 ff ff 01 00 00 01 01		                      .text $01,$FF,$FF,$01,$00,$00,$01,$01,$FF,$FF,$FF,$01,$00,$00,$00,$00
>397918		ff ff ff 01 00 00 00 00
>397920		01 ff ff ff 01 01 55 ff		                      .text $01,$FF,$FF,$FF,$01,$01,$55,$FF,$01,$55,$FF,$FF,$01,$00,$00,$00
>397928		01 55 ff ff 01 00 00 00
>397930		01 55 ff ff ff ff 01 55		                      .text $01,$55,$FF,$FF,$FF,$FF,$01,$55,$FF,$FF,$FF,$FF,$01,$00,$00,$00
>397938		ff ff ff ff 01 00 00 00
>397940		00 01 55 ff ff ff ff ff		                      .text $00,$01,$55,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$01,$FF,$FF,$01,$00,$00
>397948		ff ff 01 ff ff 01 00 00
>397950		00 00 01 55 ff ff ff ff		                      .text $00,$00,$01,$55,$FF,$FF,$FF,$FF,$01,$FF,$FF,$01,$FF,$01,$00,$00
>397958		01 ff ff 01 ff 01 00 00
>397960		00 00 01 01 55 ff ff ff		                      .text $00,$00,$01,$01,$55,$FF,$FF,$FF,$FF,$01,$FF,$FF,$FF,$01,$00,$00
>397968		ff 01 ff ff ff 01 00 00
>397970		00 00 01 55 01 55 ff ff		                      .text $00,$00,$01,$55,$01,$55,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$01,$01,$00
>397978		ff ff ff ff ff 01 01 00
>397980		00 00 01 55 55 55 ff ff		                      .text $00,$00,$01,$55,$55,$55,$FF,$FF,$FF,$FF,$FF,$FF,$01,$FF,$FF,$01
>397988		ff ff ff ff 01 ff ff 01
>397990		00 00 00 01 55 55 55 ff		                      .text $00,$00,$00,$01,$55,$55,$55,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$01
>397998		ff ff ff ff ff ff ff 01
>3979a0		00 00 00 00 01 55 55 55		                      .text $00,$00,$00,$00,$01,$55,$55,$55,$55,$55,$01,$FF,$FF,$55,$01,$00
>3979a8		55 55 01 ff ff 55 01 00
>3979b0		00 00 00 00 00 01 01 01		                      .text $00,$00,$00,$00,$00,$01,$01,$01,$01,$01,$55,$FF,$55,$01,$00,$00
>3979b8		01 01 55 ff 55 01 00 00
>3979c0		00 00 00 00 00 00 00 00		                      .text $00,$00,$00,$00,$00,$00,$00,$00,$01,$55,$55,$55,$01,$00,$00,$00
>3979c8		01 55 55 55 01 00 00 00
>3979d0		00 00 00 00 00 00 00 00		                      .text $00,$00,$00,$00,$00,$00,$00,$00,$01,$55,$55,$01,$00,$00,$00,$00
>3979d8		01 55 55 01 00 00 00 00
>3979e0		00 00 00 00 00 00 00 00		                      .text $00,$00,$00,$00,$00,$00,$00,$00,$00,$01,$01,$00,$00,$00,$00,$00
>3979e8		00 01 01 00 00 00 00 00
>3979f0		00 00 00 00 00 00 00 00		                      .text $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
>3979f8		00 00 00 00 00 00 00 00
.3ff000						FONT_4_BANK0
>3ff000		00 00 00 00 00 00 00 00		.binary "FONT/Bm437_PhoenixEGA_8x8.bin", 0, 2048
>3ff008		7e 81 a5 81 bd 99 81 7e 3c 7e db ff c3 7e 3c 00
>3ff018		00 ee fe fe 7c 38 10 00 10 38 7c fe 7c 38 10 00
>3ff028		00 3c 18 ff ff 08 18 00 10 38 7c fe fe 10 38 00
>3ff038		00 00 18 3c 18 00 00 00 ff ff e7 c3 e7 ff ff ff
>3ff048		00 3c 42 81 81 42 3c 00 ff c3 bd 7e 7e bd c3 ff
>3ff058		01 03 07 0f 1f 3f 7f ff ff fe fc f8 f0 e0 c0 80
>3ff068		04 06 07 04 04 fc f8 00 0c 0a 0d 0b f9 f9 1f 1f
>3ff078		00 92 7c 44 c6 7c 92 00 00 00 60 78 7e 78 60 00
>3ff088		00 00 06 1e 7e 1e 06 00 18 7e 18 18 18 18 7e 18
>3ff098		66 66 66 66 66 00 66 00 ff b6 76 36 36 36 36 00
>3ff0a8		7e c1 dc 22 22 1f 83 7e 00 00 00 7e 7e 00 00 00
>3ff0b8		18 7e 18 18 7e 18 00 ff 18 7e 18 18 18 18 18 00
>3ff0c8		18 18 18 18 18 7e 18 00 00 04 06 ff 06 04 00 00
>3ff0d8		00 20 60 ff 60 20 00 00 00 00 00 c0 c0 c0 ff 00
>3ff0e8		00 24 66 ff 66 24 00 00 00 00 10 38 7c fe 00 00
>3ff0f8		00 00 00 fe 7c 38 10 00 00 00 00 00 00 00 00 00
>3ff108		30 30 30 30 30 00 30 00 66 66 00 00 00 00 00 00
>3ff118		6c 6c fe 6c fe 6c 6c 00 10 7c d2 7c 86 7c 10 00
>3ff128		f0 96 fc 18 3e 72 de 00 30 48 30 78 ce cc 78 00
>3ff138		0c 0c 18 00 00 00 00 00 10 60 c0 c0 c0 60 10 00
>3ff148		10 0c 06 06 06 0c 10 00 00 54 38 fe 38 54 00 00
>3ff158		00 18 18 7e 18 18 00 00 00 00 00 00 00 00 18 70
>3ff168		00 00 00 7e 00 00 00 00 00 00 00 00 00 00 18 00
>3ff178		02 06 0c 18 30 60 c0 00 7c ce de f6 e6 e6 7c 00
>3ff188		18 38 78 18 18 18 3c 00 7c c6 06 0c 30 60 fe 00
>3ff198		7c c6 06 3c 06 c6 7c 00 0e 1e 36 66 fe 06 06 00
>3ff1a8		fe c0 c0 fc 06 06 fc 00 7c c6 c0 fc c6 c6 7c 00
>3ff1b8		fe 06 0c 18 30 60 60 00 7c c6 c6 7c c6 c6 7c 00
>3ff1c8		7c c6 c6 7e 06 c6 7c 00 00 30 00 00 00 30 00 00
>3ff1d8		00 30 00 00 00 30 20 00 00 1c 30 60 30 1c 00 00
>3ff1e8		00 00 7e 00 7e 00 00 00 00 70 18 0c 18 70 00 00
>3ff1f8		7c c6 0c 18 30 00 30 00 7c 82 9a aa aa 9e 7c 00
>3ff208		7c c6 c6 fe c6 c6 c6 00 fc 66 66 7c 66 66 fc 00
>3ff218		7c c6 c0 c0 c0 c6 7c 00 fc 66 66 66 66 66 fc 00
>3ff228		fe 62 68 78 68 62 fe 00 fe 62 68 78 68 60 f0 00
>3ff238		7c c6 c6 c0 de c6 7c 00 c6 c6 c6 fe c6 c6 c6 00
>3ff248		3c 18 18 18 18 18 3c 00 1e 0c 0c 0c 0c cc 78 00
>3ff258		c6 cc d8 f0 d8 cc c6 00 f0 60 60 60 60 62 fe 00
>3ff268		c6 ee fe d6 c6 c6 c6 00 c6 e6 f6 de ce c6 c6 00
>3ff278		7c c6 c6 c6 c6 c6 7c 00 fc 66 66 7c 60 60 f0 00
>3ff288		7c c6 c6 c6 c6 c6 7c 0c fc 66 66 7c 66 66 e6 00
>3ff298		7c c6 c0 7c 06 c6 7c 00 7e 5a 18 18 18 18 3c 00
>3ff2a8		c6 c6 c6 c6 c6 c6 7c 00 c6 c6 c6 c6 c6 6c 38 00
>3ff2b8		c6 c6 c6 c6 d6 ee c6 00 c6 6c 38 38 38 6c c6 00
>3ff2c8		66 66 66 3c 18 18 3c 00 fe c6 0c 18 30 66 fe 00
>3ff2d8		1c 18 18 18 18 18 1c 00 c0 60 30 18 0c 06 02 00
>3ff2e8		70 30 30 30 30 30 70 00 00 00 10 38 6c c6 00 00
>3ff2f8		00 00 00 00 00 00 00 ff 30 30 18 00 00 00 00 00
>3ff308		00 00 7c 06 7e c6 7e 00 c0 c0 fc c6 c6 c6 fc 00
>3ff318		00 00 7c c6 c0 c6 7c 00 06 06 7e c6 c6 c6 7e 00
>3ff328		00 00 7c c6 fe c0 7c 00 3c 66 60 f0 60 60 60 00
>3ff338		00 00 7e c6 c6 7e 06 7c c0 c0 fc c6 c6 c6 c6 00
>3ff348		18 00 38 18 18 18 3c 00 00 0c 00 1c 0c 0c cc 78
>3ff358		c0 c0 c6 d8 f0 d8 c6 00 38 18 18 18 18 18 3c 00
>3ff368		00 00 ee fe d6 c6 c6 00 00 00 fc c6 c6 c6 c6 00
>3ff378		00 00 7c c6 c6 c6 7c 00 00 00 fc c6 c6 fc c0 c0
>3ff388		00 00 7e c6 c6 7e 06 06 00 00 de 76 60 60 60 00
>3ff398		00 00 7c c0 7c 06 7c 00 18 18 7e 18 18 18 1e 00
>3ff3a8		00 00 c6 c6 c6 c6 7e 00 00 00 c6 c6 c6 6c 38 00
>3ff3b8		00 00 c6 c6 d6 fe c6 00 00 00 c6 6c 38 6c c6 00
>3ff3c8		00 00 c6 c6 c6 7e 06 7c 00 00 fe 0c 18 60 fe 00
>3ff3d8		0e 18 18 70 18 18 0e 00 18 18 18 00 18 18 18 00
>3ff3e8		e0 30 30 1c 30 30 e0 00 00 00 70 9a 0e 00 00 00
>3ff3f8		00 00 18 3c 66 ff 00 00 7c c6 c0 c0 c6 7c 18 70
>3ff408		66 00 c6 c6 c6 c6 7e 00 0e 18 7c c6 fe c0 7c 00
>3ff418		18 24 7c 06 7e c6 7e 00 66 00 7c 06 7e c6 7e 00
>3ff428		38 0c 7c 06 7e c6 7e 00 18 00 7c 06 7e c6 7e 00
>3ff438		00 00 7c c0 c0 7c 18 70 18 24 7c c6 fe c0 7c 00
>3ff448		66 00 7c c6 fe c0 7c 00 70 18 7c c6 fe c0 7c 00
>3ff458		66 00 38 18 18 18 3c 00 18 24 38 18 18 18 3c 00
>3ff468		38 0c 38 18 18 18 3c 00 66 00 7c c6 fe c6 c6 00
>3ff478		18 00 7c c6 fe c6 c6 00 0e 18 fe 60 78 60 fe 00
>3ff488		00 00 7c 1a 7e d8 7e 00 7e d8 d8 de f8 d8 de 00
>3ff498		18 24 7c c6 c6 c6 7c 00 66 00 7c c6 c6 c6 7c 00
>3ff4a8		38 0c 7c c6 c6 c6 7c 00 18 24 c6 c6 c6 c6 7e 00
>3ff4b8		38 0c c6 c6 c6 c6 7e 00 66 00 c6 c6 c6 7e 06 7c
>3ff4c8		66 7c c6 c6 c6 c6 7c 00 c6 00 c6 c6 c6 c6 7c 00
>3ff4d8		18 7c c6 c0 c6 7c 18 00 1e 32 30 78 30 70 fe 00
>3ff4e8		66 3c 18 7e 18 3c 18 00 fc c6 fc c0 cc de cc 0e
>3ff4f8		00 1c 32 30 fc 30 f0 00 0e 18 7c 06 7e c6 7e 00
>3ff508		1a 30 38 18 18 18 3c 00 0e 18 7c c6 c6 c6 7c 00
>3ff518		0e 18 c6 c6 c6 c6 7e 00 66 98 fc c6 c6 c6 c6 00
>3ff528		66 98 e6 f6 de ce c6 00 7c 06 7e c6 7e 00 fe 00
>3ff538		7c c6 c6 c6 7c 00 fe 00 18 00 18 30 60 c6 7c 00
>3ff548		00 00 fe c0 c0 c0 c0 00 00 00 fe 06 06 06 06 00
>3ff558		c0 c0 c0 de 06 0c 1e 00 c0 c0 c0 cc 1c 3e 0c 00
>3ff568		30 00 30 30 30 30 30 00 00 36 6c d8 6c 36 00 00
>3ff578		00 d8 6c 36 6c d8 00 00 aa aa aa aa aa aa aa aa
>3ff588		aa 55 aa 55 aa 55 aa 55 44 22 44 22 44 22 44 22
>3ff598		18 18 18 18 18 18 18 18 18 18 18 f8 18 18 18 18
>3ff5a8		18 18 18 f8 18 f8 18 18 36 36 36 f6 36 36 36 36
>3ff5b8		00 00 00 fe 36 36 36 36 00 00 00 f8 18 f8 18 18
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>3a6bb8		22 58 6b 3a a5 31 c9 09 b0 0d a7 32 f0 09 c9 20
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>3a6bd8		08 5b 68 28 c2 10 e2 20 a2 31 00 74 00 ca d0 fb
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>3a6c08		20 a5 34 85 0a a2 01 00 22 b8 6a 3a a7 32 d0 06
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>3a6c58		a5 34 85 13 22 b8 6a 3a a7 32 f0 26 c9 20 d0 f4
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>3a6c78		f0 bf c2 20 a5 32 85 15 e2 20 a5 34 85 17 e6 31
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>3a6cd8		8f 56 03 00 22 18 11 00 b0 25 e2 20 a2 aa 6d a9
>3a6ce8		3a 48 ab 20 c0 02 af 2e 03 00 20 ea 02 a9 20 20
>3a6cf8		18 00 af 20 03 00 20 ea 02 20 33 02 20 33 02 28
>3a6d08		6b 8b 08 c2 10 e2 20 a5 31 c9 03 f0 0f a2 84 6d
>3a6d18		a9 3a 48 ab 20 c0 02 20 33 02 80 54 c2 20 a5 0d
>3a6d28		8f 21 08 00 a5 0f 8f 23 08 00 20 77 4e a5 11 8f
>3a6d38		50 03 00 a5 13 8f 52 03 00 a5 15 8f 58 03 00 a5
>3a6d48		17 8f 5a 03 00 22 1c 11 00 b0 25 e2 20 a2 94 6d
>3a6d58		a9 3a 48 ab 20 c0 02 af 2e 03 00 20 ea 02 a9 20
>3a6d68		20 18 00 af 20 03 00 20 ea 02 20 33 02 20 33 02
>3a6d78		28 ab 6b 5c 33 22 3a 6b 00 00 00 00 42 61 64 20
>3a6d88		61 72 67 75 6d 65 6e 74 73 0d 0d 00 55 6e 61 62
>3a6d98		6c 65 20 74 6f 20 73 61 76 65 20 66 69 6c 65 3a
>3a6da8		20 00 55 6e 61 62 6c 65 20 74 6f 20 6c 6f 61 64
>3a6db8		20 66 69 6c 65 3a 20 00 0d 20 20 50 43 20 20 20
>3a6dc8		20 20 41 20 20 20 20 58 20 20 20 20 59 20 20 20
>3a6dd8		20 53 50 20 20 20 44 42 52 20 44 50 20 20 20 4e
>3a6de8		56 4d 58 44 49 5a 43 0d 00 41 43 44 46 47 4a 48
>3a6df8		4c 4d 52 3b 53 54 56 57 58 3e 3f 00 18 fb 08 c2
>3a6e08		20 48 a9 00 08 5b 68 28 08 e2 20 48 a9 00 48 ab
>3a6e18		68 28 c2 30 20 43 6e a9 ff fe 1b 08 e2 20 48 a9
>3a6e28		3a 48 ab 68 28 a2 3c d2 20 c0 02 08 e2 20 48 a9
>3a6e38		00 48 ab 68 28 4c 33 22 4c 40 6e 08 20 b5 01 20
>3a6e48		24 46 28 60 00 00 00 00 00 00 00 00 00 00 00 00
>3a6e58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
;		...repeated 1561 times (24976 bytes)...
>3acff8		00 00 00 00 00 00 00 00 30 31 32 33 34 35 36 37
>3ad008		38 39 41 42 43 44 45 46 2b 00 2d 00 2a 00 2f 00
>3ad018		4d 4f 44 00 5e 00 3c 00 3d 00 3e 00 4e 4f 54 00
>3ad028		41 4e 44 00 4f 52 00 28 00 29 00 52 45 4d 00 50
>3ad038		52 49 4e 54 00 4c 45 54 00 47 4f 54 4f 00 45 4e
>3ad048		44 00 49 46 00 54 48 45 4e 00 45 4c 53 45 00 47
>3ad058		4f 53 55 42 00 52 45 54 55 52 4e 00 46 4f 52 00
>3ad068		54 4f 00 53 54 45 50 00 4e 45 58 54 00 44 4f 00
>3ad078		4c 4f 4f 50 00 57 48 49 4c 45 00 55 4e 54 49 4c
>3ad088		00 45 58 49 54 00 43 4c 52 00 53 54 4f 50 00 50
>3ad098		4f 4b 45 00 50 4f 4b 45 57 00 50 4f 4b 45 4c 00
>3ad0a8		43 4c 53 00 52 45 41 44 00 44 41 54 41 00 52 45
>3ad0b8		53 54 4f 52 45 00 44 49 4d 00 43 41 4c 4c 00 3c
>3ad0c8		3d 00 3e 3d 00 3c 3e 00 2d 00 4c 45 4e 00 50 45
>3ad0d8		45 4b 00 50 45 45 4b 57 00 50 45 45 4b 4c 00 43
>3ad0e8		48 52 24 00 41 53 43 00 53 50 43 00 54 41 42 00
>3ad0f8		41 42 53 00 53 47 4e 00 48 45 58 24 00 44 45 43
>3ad108		00 53 54 52 24 00 56 41 4c 00 4c 45 46 54 24 00
>3ad118		52 49 47 48 54 24 00 4d 49 44 24 00 52 55 4e 00
>3ad128		4e 45 57 00 4c 4f 41 44 00 4c 49 53 54 00 44 49
>3ad138		52 00 42 4c 4f 41 44 00 42 52 55 4e 00 42 53 41
>3ad148		56 45 00 44 45 4c 00 53 41 56 45 00 52 45 4e 41
>3ad158		4d 45 00 43 4f 50 59 00 4d 4f 4e 49 54 4f 52 00
>3ad168		47 45 54 00 49 4e 50 55 54 00 53 45 54 42 4f 52
>3ad178		44 45 52 00 54 45 58 54 43 4f 4c 4f 52 00 53 45
>3ad188		54 42 47 43 4f 4c 4f 52 00 53 45 54 44 41 54 45
>3ad198		00 47 45 54 44 41 54 45 24 00 53 45 54 54 49 4d
>3ad1a8		45 00 47 45 54 54 49 4d 45 24 00 47 52 41 50 48
>3ad1b8		49 43 53 00 53 45 54 43 4f 4c 4f 52 00 42 49 54
>3ad1c8		4d 41 50 00 43 4c 52 42 49 54 4d 41 50 00 50 4c
>3ad1d8		4f 54 00 4c 49 4e 45 00 46 49 4c 4c 00 53 50 52
>3ad1e8		49 54 45 00 53 50 52 49 54 45 41 54 00 53 50 52
>3ad1f8		49 54 45 53 48 4f 57 00 54 49 4c 45 53 45 54 00
>3ad208		54 49 4c 45 4d 41 50 00 54 49 4c 45 53 48 4f 57
>3ad218		00 54 49 4c 45 41 54 00 4d 45 4d 43 4f 50 59 00
>3ad228		4c 49 4e 45 41 52 00 52 45 43 54 00 0d 52 45 41
>3ad238		44 59 0d 00 43 32 35 36 20 46 6f 65 6e 69 78 20
>3ad248		42 41 53 49 43 38 31 36 20 76 30 2e 31 2e 30 2d
>3ad258		61 6c 70 68 61 2b 32 36 33 0d 00
>3b0000						.align 256
.3b0000						CREDITS_TEXT
>3b0000		54 68 69 73 20 69 73 20		                .text "This is the credits screen!"
>3b0008		74 68 65 20 63 72 65 64 69 74 73 20 73 63 72 65
>3b0018		65 6e 21
>3b001b		20 20 20 20 20 20 20 20		                .fill 128 - len("This is the credits screen!"), $20
>3b0023		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
;		...repeated 4 times (64 bytes)...
>3b0073		20 20 20 20 20 20 20 20 20 20 20 20 20
>3b0080		49 20 77 6f 75 6c 64 20		                .text "I would like to thank the academy."
>3b0088		6c 69 6b 65 20 74 6f 20 74 68 61 6e 6b 20 74 68
>3b0098		65 20 61 63 61 64 65 6d 79 2e
>3b00a2		20 20 20 20 20 20 20 20		                .fill 128 - len("I would like to thank the academy."), $20
>3b00aa		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
;		...repeated 4 times (64 bytes)...
>3b00fa		20 20 20 20 20 20
>3b0100						                .text ""
>3b0100		20 20 20 20 20 20 20 20		                .fill 128 - len(""), $20
>3b0108		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
;		...repeated 6 times (96 bytes)...
>3b0178		20 20 20 20 20 20 20 20
>3b0180		50 72 65 73 73 20 61 6e		                .text "Press any key to go back..."
>3b0188		79 20 6b 65 79 20 74 6f 20 67 6f 20 62 61 63 6b
>3b0198		2e 2e 2e
>3b019b		20 20 20 20 20 20 20 20		                .fill 128 - len("Press any key to go back..."), $20
>3b01a3		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
;		...repeated 4 times (64 bytes)...
>3b01f3		20 20 20 20 20 20 20 20 20 20 20 20 20
>3b0200		20 20 20 20 20 20 20 20		                .fill 128 * 60,$20
>3b0208		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
;		...repeated 478 times (7648 bytes)...
>3b1ff8		20 20 20 20 20 20 20 20
>3b2000						.align 256
>3b2000		f3 f3 f3 f3 f3 f3 f3 f3		CREDITS_COLOR   .fill 128 * 64, $F3
>3b2008		f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3
;		...repeated 510 times (8160 bytes)...
>3b3ff8		f3 f3 f3 f3 f3 f3 f3 f3

;******  End of listing
