Memory device UKNTS .

 

It is recommended to read part and 1 to 3 (even if they are not anything obvious) .

It is also recommended to simultaneously watch the circuit diagram 3.059.316 E3

 

First of all, some general characteristics of the UKSC memory:

This, and all that is written below, is the ultimate truth (even if contradictory information is written somewhere in the instructions to the UKSC).

 

 

 

Organization of RAM and ROM , the core chipset UKNTS.

 

RAM is represented by three "plans" of 64kb each. It is made accordingly, in the form of three sets of 8 chips each, each with a capacity of 64 kbps. Plans are numbered 0, 1, and 2.

Plan 0 - DS5-12 chips (see page 2 of the diagram),

Plan s 1 and 2 - chip the DS 13-20, the DS 21-28 .

 

ROM is implemented by four banks of 8kb each, one of which can be switched off (and replaced with an external ROM) directly during normal operation and without resetting the computer . All of them can be disabled only on condition that the ROM is physically removed (each bank can be seized separately - because each of them is represented by its own chip). See also comments on Part 3.

Bank 0 is implemented on the DS 4 chip ( see pages 1 and 2 of the diagram ) ,

Banks 1,2,3 are implemented on DS1-3 microcircuits.

 

The core of the chipset of the motherboard of the UKNTs consists of three specialized microcircuits that implement: “1” - the trunk of the peripheral processor (chip D1) , “2” - the trunk of the central processor ( chip D 3) , “3” - the bridge between “1” and “ 2 ”chips (hereinafter we will briefly call them chipset 1, chipset 2 and chipset 3) .

 

Chipset 1 (chip D 9 ) is directly connected to 64kb of RAM 0 and 32kb of ROM. It is also directly connected to the PCB. This allows the software to potentially directly use 64kb of RAM of plan 0 and 32kb of ROM. However, in the direct addressing, only the lower 32kb of RAM of plan 0 is used (for details, see below). The upper 32kb are given to the video adapter. However, as already mentioned above (as well as in Part 3) , these top 32kb can be replaced by ROM banks (with the ROM physically removed). It is important that sequential bytes from the RAM of plan 0 are arranged in pairs in 16-bit words, which is also true for ROM.

Further, Chipset 1 is also directly connected to the D15 buffer , to which (on its other side) external devices can be connected via 2 expansion slots (XS1 and XS2 connectors on the diagram e, page 1 ) . In particular, it can be 24 + 24kb of external ROM, a hard disk controller, mouse, joystick or modem controllers.

 

Chipset 2 ( chip D 8 ) is directly connected to 64 + 64kb of RAM plans 1 and 2. This potentially allows the CPU to directly use 128kb of RAM. However, since the processor has only a 16-bit address bus, and there is no mechanism for switching pages on its backbone, in reality, only the lower 32kb of plan 1 and the lower 32kb of plan 2 are available for direct addressing. The upper 32 + 32kb of these plans are given to the video adapter. In order to organize bytes into words, bytes from plan 1 are always substituted for even addresses (i.e., the least significant byte of the word), and bytes from plan 2 - onto odd addresses and addresses (i.e. the highest byte of the word) - this shows up difference from the use of RAM plan 0 on the part of the PP (see above about Chipset 1)

 

Chipset 3 ( chip D 10) is included between chipsets 1 and 2. According to the scheme, you can trace that , one way or another , it connects to all 192kb of RAM - this is an important circumstance, because It is on this chip that the video adapter and the direct memory access mechanism are implemented . The direct memory access controller is presented both from the CPU and from the PC side and it is presented as a peripheral device (i.e., communication with it is carried out via input-output ports). Drawing in the memory of the video adapter is made, it is already clear, it is through this mechanism. Moreover, access is allowed for both the PC and the CPU (although in normal operation, only the PC is responsible for rendering characters on the screen).

An important circumstance is that the direct memory access mechanism allows the PC to access all 192kb of RAM: 64kb of “ours” and 128kb of “aliens,” while the CPU can see RAM only in plans 1 and 2 through this mechanism (probably , this is dictated by security considerations - otherwise a “hung” or “illiterate” user program could spoil the contents of the lower 32kb of plan 0, which are the system RAM of the peripheral processor).

 

All of the above can be depicted in the picture:

 

1. memory addressing from the mains of two processors:

------------------------- ----------------------- || | - ------- --------------------- -----

|          Mainline software (chipset 1) |||     Highway PP (chipset 2) |          

------------------------------------------------ || | - ------- --------------------- -----

|          | Cell number | RAM        cell number |     |                          

| PP address | ROM | --------------- ||| --------- ------- - | CPU Address |                    

|               | Plan 0 || | Plan 1 | Plan 2 |          |                        

--------------------- --------------------------- || | - ------- --------------------- -----

| 177776/177777 | 077776/077777 | | || 077777 | 077777 | 177776/177777 |

| ............. | ............. | | || ...... | ...... | ............. |

| 100002/100003 | 000002/000003 | | || 040001 | 040001 | 100002/100003 |

| 100000/100001 | 00000 0 /00000 1 | | || 040000 | 040000 | 100000/100001 |

| 077776/077777 |               | 077776/077777 | || 037777 | 037777 | 077776/077777 |

| ............. |               | ............. | || ...... | ...... | ............. |

| 000002/000003 |               | 000002/000003 | || 000001 | 000001 | 000002/000003 |

| 000000/000001 |               | 000000/000001 | || 000000 | 000000 | 000000/000001 |

------------------------------------------------ || | -------- --------------------- -----

Notes:

 

2. memory addressing through direct memory access

----------------------------------------

| |            RAM |

| RAP Address | -------------------------- |

| | Plan 0 | Plan 1 | Plan 2 |

----------------------------------------

| 177777 | 177777 | 177777 | 177777 |

| ...... | ...... | ...... | ...... |

| 100001 | 100001 | 100001 | 100001 |

| 100,000 | 100,000 | 100,000 | 100,000 |

| 077777 | 077777 | 077777 | 077777 |

| ...... | ...... | ...... | ...... |

| 000001 | 000001 | 000001 | 000001 |

| 000000 | 000000 | 000000 | 000000 |

----------------------------------------

Notes:

 

 

 

RAP device .

 

As mentioned above, the RAP mechanism is made in the form of an internal peripheral device (as part of the chipset 3) . It is available both from the PC trunk and from the CPU bus through a set of I / O ports. In other words, from the point of view of chipsets 1 and 2, the DAC device is an external device.

 

Registers for working with the DAP device on the main trunk:

177 010 - [ R / W ] in this register must place 16-bit first physical address "horizontal" triple RAM cells ( three parallel cell of three RAMs plans)

177 012 - [ R / W ] 8-bit data (low byte) of the memory cell plan and 0 . When reading, the high byte of the register always contains zeros , while writing, it is ignored.

177 014 - [ R / W ] 16-bit data from RAM cells plan s 1 and 2 (from Box 2 is substituted in plan senior register bytes, from plan 1 - in Jr.).

 

Registers for working with the DAP device on the CPU backbone:

176640 - [ R / W ] register for setting a 16-bit physical address of a pair of RAM cells from plans 1 and 2,

176642 - [ R / W ] 16-bit data from RAM cells of plans 1 and 2 (a cell from plan 2 is inserted into the high byte of the register, from plan 1 into the low byte).

Plan 0 RAM is not available even for the CPU through the RAP mechanism (see above).

 

It is important to note that the operation of the DAP device, the operation of the video adapter and the operation of both processors occur in parallel. In particular, the CPU can execute some program, while the CPU loads other sections of program code in its RAM.

 

It is also significant that the address register 177010 on the mains and the address register 176640 on the mains are not identical! In other words, in fact, the RAP mechanism consists of two completely independent units, one of which is responsible for access from the main trunk to RAM in plans 0.1 and 2, and the other for access from the CPU main to RAM in plans 1 and 2. Of course, they can work in parallel, which, in particular, allows you to organize a high-speed buffered data exchange between the CPU and the PC (with the initiative of the PC), in contrast to the exchange of data via an unbuffered hardware communication channel (see below). This technique, however, is to a certain extent used in the standard procedures of the UKSC Monitor.

 

Notes :

 

Writing Values ​​to 177010,177012,177014

020000 012737 ; MOV   # 123456, @ # 177010

020002 123456 ;

020004 177010;

020006 112737; MOVB # 034, @ # 177012

020010 000034;

020012 177012;

020014 012737; MOV   # 01 7035 , @ # 177014

020016 017035;

020020 177014;

Here, plot 020014-020020 is equivalent to the following:

020014 112737; MOVB # 035, @ # 177014

020016 000035;

020020 177014;

020022 112737; MOVB # 036, @ # 177015

020024 000036;

020026 177015;

 

Reading 177012.177014 values ​​into registers R 0, R 1

020000 012737; MOV   # 123456, @ # 177010

020002 123456;

020004 177010;

020006 11 3 7 00 ; MOVB @ # 177012 , R0

020010 177012 ;

020012 013701 ; MOV @ # 177014, R1

020014 177014;

 

 

 

Video adapter

 

The video adapter is described in detail in part 5.

 

 

 

Communication channels CPU-PP.

 

As mentioned above (see also part 1), the chipset 3 implements another peripheral device - a cluster of communication channels between the CPU and the software. There are three of these channels ( K 0, K 1 and K 2 are numbered ), and they are all 8-bit. In principle, all channels are absolutely equal with the only difference being that channels K0 and K1 are bidirectional, and channel K2 is unidirectional (transmits data from the CPU to the PC). However, the standard firmware of the ROM ROM regulates the use of each of these channels for very specific purposes. All channels contain register buffers (each for 1 byte) - a total of 5 buffers.

 

Channel K0 - used to emulate the user console by the peripheral processor.

ASCII codes of characters for printing on the screen are transmitted from the CPU to the PC (the text mode in the UKSC is emulated by the graphic mode).

ASCII codes of pressed keys are transmitted from the PC to the CPU .

An example of the use of channel K0 can be found in the demonstration program for communication between the UKNTs and PC via the COM port.

 

Channel K1 - if memory serves me right, it is used to access the parallel port (printer port) from the CPU side in transit through the PC. The parallel port in the UKSC is implemented as a full-fledged bi-directional 12-bit port.

 

Channel K2 is used for programming the PCB according to the instructions of the user program executed in the CPU memory.

 

The rules for working with these channels are quite complex and are described in a separate book from the documentation for the UKSC, which I, unfortunately, have not yet scanned.

Original text

Ядро чипсета материнской платы УКНЦ состоит из трех специализированных микросхем, которые реализуют: «1» – магистраль периферийного процессора (микросхема D1), «2» – магистраль центрального процессора (микросхема D3), «3»– мост между «1» и «2» микросхемами (далее будем их кратко называть чипсет 1, чипсет 2 и чипсет 3).