Program uploads image embedded P ZU P n = 3 1.5 kb .
It is recommended that you first read Part 1.
A small comment:
Card RAM + ROM of the peripheral processor = 32 + 32 kb
------------------------------------ ----- -
| Address | KB | Use | Thu | ZPS |
------------------------------------ ------
| 177776/177777 | | ? | W / w | W / w |
| ............. | 0.5 | ? | W / w | W / w |
| 17 7 002 / 17 7 003 | ROM | ? | W / w | W / w |
| 17 7 000 / 17 7 001 | | ? | W / w | W / w |
---------------------------------- - ------
| 17 6 776 / 17 6777 | | ROM | ROM | X |
| ............. | 31.5 | ROM | ROM | X |
| 1 0 0002/1 0 0003 | ROM | ROM | ROM | X |
| 1 0 0000/1 0 0001 | | ROM | ROM | X |
---------------- -------------------- ------
| 07 7776/ 07 7777 | | RAM | RAM | RAM |
| ............. | 32 | RAM | RAM | RAM |
| 000002/000003 | RAM | RAM | RAM | RAM |
| 000000/000001 | | RAM | RAM | RAM |
---------------- -------------------- ------
Thus , all 32 KB of RAM and 31.5 KB of peripheral processor ROM are available .
And nteres are primarily 31,5k used the code located in the P memory . However, 32kb of RAM of the peripheral processor also contains useful information (in any case, the part of it that contains graphic character encodings, as well as the settings table for the graphic adapter) .
Before proceeding with the description of the unloading procedure of 31.5 kb of ROM, I will answer two questions that, most likely, have already arisen:
1) how to read the remaining 0.5kb of ROM ;
2) how is the addressing of an external removable ROM plugged into one of the two expansion slots (an external ROM module has a volume of 24kb, two such modules can be connected to the machine at the same time).
Answers (briefly):
1) the upper 0.5k b ROM P P are not available at all (at least I think so) ;
2) PP ROM is organized in the form of memory banks, with a capacity of 8 kb (a total of 4 banks a ). B ipset peripheral processor team periferifnogo same processor can svapirovat these memory banks in such a way that: 1) The top three banks ROM №1 , №2 , №3 always stay in place, 2) a first ROM bank number 0 (in addresses 100000 -117777) can be used either built-in or replaced by one of six banks of external ROM (three in the first expansion slot and three more in the second) . This allows you to take turns connecting the overlay modules of the external ROM in pieces of 8kb. In addition, in debug mode (in my opinion, only with your own ROM removed), it is possible to replace any of the 4 ROM banks (and, in any combination) with the corresponding RAM bank of the video adapter (see part 4).
* Detailed answers - see in the file describing the memory device of the UKSC (part 4) .
Thus, in a nutshell, the algorithm is as follows:
1) we introduce a program into RAM RAM that copies , using direct access to the CPU memory , the contents of 31.5 kb P RAM P P to any area of USER mode CPU RAM with the same size of 31.5 kb;
2) in the memory of the CPU RAM (USER mode RAM) we enter a program that transfers 31.5 kb of clone (also located in the USER mode RAM ) through the “Joint C2” port to the PC COM port .
* The “Joint C2” port, as well as the “Local Area Network” port, are the only two external ports in the UKSC that are accessible from the main processor trunk. The remaining external I / O ports are accessible from the peripheral processor backbone.
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1) carry out a full reset of the computer
2) in the PP monitor, start the PP program
3) in the CPU monitor, start the CPU program
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PP program
P forwards 16,128 words of ROM ROM to addresses 100000-176777 in RAM RAM to addresses 010000-106777 .
address macro code
020000 012.7 thousand MOV # 100000, R0 ; PP ROM read in addresses 100000-176777
020002 100000
020004 012737 MOV # 004000, @ # 177010 ; write it in the RAM of the CPU to the addresses 010000-106777
020006 004000 ; (010000/2 = 004000)
020010 177010
020012 012701 MOV # 037400, R1 ; we send 037400 words (077000 bytes)
020014 037400
L1 :; repeat
020016 012037 MOV (R0) +, @ # 177014 ; forward the next word from the ROM
020020 177014 ; at address R0 in the RAM of the CPU at the address { 177010 } * 2
; and perform an offset of 2 bytes R 0: = R 0 + 2
020022 005237 INC @ # 177010 ; perform offset
020024 177010 ; { 177010 } * 2 : = ({ 177010 } + 1) * 2
020026 077105 SOB R 1, L 1 ; decrease the word counter R 1: = R 1-1
; until transferred 037,400 words (077,000 bytes )
020030 000000 HALT ; end
Before starting it is necessary to check that PSW = 000200 (otherwise, there may be a failure in the control of the RAP device if the program is interrupted by an interrupt that draws characters on the screen) .
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CPU program
It transfers 32256 bytes of the image of the ROM ROM from the addresses 100000-176777 , uploaded to the USER- RAM RAM at addresses 010000-106777 , to the data port of the source “ Joint C2 ”.
address macro code
001000 012700 MOV # 010000, R0 ; we send the contents of the RAM of the CPU
001002 010000 ; at the addresses 010000-106777
001004 012701 MOV # 077000, R1 ; send 077000 bytes (037400 words)
001006 077000
L2 :; repeat
L3: ; repeat
001010 105737 TSTB @ # 176574 ; check source readiness
001012 176574 ; (bit # 7 = 1) of junction C2
001 014 100 375 BPL L3 ; until the source is ready (bit # 7 = 1)
001016 112037 MOVB (R0) +, @ # 176576 ; forward the next byte of the image ROM ROM PP
001020 176576 ; In Joint C2
; and perform an offset of 1 byte R0: = R0 + 1
001022 077106 SOB R1, L2 ; decrease the byte counter R 1: = R 1-1
; until 077000 bytes (037400 words) transmitted
0 01024 000000 HALT ; end
Before starting it is necessary to check that PSW = 000200 (otherwise, the program may crash due to the transition to processing an unexpected interrupt) .
Program run time 32256 bytes / (9600 baud / 11 bits) = 37 sec.
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