Z80 Assembly programming for the Amstrad CPC

The CPC was the 8 bit I grew up with... while slower in some ways than the C64, it had far superior graphical capabilities to the ZX Spectrum, and usually beats the MSX for graphical speed because of it's smaller screen footprint (16k on the CPC to 24k on the MSX) and its CRTC graphics chip is favoured by the modern clever demo authors... While the budget tape-based 464 machine had 64k, the disk system - the 6128 - has 128k and a disk system... and after market upgrades can give the machine up to 576k There were two major generations of the CPC, the regular version, and the version released in the 90... the CPC+, which has has hardware sprites, enhanced color

CPC 464/664/6128 CPC+ / GX4000 Cpu 3.5mhz Z80 3.5mhz Z80 Ram 64k+ (576k max) 64k+ (576k max) Screen Ram 16k 16k Resolution 2-color 640x200 640x200 Resolution 4-color 320x200 / 256x192 320x200 / 256x192 Resolution 16-color 160x200 160x200 Hardware Sprites none 16 sprites 16x16 @ 16 color Sound chip AY 3 channel AY 3 channel Cartridge Rom none 512k Joystick  2 joysticks UDLR + 3 fire 2 joysticks UDLR + 2 fire

ChibiAkumas Tutorials:

Useful Documents!
CPC464_Firmware_1984_AMSOFT - The official breakdown of the rom functions
CRTC - Details of the amstrad CPC CRTC hardware
Amstrad Firmware guide - Pdf documenting the CPC firmware calls
CPC Firmware Guide - Detailed info on how to use the CPC hardware and firmware
Basic Manual - You'll want to know at least enough basic to do calls and operate the computer
AY sound chip PDF - Manual for the sound chip (Warning! Reg-numbers are in OCTAL! R10 is actually Reg 8)
CPC Firmware disassembly - If you can't find what you need elsewhere, you can always look at the source code!

Memory Map

OUT/IN Port Numbers

The Gate array is at port &7Fxx.. It can be accessed by loading B with &7F and performing 'OUT (C),C' or 'OUT (C),A'

Extra banks continue in the same way:

... And so on!

* This bank mode may not work on all hardware

CRTC - Registers

Here is a pictorial representation of the screen registers function:

CPC Palette

Each color has a firmware (basic) number and a hardware number (used with OUT)

Both are shown below in the format Firmware (0-26) - Hardware  (40h-5Fh)

The pixel bits are in different orders, depending on screen mode.
In the chart below: Numbers are the bit number, A-Z are the pixels contained in the byte.

Screen Memory

Not all 16K of the screen is used... The screen memory layout is split into strips of character blocks as shown below:

256x192 'speccy screen'

The CPC's 320x200 screen is big, but most other systems used only 256x192, so this is often used by games as it makes things easier to port. It also means the VRAM movement commands can only update the L part of the HL address, which increases speed a little too. We send a sequence of values to the CRTC chip to set up the screen layout. The 256x192 screen is 12k, but the CPC 'spreads' it over 16k, leaving some 512 byte blocks spare... we'll can use some of these for our work data! Free areas:  &C600-&C7FF ;&200 *8 = &1000 free  &CE00-&CFFF  &D600-&D7FF  &DE00-&DFFF  &E600-&E7FF  &EE00-&EFFF  &F600-&F7FF  &FE00-&FFFF

The lines of the screen are split into two 'halves', these fill the two 16k banks at &8000-&BFFF and &C000-&FFFF Lines 0-127 start at memory address base &8200 Lines 128-271 start at memory address base &C000 The formulas we need to use to move around memory are a bit more complex for Overscan which will make 'half tile' moves almost impossible, at least implausible for a example of this scope. With a 256 pixel, 64 byte wide screen we only needed to update L as we moved across the screen. But now, because our screen is 96 bytes wide, we will need to update H and L, at least when we move a full tile, the odd (mid tile) moves we can still just update L Moving down a line is the same as before, we add &0800 to HL, but moving over the 8 line boundary (down a tile) is more complex, as we have to cope with the 'jump' between the two banks (over address &B7FF we have to jump to &C000)

A 384x272 @ 4 color screen should be about 25k, but it actually covers 31k (&8200-&FEC0) The reason for this 'Discrepancy' is that there are gaps which are not used by the pixel data, which we can use for our work data - which may be important when half our 64k ram is used by the screen!!! Because the second bank has more screen lines (144), the &C000-&FFFF area has smaller unused areas.

Bank 1 free areas: &8000-&81FF &8800-&89FF &9000-&9FFF &9800-&99FF &A000-&AFFF &A800-&A9FF &B000-&BFFF &B800-&B9FF Bank 2 free areas: &C6C0-&C7FF &CEC0-&CFFF &D6C0-&D7FF &DEC0-&DFFF &E6C0-&E7FF &EEC0-&EFFF &F6C0-&F7FF &FEC0-&FFFF

We need to use an alternative set of CRTC settings to define our larger screen, and strange memory layout!

Turning on CPC+ features, and setting the Palette

The CPC+ has a special bank of memory (Asic registers) - These contain the palette and other CPC+ feature at the memory address &4000-7FFF There is a special sequence to unock the CPC+ Asic we OUT it to &BC Once we've done this we can page in the ASIC with an OUT to &7FB8, we can page it out again with an OUT to &7FA0 CPC+ Colors are defined by 2 bytes from address &6400+ in the ASIC registers (CPC+ special ram)  &0000   &0008   &000F     &0800   &0808   &080F     &0F00   &0F08   &0F0F  &0080 &0088 &008F &0880 &0888 &088F &0F80 &0F88 &0F8F &00F0 &00F8 &00FF &08F0 &08F8 &08FF &0FF0 &0FF8 &0FFF NOTE: When using the ASIC memory, We should make sure that we paged out any extended 128k banks from the &4000-&7FFFF range, as it can cause problems using the plus registers while also paging memory in from 128k ram upgrades. Mode C1/C3 are OK to use as they  page in at &C000. Of  course you can use the extra memory during 'normal times' when the CPC+ ASIC memory is not in use Each color definition is 2 bytes, and there are definitions for the main 16 colors, the border, and CPC+ Hardware Sprites From To Purpose &6400 &641F Colors 0-15 &6420 &6421 Border &6422 &643F Sprite colors 1-15 (0 is transparent) We send two bytes in the format &-GRB ... where the - nibble is unused, G is Green, R is Red and B is blue

CPC+ Hardware sprites

The Amstrad CPC has 16 hardware sprites... each is 16x16

Ypos is 2 bytes, in little endian format. Ypos should be between -64 to +200 (0 is topmost visible pixel)

ASIC RAM and Cartridge ROM on the CPC+:

Asic Ram, when enabled appears at &4000-&7FFF, but we also have cartridge ROM On a CPC+ the Cartrige ROM has 32 banks... numbered 0-31... Banks 0-7 are intended to act as system ROM, appearing between &0000-&3FFF... however ANY bank (0-31) can be paged in at &C000-&FFFF - the same area as screen memory! Even better, if we WRITE to this area - it will be written to the screen RAM through the rom, so we don't need to page out the ROM to write data to the screen! Setting a rom bank is easy, we write the ROM we want to port &DF... values 0-7 will set the Low rom area number... setting the High rom area is done by adding 128 to the rom we want, and OUTing it to &DF Once we've selected it we still need to enable the rom, and we do this by writing to Bit 3 of the Gate array!

Area  Normal mode  Asic Regs ON   Low ROM ON  High ROM on  &0000 RAM_0 RAM_0 Cart 0-7 RAM_0 &4000 RAM_1 Asic RAM RAM_1 RAM_1 &8000 RAM_2 RAM_2 RAM_2 RAM_2 &C000 RAM_3 RAM_3 RAM_3 Cart 0-31

To detect a CPC Plus, we send the PLUS sequence, and turn on the ASIC ram.. .if nothing happened we don't have a CPC+... we can use this fact to detect a CPC!

While you can write to ASIC ram just like normal memory, don't rely on being able to read from it! The development of ChibiAkumas ran into a problem, because reading the CPCPlus interrupt line from the ASIC worked on emulators... but not real hardware! It's probably best to assume you can't read back any writable ASIC values!

Detecting the CPC+ and RAM:

So to detect RAM and the PLUS ASIC, we need to set a byte in our normal memory, turn on the feature (RAM or ASIC)... and WRITE to the same location - then turn off the feature... If the byte we wrote isn't there, then we know the feature does not exist! In this code we'll use &69 as a byte that we'll write to the test location, and CPL to flip the bits of the location when we test.

Keyboard Matrix

AY Sound Chip:

Firmware Call List

Amstrad Links